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INTEGRATED CIRCUITS
74AVC16334A
16-bit registered driver with
inverted register enable and
Dynamic Controlled Outputs (3-State)
Product specification
Supersedes data of 2000 May 02
2000 Aug 03
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
FEATURES
74AVC16334A
PIN CONFIGURATION
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A/5/7.
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed
degradation
• Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
• Power off disables 74AVC16334A outputs, permitting Live
Insertion
• Integrated input diodes to minimize input overshoot and
undershoot
• Full PC133 solution provided when used with PCK2509S or
PCK2510S and CBT16292
DESCRIPTION
The 74AVC16334A is a 16-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor (Live
Insertion).
OE
1
48
Y0
2
47
A0
Y1
3
46
A1
GND
4
45
GND
Y2
5
44
A2
Y3
6
43
A3
VCC
7
42
VCC
Y4
8
41
A4
Y5
9
40
A5
GND
10
39
GND
Y6
11
38
A6
Y7
12
37
A7
Y8
13
36
A8
Y9
14
35
A9
GND
15
34
GND
Y10
16
33
A10
Y11
17
32
A11
VCC
18
31
VCC
Y12
19
30
A12
Y13
20
29
A13
GND
21
28
GND
Y14
22
27
A14
Y15
23
26
A15
NC
24
25
LE
A Dynamic Controlled Output (DCO) circuitry is implemented to
support termination line drive during transient. See the graphs on
page 8 for typical curves.
CP
SH00167
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.0 ns; CL = 30 pF.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
An to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
tPHL/tPLH
Propagation delay
LE to Yn;
CP to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
CI
Input capacitance
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
TYPICAL
UNIT
2.5
1.7
1.5
ns
2.7
2.0
1.6
ns
3.8
pF
Outputs enabled
25
Output disabled
6
pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
48-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
2000 Aug 03
TEMPERATURE
RANGE
OUTSIDE NORTH
AMERICA
–40°C to +85°C
AVC16334A DGG
2
NORTH AMERICA
DRAWING
NUMBER
SOT362-1
853-2212 24282
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
PIN DESCRIPTION
74AVC16334A
LOGIC SYMBOL (IEEE/IEC)
PIN NUMBER
SYMBOL
24
NC
NAME AND FUNCTION
No connection
OE
1
CP
48
LE
25
EN1
2C3
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23
Y0 to Y15
Data outputs
4, 10, 15, 21, 28, 34, 39,
45
GND
Ground (0 V)
Y0
2
47
A0
7, 18, 31, 42
VCC
Positive supply voltage
Y1
3
46
A1
Output enable input
(active LOW)
Y2
5
44
A2
Y3
6
43
A3
Latch enable input
(active LOW)
Y4
8
41
A4
Y5
9
40
A5
Clock input
Y6
11
38
A6
Y7
12
37
A7
Y8
13
36
A8
Y9
14
35
A9
Y10
16
33
A10
Y11
17
32
A11
Y12
19
30
A12
Y13
20
29
A13
Y14
22
27
A14
Y15
23
26
A15
1
G2
OE
25
LE
48
CLK
47, 46, 44, 43, 41, 40,
38, 37, 36, 35, 33, 32,
30, 29, 27, 26
C3
A0 to A15
Data inputs
LOGIC SYMBOL
OE
11 ∇
1
3D
SH00168
CP
FUNCTION TABLE
INPUTS
OUTPUTS
OE
LE
CLK
A
H
X
X
X
L
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
H
L
H
L or H
X
Y01
LE
A1
D
LE
Y1
CP
H
L
X
Z
↑
TO THE 17 OTHER CHANNELS
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
LOW-to-HIGH level transition
NOTE:
1. Output level before the indicated steady-state input conditions
were established.
SH00202
2000 Aug 03
=
=
=
=
=
Z
3
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
74AVC16334A
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
168-pin SDR SDRAM DIMM
SDRAM
BACK SIDE
FRONT SIDE
74AVC16334A 74AVC16334A 74AVC16334A
PCK2509S or PCK2510S
The PLL clock distribution device and AVC registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00525
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
1.95
2.7
3.6
V
VCC
DC supply voltage
(according to JEDEC Low Voltage Standards)
1.65
2.3
3.0
VCC
DC supply voltage (for low voltage applications)
VI
VO
Tamb
tr, tf
1.2
3.6
V
DC Input voltage range
0
3.6
V
DC output voltage range; output 3-State
0
3.6
DC output voltage range; output HIGH or LOW state
0
VCC
–40
+85
°C
0
0
0
30
20
10
ns/V
Operating free-air temperature range
VCC = 1.65 to 2.3 V
VCC = 2.3 to 3.0 V
VCC = 3.0 to 3.6 V
Input rise and fall times
V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
PARAMETER
SYMBOL
VCC
CONDITIONS
DC supply voltage
IIK
DC input diode current
VI t0
VI
DC input voltage
For data inputs1
IOK
DC output diode current
VO uVCC or VO t 0
VO
DC output voltage; output 3-State
VO
IO
IGND, ICC
Tstg
PTOT
UNIT
–0.5 to +4.6
V
–50
mA
–0.5 to 4.6
V
"50
mA
Note 1
–0.5 to 4.6
V
DC output voltage; output HIGH or LOW state
Note 1
–0.5 to VCC +0.5
V
DC output source or sink current
VO = 0 to VCC
"50
mA
"100
mA
–65 to +150
°C
DC VCC or GND current
Storage temperature range
Power dissipation per package
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125 °C
above +55°C derate linearly with 8 mW/K
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2000 Aug 03
RATING
4
600
mW
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
74AVC16334A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
VCC = 1.2 V
VIH
VIL
VOH
VOL
II
IOFF
IOZ
O
ICC
HIGH level Input voltage
MAX
VCC
–
–
0.65 VCC
0.9
–
VCC = 2.3 to 2.7 V
1.7
1.2
–
VCC = 3.0 to 3.6 V
VCC = 1.65 to 1.95 V
2.0
1.5
–
VCC = 1.2 V
–
–
GND
VCC = 1.65 to 1.95 V
–
0.9
0.35 VCC
VCC = 2.3 to 2.7 V
–
1.2
0.7
VCC = 3.0 to 3.6 V
–
1.5
0.8
VCC = 1.65 to 3.6 V; VI = VIH or VIL;
IO = –100 µA
0 20
VCC0.20
VCC
–
VCC = 1.65 V; VI = VIH or VIL; IO = –4 mA
VCC0.45
VCC0.10
–
VCC = 2.3 V; VI = VIH or VIL; IO = –8 mA
VCC0.55
VCC0.28
–
VCC = 3.0 V; VI = VIH or VIL; IO = –12 mA
VCC0.70
VCC0.32
–
VCC = 1.65 to 3.6 V; VI = VIH or VIL;
IO = 100 µA
–
GND
0 20
0.20
VCC = 1.65 V; VI = VIH or VIL; IO = 4 mA
–
0.10
0.45
VCC = 2.3 V; VI = VIH or VIL; IO = 8 mA
–
0.26
0.55
VCC = 3.0 V; VI = VIH or VIL; IO = 12 mA
–
0.36
0.70
Input
In
ut leakage current
VCC = 3
3.6
6 V;
VI = VCC or GND
–
0.1
2.5
3-State output OFF-state current
VCC = 0 V; VI or VO = 3.6 V
–
0.1
10
VCC = 1.65 to 2.7 V; VI = VIH or VIL;
VO = VCC or GND
–
0.1
5
VCC = 3.0 to 3.6 V; VI = VIH or VIL;
VO = VCC or GND
–
0.1
10
VCC = 1.65 to 2.7 V; VI = VCC or GND; IO = 0
–
0.1
20
VCC = 3.0 to 3.6 V; VI = VCC or GND; IO = 0
–
0.2
40
LOW level Input voltage
HIGH level output voltage
g
LOW level output voltage
g
3 State output OFF-state
3-State
OFF state current
Quiescent supply current
NOTE:
1. All typical values are at Tamb = 25°C.
2000 Aug 03
UNIT
TYP1
5
V
V
V
V
µA
µA
µA
µA
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
74AVC16334A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3 ± 0.3 V
VCC = 2.5 ± 0.2 V
VCC = 1.8 ± 0.15 V
VCC =
1.5 ± 0.1 V
VCC =
1.2 V
MIN
TYP1
MAX
MIN
TYP1
MAX
MIN
TYP1
MAX
MIN
MAX
TYP
UNIT
Propagation
delay
An to Yn
1
0.7
1.5
2.6
0.8
1.7
3.0
1.0
2.5
4.4
1.7
5.3
5.0
Propagation
delay
LE to Yn
2
0.7
1.6
3.2
1.0
2.0
3.3
1.2
2.7
4.8
1.7
6.0
5.3
Propagation
delay
CP to Yn
3
0.7
1.6
2.8
0.8
1.7
3.0
1.0
2.3
3.9
1.4
4.6
4.1
tPZH/tPZL
3-State output
enable time
OE to Yn
6
0.7
1.7
3.4
1.0
2.2
3.8
1.5
3.1
5.3
2.0
6.7
6.0
ns
tPHZ/tPLZ
3-State output
disable time
OE to Yn
6
1.0
2.1
3.7
0.9
2.0
3.9
1.5
3.7
6.5
1.7
7.1
6.1
ns
CP pulse width
HIGH or LOW
3
1.0
–
–
1.2
–
–
2.0
–
–
–
–
–
LE pulse width
LOW
2
1.0
–
–
1.2
–
–
2.0
–
–
–
–
–
Set-up time
An to CP
5
0.2
–0.1
–
0.1
–0.1
–
0.1
–0.1
–
0.1
–
0.0
Set-up time
An to LE
4
0.4
0.1
–
0.5
0.1
–
0.8
0.3
–
1.2
–
1.0
Hold time
An to CP
5
0.6
0.2
–
0.6
0.2
–
0.6
0.2
–
0.6
–
0.1
Hold time
An to LE
4
0.4
0.1
–
0.4
0.1
–
0.3
0.1
–
0.3
–
–0.4
Maximum clock
pulse frequency
3
500
–
–
400
–
–
250
–
–
–
–
–
tPHL/tPLH
tW
tSU
S
th
fmax
ns
ns
ns
NOTE:
1. All typical values are measured at Tamb = 25°C and at VCC = 1.8 V, 2.5 V, 3.3 V.
2000 Aug 03
ns
6
MHz
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
74AVC16334A
ÉÉÉ ÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉÉ
ÉÉÉ
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V RANGE
VI
VM = 0.5 VCC
VX = VOL + 0.300 V
VY = VOH – 0.300 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
An
INPUT
VM
GND
th
th
tSU
tSU
VI
LE
INPUT
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND
VCC < 2.3 V RANGE
VM
GND
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00166
VM = 0.5 VCC
VX = VOL + 0.15 V
VY = VOH – 0.15 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
Waveform 4. Data set-up and hold times for the An input to the
LE input
VI
VI
An
INPUT
VM
CP INPUT
VM
GND
GND
tPHL
tsu
tsu
tPLH
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
th
th
VOH
VI
Yn
OUTPUT
VM
An INPUT
GND
VOL
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00132
VOH
Waveform 1. Input (An) to output (Yn) propagation delay
VM
Yn OUTPUT
VOL
VM
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
VM = 0.5VCC at VCC = 2.3 to 2.7 V
SH00136
tPLH
Waveform 5. Data set-up and hold times for the An input to the
clock CP input
VI
LE INPUT
VM
tW
GND
tPHL
VOH
VM
Yn OUTPUT
VI
VOL
nOE INPUT
NOTE: VM = 0.5 VCC at VCC = 2.3 to 2.7 V
SH00165
VM
GND
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
tPLZ
tPZL
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
1/fMAX
VI
CP INPUT
GND
VM
VOL
VM
tW
tPHZ
tPHL
tPLH
tPZH
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
VOH
Yn OUTPUT
VM
VX
VM
VY
VM
GND
VOL
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
outputs
enabled
SH00135
Waveform 3. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
outputs
disabled
outputs
enabled
SH00137
Waveform 6. 3-State enable and disable times
2000 Aug 03
7
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
TEST CIRCUIT
74AVC16334A
GRAPHS
S1
3.5
RL
VO
VI
PULSE
GENERATOR
2 * VCC
Open
GND
VOL OUTPUT VOLTAGE (V)
VCC
D.U.T.
RT
RL
CL
Test Circuit for switching times
3
2.5
VCC = 3.3 V
2
1.5
VCC = 2.5 V
1
VCC = 1.8 V
0.5
0
0
DEFINITIONS
50
100
150
200
250
I OL OUTPUT CURRENT (mA)
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of pulse generators.
SH00204
SWITCH POSITION
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
VCC
GND
VCC
VI
RL
< 2.3 V
VCC
1000 Ω
2.3–2.7 V
VCC
500 Ω
3.0 V
VCC
500 Ω
Figure 1. Output voltage (VOL) vs. output current (IOL)
3.5
VOH OUTPUT VOLTAGE (V)
SV01018
Waveform 7. Load circuitry for switching times
3.0
2.5
2.0
1.5
1.0
V
= 3.3 V
0.5 CC
0.0
–250
VCC = 2.5 V
–200
–150
VCC = 1.8 V
–100
–50
0
I OH OUTPUT CURRENT (mA)
SH00205
Figure 2. Output voltage (VOH) vs. output current (IOH)
A Dynamic Controlled Output (DCO) circuit is designed in. During
the transition, it initially lowers the output impedance to effectively
drive the load and, subsequently, raises the impedance to reduce
noise. Figures 1 and 2 show VOL vs. IOL and VOH vs. IOH curves to
illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DCO circuit provides a
maximum dynamic drive that is equivalent to a high drive standard
output device.
2000 Aug 03
8
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
2000 Aug 03
9
74AVC16334A
SOT362-1
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
74AVC16334A
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 08-00
Document order number:
2000 Aug 03
10
9397-750 07394
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湘ICP备2023018690号
