AT25SF321
32-Mbit, 2.5V Minimum
SPI Serial Flash Memory with Dual-I/O and Quad-IO Support
Features
Single 2.5V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual and Quad Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Blocks via WP Pin
3 Protected Programmable Security Register Pages
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
0.7ms Typical Page Program (256 Bytes) Time
70ms Typical 4-Kbyte Block Erase Time
300ms Typical 32-Kbyte Block Erase Time
600ms Typical 64-Kbyte Block Erase Time
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
2µA Deep Power-Down Current (Typical)
10µA Standby current (Typical)
4mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil and 208-mil)
8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
Die in Wafer Form
DS-25SF321–047F–8/2017
Description
The Adesto® AT25SF321 is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM
for execution. The flexible erase architecture of the AT25SF321 is ideal for data storage as well, eliminating the need for
additional data storage devices.
The erase block sizes of the AT25SF321 have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because
certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and
unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased
memory space efficiency allows additional code routines and data storage segments to be added while still maintaining
the same overall device density.
The device also contains three pages of Security Register that can be used for purposes such as unique device
serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register
pages can be individually locked.
1.
Pin Descriptions and Pinouts
Table 1-1.
Symbol
CS
SCK
Pin Descriptions
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down
mode), and the SO pin will be in a high-impedance state. When the device is deselected,
data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI pin
is always latched in on the rising edge of SCK, while output data on the SO pin is always
clocked out on the falling edge of SCK.
Asserted
State
Type
Low
Input
-
Input
-
Input/Output
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data
input including command and address sequences. Data on the SI pin is always latched in on
the rising edge of SCK.
SI (I/O0)
With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin
(I/O0) in conjunction with other pins to allow two or four bits of data on (I/O3-0) to be clocked
in on every falling edge of SCK
To maintain consistency with the SPI nomenclature, the SI (I/O0) pin will be referenced as
the SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it
will be referenced as I/O0
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
AT25SF321
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2
Table 1-1.
Symbol
Pin Descriptions (Continued)
Name and Function
Asserted
State
Type
-
Input/Output
-
Input/Output
-
Input/Output
-
Power
-
Power
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
SO (I/O1)
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in
conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked in on every
falling edge of SCK
To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as
the SO pin unless specifically addressing the Dual-I/O modes in which case it will be
referenced as I/O1
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
WRITE PROTECT: The WP pin controls the hardware locking feature of the device.
WP
(I/O2)
With the Quad-Input Byte/Page Program command, the WP pin becomes an input pin (I/O2)
and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every rising
edge of SCK. With the Quad-Output Read commands, the WP Pin becomes an output pin
(I/O2) in conjunction with other pins to allow four bits of data on (I/O33-0) to be clocked in on
every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the WP (I/O2) pin will be referenced as
the WP pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O2
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to VCC whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold Function” on page 34 for additional details on the Hold operation.
HOLD
(I/O3)
With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin
(I/O3) and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every
rising edge of SCK. With the Quad-Output Read commands, the HOLD Pin becomes an
output pin (I/O3) in conjunction with other pins to allow four bits of data on (I/O33-0) to be
clocked in on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the HOLD (I/O3) pin will be referenced
as the HOLD pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O3
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to VCC
whenever possible.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
VCC
GND
Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
GROUND: The ground reference for the power supply. GND should be connected to the
system ground.
AT25SF321
DS-25SF321–047F–8/2017
3
Figure 1-1. 8-SOIC (Top View)
CS
SO
WP
GND
2.
1
2
3
4
Figure 1-2. 8-UDFN (Top View)
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
1
8
2
7
3
6
4
5
VCC
HOLD
SCK
SI
Block Diagram
Figure 2-1. Block Diagram
Control and
Protection Logic
CS
I/O Buffers
and Latches
SRAM
Data Buffer
SI (I/O0)
SO (I/O1)
Interface
Control
And
Logic
WP (I/O2)
Address Latch
SCK
Y-Decoder
Y-Gating
X-Decoder
Flash
Memory
Array
HOLD (I/O3)
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
3.
Memory Array
To provide the greatest flexibility, the memory array of the AT25SF321 can be erased in four levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
AT25SF321
DS-25SF321–047F–8/2017
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Figure 3-1. Memory Architecture Diagram
Block Erase Detail
64KB
32KB
Page Program Detail
4KB
1-256 Byte
Block Address
Range
32KB
64KB
Sector 62
•••
•••
32KB
32KB
64KB
Sector 0
32KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
00FFFFh–00F000h
00EFFFh–00E000h
00DFFFh–00D000h
00CFFFh–00C000h
00BFFFh–00B000h
00AFFFh–00A000h
009FFFh–009000h
008FFFh–008000h
007FFFh–007000h
006FFFh–006000h
005FFFh–005000h
004FFFh–004000h
003FFFh–003000h
002FFFh–002000h
001FFFh–001000h
000FFFh–000000h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
3FFFFFh – 3FFF00h
3FFEFFh – 3FFE00h
3FFDFFh – 3FFD00h
3FFCFFh – 3FFC00h
3FFBFFh – 3FFB00h
3FFAFFh – 3FFA00h
3FF9FFh – 3FF900h
3FF8FFh – 3FF800h
3FF7FFh – 3FF700h
3FF6FFh – 3FF600h
3FF5FFh – 3FF500h
3FF4FFh – 3FF400h
3FF3FFh – 3FF300h
3FF2FFh – 3FF200h
3FF1FFh – 3FF100h
3FF0FFh – 3FF000h
3FEFFFh – 3FEF00h
3FEEFFh – 3FEE00h
3FEDFFh – 3FED00h
3FECFFh – 3FEC00h
3FEBFFh – 3FEB00h
3FEAFFh – 3FEA00h
3FE9FFh – 3FE900h
3FE8FFh – 3FE800h
•••
32KB
– 3FF000h
– 3FE000h
– 3FD000h
– 3FC000h
– 3FB000h
– 3FA000h
– 3F9000h
– 3F8000h
– 3F7000h
– 3F6000h
– 3F5000h
– 3F4000h
– 3F3000h
– 3F2000h
– 3F1000h
– 3F0000h
– 3EF000h
– 3EE000h
– 3ED000h
– 3EC000h
– 3EB000h
– 3EA000h
– 3E9000h
– 3E8000h
– 3E7000h
– 3E6000h
– 3E5000h
– 3E4000h
– 3E3000h
– 3E2000h
– 3E1000h
– 3E0000h
•••
64KB
Sector 63
3FFFFFh
3FEFFFh
3FDFFFh
3FCFFFh
3FBFFFh
3FAFFFh
3F9FFFh
3F8FFFh
3F7FFFh
3F6FFFh
3F5FFFh
3F4FFFh
3F3FFFh
3F2FFFh
3F1FFFh
3F0FFFh
3EFFFFh
3EEFFFh
3EDFFFh
3ECFFFh
3EBFFFh
3EAFFFh
3E9FFFh
3E8FFFh
3E7FFFh
3E6FFFh
3E5FFFh
3E4FFFh
3E3FFFh
3E2FFFh
3E1FFFh
3E0FFFh
•••
32KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
Page Address
Range
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
0017FFh – 001700h
0016FFh – 001600h
0015FFh – 001500h
0014FFh – 001400h
0013FFh – 001300h
0013FFh – 001300h
0013FFh – 001300h
0012FFh – 001200h
0011FFh – 001100h
0010FFh – 001000h
000FFFh – 000F00h
000CFFh – 000C00h
000BFFh – 000B00h
000AFFh – 000A00h
0009FFh – 000900h
0008FFh – 000800h
0007FFh – 000700h
0006FFh – 000600h
0005FFh – 000500h
0004FFh – 000400h
0003FFh – 000300h
0002FFh – 000200h
0001FFh – 000100h
0000FFh – 000000h
AT25SF321
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4.
Device Operation
The AT25SF321 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI
Master. The SPI Master communicates with the AT25SF321 via the SPI bus which is comprised of four signal lines: Chip
Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25SF321
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
Figure 4-1. SPI Mode 0 and 3
CS
SCK
SI
MSB
SO
4.1
LSB
MSB
LSB
Dual Output Read
The AT25SF321 features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every
clock cycle to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of
data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.
4.2
Quad Output Read
The AT25SF321 features a Quad-Output Read mode that allow four bits of data to be clocked out of the device every
clock cycle to improve throughput. To accomplish this, the SI, SO, WP, HOLD pins are utilized as outputs for the transfer
of data bytes. With the Quad-Output Read Array command, the SI, WP, HOLD pins become outputs along with the SO
pin.
5.
Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent
information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25SF321 will be ignored by the device and no operation will be started. The device will
continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and
then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the
device, then no operation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25SF321 memory array is 3FFFFFh, address bits A23-A22 are always ignored by
the device.
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Table 5-1.
Command Listing
Command
Opcode
Clock
Frequency
Address
Bytes
Dummy
Bytes
Data
Bytes
Section
Link
Read Commands
0Bh
0000 1011
Up to 85 MHz
3
1
1+
03h
0000 0011
Up to 50 MHz
3
0
1+
Dual Output Read
3Bh
0011 1011
Up to 85 MHz
3
1
1+
6.2
Dual I/O Read
BBh
1011 1011
Up to 85 MHz
3
0
1+
6.3
Quad Output Read
6Bh
0110 1011
Up to 85 MHz
3
1
1+
6.4
Quad I/O Read
EBh
1110 1011
Up to 85 MHz
3
1
1+
6.5
Continuous Read Mode Reset - Dual
FFFFh
1111 1111
1111 1111
Up to 104 MHz
0
0
0
6.6
Continuous Read Mode Reset - Quad
FFh
1111 1111
Up to 104 MHz
0
0
0
6.6
Block Erase (4 Kbytes)
20h
0010 0000
Up to 104 MHz
3
0
0
Block Erase (32 Kbytes)
52h
0101 0010
Up to 104 MHz
3
0
0
Block Erase (64 Kbytes)
D8h
1101 1000
Up to 104MHz
3
0
0
60h
0110 0000
Up to 104 MHz
0
0
0
C7h
1100 0111
Up to 104 MHz
0
0
0
Byte/Page Program (1 to 256 Bytes)
02h
0000 0010
Up to 104 MHz
3
0
1+
7.1
Program/Erase Suspend
75h
0111 0101
Up to 104 MHz
0
0
0
7.4
Program/Erase Resume
7Ah
0111 1010
Up to 104 MHz
0
0
0
7.5
Write Enable
06h
0000 0110
Up to 104 MHz
0
0
0
8.1
Write Disable
04h
0000 0100
Up to 104 MHz
0
0
0
8.2
Erase Security Register Page
44h
0100 0100
Up to 104 MHz
3
0
0
9.1
Program Security Register Page
42h
0100 0010
Up to 104 MHz
3
0
1+
9.2
Read Security Register Page
48h
0100 1000
Up to 85MHz
3
1
1+
9.3
Read Status Register Byte 1
05h
0000 0101
Up to 104 MHz
0
0
1
Read Status Register Byte 2
35h
0011 0101
Up to 104 MHz
0
0
1
Write Status Register
01h
0000 0001
Up to 104 MHz
0
0
1 or 2
10.2
Write Enable for Volatile Status
Register
50h
0101 0000
Up to 104MHz
0
0
0
10.3
Read Array
6.1
Program and Erase Commands
Chip Erase
7.2
7.3
Protection Commands
Security Commands
Status Register Commands
AT25SF321
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10.1
7
Table 5-1.
Command Listing
Command
Opcode
Clock
Frequency
Address
Bytes
Dummy
Bytes
Data
Bytes
Section
Link
Miscellaneous Commands
Read Manufacturer and Device ID
9Fh
1001 1111
Up to 104MHz
0
0
3
11.1
Read ID
90h
1001 0000
Up to 104 MHz
0
3
2
11.2
Deep Power-Down
B9h
1011 1001
Up to 104 MHz
0
0
0
11.3
Resume from Deep Power-Down
ABh
1010 1011
Up to 104 MHz
0
0
0
11.4
Resume from Deep Power-Down and
Read ID
ABh
1010 1011
Up to 104 MHz
0
3
1
11.4
6.
Read Commands
6.1
Read Array (0Bh and 03h)
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address is specified. The device incorporates an internal address
counter that automatically increments every clock cycle.
Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each opcode depends on the
maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock
frequency up to the maximum specified by fCLK, and the 03h opcode can be used for lower frequency read operations up
to the maximum specified by fRDLF.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
starting address location of the first byte to read within the memory array. Following the three address bytes, an
additional dummy byte needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.
After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in, additional clock cycles
will result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte
(3FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array
(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into high-impedance state. The CS pin can
be deasserted at any time and does not require a full byte of data be read.
Figure 6-1. Read Array - 03h Opcode
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