NCT3107STR

Nuvoton DDR Termination Regulator NCT3107S DATE: NOVEMBER, 2011 Revision: A2 NCT3107S -Table of Content1.GENERATION DESCRIPTION............................................................................................. 1 2.FEATURES........................................................................................................................... 1 3.BLOCK DIAGRAM ............................................................................................................... 2 4.PIN CONFIGURATION AND TYPICAL APPLICATION CIRCUIT ....................................... 2 5.PIN DESCRIPTION............................................................................................................... 3 6.FUNCTIONAL DESCRIPTION ............................................................................................. 3 7.ELECTRICAL CHARACTERISTIC....................................................................................... 9 8.TYPICAL OPERATING CHARACTERISTICS AND WAFEFORMS .................................. 11 9.PACKAGE DIMENSION ..................................................................................................... 16 10.ORDERING INFORMATION............................................................................................. 17 11.TOP MARKING SPECIFICATION .................................................................................... 17 12.REVISION HISTORY ........................................................................................................ 18 -I- Publication Date: Nov., 2011 Revision A2 NCT3107S 1. GENERATION DESCRIPTION The NCT3107S is a sink/source linear regulator for DDR-SDRAM VTT bus termination. The device contains a high speed operational amplifier to provide excellent response to load transients and only requires a minimum output capacitance of 10uF. The NCT3107S also incorporates a remote sensing function (VSEN pin) to provide superior load regulation and a VREF output as a reference for the chipset and DIMMS. An additional feature found on the NCT3107S is an active low shutdown (SD# pin) that provides Suspend to RAM (STR) functionality. When SD# is pilled low, the VTT output voltage will be discharged to ground but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current. NCT3107S is available in ESOP-8 package. It is specified from -40°C to 85°C. 2. FEATURES General z Sink and Source Current z Thermal Shutdown z Low Output Voltage Offset z Remote Sensing (VSEN) z No External Resistors Required z ±10mA Buffered Reference Output (VREF) z Linear Topology z Meets DDR2 Specifications; Support DDR3 VTT Applications z Suspend to RAM (STR) Functionality z Low External Component Count z ESOP-8 150mil with Exposed Pad Package z Required Minimum Output Capacitance of 10uF for Memory Termination Applications (DDR) z Green Package (Lead Free and Halogen Free) z Built-in Over Current Protection Applications z Memory Termination Regulator for DDR2 and DDR3 z Motherboards z LCD TV/PDP TV, Copier/Printer, Set Top Box -1- Publication Date: Nov., 2011 Revision A2 NCT3107S 3. BLOCK DIAGRAM 2u SD# VDD AVIN 7 PVIN 8 VTT 3 VSEN Anti-shoot through Circuit Current Limit Circuit Thermal Protection Shutdown Logic 2 6 5 50k 50k VREF GN Discharge VTT 4 1 4. PIN CONFIGURATION AND TYPICAL APPLICATION CIRCUIT AVIN GND 1 8 VTT SD# 2 7 PVIN CAIN VDDQ EP VSEN VREF 3 4 6 5 SD# PVIN VSEN VDDQ CPIN AVIN VDDQ AVIN VREF=VDDQ/ CREF VREF SD# VTT GND VTT= VREF COU CAIN=0.1uF, CPIN=10uF, CREF = Reserved COUT=10uF+100uF for worse case test condition -2- Publication Date: Nov., 2011 Revision A2 NCT3107S 5. PIN DESCRIPTION PIN NAME NO PIN TYPE GND 1 Ground SD# 2 I VSEN 3 AI Feedback pin for regulating VTT. VREF 4 AO Buffered internal reference voltage of ½VDDQ. VDDQ 5 AI Input for internal reference equal to ½VDDQ. AVIN 6 Power PVIN 7 AI Analog input pin for internal power MOSFET source. VTT 8 AO Output voltage for connection to termination resistors. EP DESCRIPTION Ground Shutdown VTT output voltage. Analog input pin for power source. Exposed pad thermal connection. Connect to ground. PIN TYPE PIN Attribute AO Output pin (Analog) AI Input pin (Analog) I Input pin (Digital) POWER GROUND Positive power supply input Power supply ground 6. FUNCTIONAL DESCRIPTION General Description The NCT3107S is a sink/source linear regulator for DDR-SDRAM VTT bus termination. The device contains a high speed operational amplifier to provide excellent response to load transients and only requires a minimum output capacitance of 10uF. The NCT3107S also incorporates a remote sensing function (VSEN pin) to provide superior load regulation and a VREF output as a reference for the chipset and DIMMS. An additional feature found on the NCT3107S is an active low shutdown (SD# pin) that provides Suspend to RAM (STR) functionality. When SD# is pilled low, the VTT output voltage will be discharged to ground but, VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The DDR-SDRAM memory termination structure determines the main characteristics of the VT rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance. Fig. 6-1 shows typical characteristics for a single memory cell. When Q1 is on and Q2 is off: z Current flows from VDDQ via the termination resistor to VTT z VTT sinks current -3- Publication Date: Nov., 2011 Revision A2 NCT3107S When Q1 is off and Q2 is on: z Current flows from VTT via the termination resistor to GND z VTT sources current VDDQ Q1 Chipset VTT RS RT Memory Q2 VREF GND Fig. 6-1 DDR Physical Signal System Bi-Directional SSTL Signaling AVIN and PVIN AVIN and PVIN are the input supply voltage pins for NCT3107S. AVIN is used to supply the internal control circuitry and PVIN is used to provide the rail voltage for the output staged used to create VTT. AVIN has to be greater than or equal to PVIN in any applications. This prevents the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown threshold, the part will enter a shutdown state identical to the manual shutdown where VTT is tri-stated and VREF remains active. A lower rail can be used but it will reduce the maximum output current. VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of two internal 50kΩ resistors. This guarantees that VTT will precisely track VREF. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the power rail at the DIMM instead of PVIN. This ensures that the reference voltage precisely tracks the DDR memory rails without a large voltage drop from the power lines. VREF VREF provides the buffered output of the internal reference voltage ½VDDQ. This output should be used to provide the reference voltage for chipset and memory. Typically, there is no necessary to place output capacitor. But for worse condition, an output bypass capacitor could be reserved, close to the pin, to secure a suitable phase margin. Insufficient capacitance may cause an oscillation. A ceramic capacitor in the range 0.01uF to 0.1uF is recommended. The output remains active during the shutdown state and thermal shutdown events for the Suspend to RAM functionality. VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VREF. If a transient is expected to last above the maximum continuous current rating for a significant amount of time, then the bulk output capacitor should be sized large enough to prevent an excessive voltage drop. If the NCT3107S is to operate in elevated temperatures for long durations, care should be taken to ensure the maximum operating junction temperature is not exceeded. Proper thermal de-rating -4- Publication Date: Nov., 2011 Revision A2 NCT3107S should always be used. If the junction temperature exceeds the thermal shutdown threshold, VTT will tri-state until the part returns below the temperature hysteresis trip-point. VSEN The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications, the termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the NCT3107S, then the long trace will cause a significant DC voltage drop resulting in a termination voltage lower at one end of the bus than the other. The VSEN pin can be used to improve this performance by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus. If remote load regulation is not used, then the VSEN pin must be connected to VTT. Care should be taken when a long VSEN trace is implemented in close proximity to the memory. Noise pick up in the VSEN trace can cause problems with precise regulation of VTT. A small 0.1uF ceramic capacitor placed next to the VSEN pin can help filter any high frequency signals and prevent errors. Shutdown The NCT3107S contains an active low shutdown pin that can be used for Suspend to RAM functionality. In the condition, the VTT output voltage will be discharged to ground while the VREF output remains active and provides a constant reference signal for the memory and chipset. During shutdown, VTT should not be exposed to voltages that exceed PVIN. With the shutdown pin asserted low, the quiescent current of the NCT3107S will drop. However, VDDQ always maintain its constant impedance of 100kΩ for generating the internal reference. Therefore, to calculate the total power loss in shutdown, both currents need to be considered. The shutdown pin also has an internal pull up current. Therefore, to turn the part on, the shutdown pin can either be connected to AVIN or left open. Current Limit Protection The NCT3107S provides a current limit circuitry for short circuit protection, which monitors the output current and controls internal power MOSFET gate voltage to limit the output current. This reduction is a non latch protection. Thermal Shutdown The NCT3107S has a thermal shutdown circuitry to limit the junction temperature. When the junction temperature exceeds 150°C, the thermal shutdown circuitry let the output into tri-state, allowing the device to cool down. The output circuitry is enabled again after the junction temperature cools down by 30°C, resulting in a pulsed output during continuous thermal overload conditions. The thermal protection is designed to protect the IC in the event of over temperature conditions. For reliabile operation, the junction temperature cannot exceed 125°C. Input Decoupling To achieve the best results when using the NCT3107S, decouple the power supply for AVIN with a 0.1uF to 4.7uF capacitor. For PVIN pin, use a 10uF (or greater) capacitor to improve performance during large load transients to prevent the input rail from dropping. Provide more input capacitance as more output capacitance is used at VTT. In general, use one-half of the COUT value for input. Use a high quality ceramic surface mount capacitor if possible. Surface mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high frequency response for decoupling applications. -5- Publication Date: Nov., 2011 Revision A2 NCT3107S Output Stability To maintain circuit stability and improve transient response over temperature and current, the NCT3107S needs a suitable output capacitor. In order to insure the circuit stability, the suitable output capacitor should be larger than 10uF. For worse case test condition (from maximum sinking current to maximum sourcing current), the capacitance has to be large than 100uF. The choice for output capacitor will be determined solely on the application and the requirements for load transient response of VTT. The value of ESR should be determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. Thermal Design Because the NCT3107S is a linear regulator, the VTT current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference between PVIN and VTT times IOUT current becomes the power dissipation as shown in below equation. PDISS_SRC = (PVIN - VTT) × IOUTSRC In this case, if PVIN is connected to an alternative power supply lower than the VDDQ voltage, overall power loss can be reduced. For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, PDISS_SNK can be calculated by below equation. PDISS_SNK = VTT × IOUTSNK Since the device does not sink and source at the same time and IOUT varies rapidly with time, actual power dissipation need to be considered for thermal design is an average of above value over thermal relaxation duration of the system. Another source of power consumption is the current used for internal control circuitry from AVIN supply and PVIN supply. This can be estimated as 5mW or less during normal operating conditions. This power must be effectively dissipated from the package. Maximum power dissipation allowed by the package is calculated by below equation. PPKG = [TJ (MAX) – TA (MAX)] / θJA where z TJ (MAX) is +125°C z TA (MAX) Is the maximum ambient temperature in the system z θJA Is the thermal resistance from junction to ambient θJA highly depends on IC package, PCB layout, the aireflow. Thermal resistance θJA can be improved by adding copper under the exposed pad of ESOP-8 while the IC package is fixed. The copper under the exposed pad of ESOP-8 is an effective heatsink and is useful for improving thermal conductivity. Figure show the relationship between thermal resistance θJA vs. copper area on a standard JEDEC 51-7 (4 layers, 2S2P) thermal test board at TA = 25°C, PCB copper thickness = 2oz. The 70mm2 copper plane reduce θJA from 75°C/W to 45°C/W and increases maximum power disspation from 1.33W to 2.22W. -6- Publication Date: Nov., 2011 Revision A2 NCT3107S 70mm2 copper area 30mm2 copper area Minimum copper area Fig. 6-2 Power Dissipation vs. Ambient Temperature Fig. 6-3 Thermal Resistance θJA vs. Copper Area of ESOP Packages Layout Consideration Consider the following points before starting the NCT3107S layout design. z The input bypass capacitors for AVIN, PVIN and VSEN should be placed as close as possible to the pin with short and wide connections. z The output capacitors for VTT and VREF should be placed close to the pin with short and wide connection in order to avoid ESR and/or ESL trace inductance. z VSEN should be connected to the positive node of VTT output capacitor(s) as a separate trace from the high current power line. The configuration is strongly recommended to avoid additional ESR and/or ESL. If sensing the voltage at the point of the load is required, it is recommended to attach the output capacitor(s) at that point. Also, it is recommended to minimized any additional ESR and/or ESL of ground trace between the GND pin and the output capacitor(s). z VDDQ can be connected separately from PVIN. Remember that this sensing potential is the reference voltage of VREF. Avoid any noise generative lines. z The negative nose of the VTT output capacitor(s) and the VREF capacitor should be tied together by avoiding common impedance to the high current path of the VTT source/sink current. Also, place bulk caps close to the DIMM load point, route the VSEN to the DIMM load sense point. z In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly to the package’s thermal pad. The wide traces of component and the side copper connected to the thermal land pad help to dissipate heat. The thermal land connected to the ground plane could also be used to help dissipation. Numerous vias connected from the thermal land to the internal/solder side ground plane(s) should also be used to help dissipation. -7- Publication Date: Nov., 2011 Revision A2 NCT3107S 75 90 219 90 Unit: mil (Not to scale) 50 24 Fig. 6-4 Recommended Land Pattern Ground Layer (Top Layer) for Heat Dissipating COUT Connection to Internal Ground Layer GND VTT SD# PVIN VSEN AVIN VREF CREF CPIN CAIN VDDQ Ground Layer nd (2 Layer) CDDQ Fig. 6-5 PCB Layout Guideline -8- Publication Date: Nov., 2011 Revision A2 NCT3107S 7. ELECTRICAL CHARACTERISTIC Absolute Maximum Ratings PARAMETER RATING UNIT Power Pins AVIN, PVIN, VDDQ -0.3 to 6V V Voltage on Other Pins -0.3 to 6V V Junction Temperature 150 °C Storage Temperature -50 to 150 °C Soldering Temperature Refer to IPC/JEDEC J-STD-020 Specification Human Body Mode 2 kV Machine Mode 200 V Latch-up 100 mA ESD Protection Note1. No pin should exceed AVIN. Note2. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Note3. Devices are ESD sensitive. Handling precaution recommended. Thermal Information ITEM Power Dissipation, PD @ TA=25℃ Package Thermal Resistance, ESOP8, θJA RATING UNIT 1.33 W 75 ℃/W Note1. At elevated temperatures, devices must be de-rated based on thermal resistance. The device in the ESOP-8 package must be de-rated at θJA=75˚C/W junction to ambient with minimum PCB footprint. Recommended Operating Conditions PARAMETER RATING UNIT Operating Temperature -40 to 85 °C Junction Temperature -40 to 125 °C Supply Voltage, AVIN 2.2 to 5.5 V Capacitance of AVIN Decoupling Capacitor 0.1 to 4.7 uF Capacitance of PVIN Decoupling Capacitor 10 to 270 uF Capacitance of VDDQ Decoupling Capacitor 0.1 to 270 uF Capacitance of VREF Regulation Capacitor 0.01 to 0.1 uF Capacitance of VTT Regulation Capacitor 10 to 470 uF -9- Publication Date: Nov., 2011 Revision A2 NCT3107S Electrical Characteristics AVIN=2.5V, PVIN=VDDQ=1.8V, COUT=10uF and all outputs are unload (unless otherwise noted). Typical value are at Ta=25°C and limits apply over the full operating temperature, Ta= -40~85°C. PARAMETER SYM. MIN. TYP. MAX. UNIT 0.49×VDDQ 0.5×VDDQ 0.51×VDDQ V CONDITIONS Reference Voltage VREF Source Current IREF+ Sink Current IREF- VREF Voltage Tolerance 10 mA -15 VDDQ Input Impedance IREF=0mA -10 mA +15 mV ZVDDQ 100 IQ 320 500 IREF=±10mA kΩ Input / Output Current Quiescent Current (1) Shutdown Quiescent Current (1) uA IOUT=0A ISD 115 150 uA SD#=0V Shutdown Leakage Current IQ_SD 2 5 uA SD#=0V VSEN Input Current IVSEN 1 uA VTT Discharge Current in Shutdown -1 IVTT_Dis 20 mA SD#=0V, VTT=0.4V Output Voltage Offset (VREF-VTT) DDR2, PVIN=VDDQ=1.8V -20 20 mV IOUT=0A DDR3, PVIN=VDDQ=1.5V -20 20 mV IOUT=0A -30 30 mV IOUT =±1.5A (2) -30 30 mV IOUT =±1.2A (2) VOS DDR2, PVIN=VDDQ=1.8V DDR3, PVIN=VDDQ=1.5V Logic Input Level Minimum Shutdown High Level VIH Maximum Shutdwon Low Level VIL 1.9 V 0.8 V AVIN=2.2V~5.5V Current Limit Protection Output Current Limit ILIM 2.5 A PVIN=VDDQ=1.8V 1.5 A PVIN=VDDQ=1.5V Over Temperature Protection (3) Thermal Shutdown Temperature 145 150 160 °C Thermal Shutdown Hysteresis 20 30 40 °C Note1. Quiescent is defined as the current flow into AVIN. Note2. VTT load regulation is tested by using a 10ms current pulse and measuring VTT. Note3. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ (MAX), the junction to ambient thermal resistance, θJA, and the ambient temperature, TA exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal shutdown. Ensured by design, no production tested. Note4. Limits are 100% production tested at 25˚C. Limits over operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate average outgoing quality level. -10- Publication Date: Nov., 2011 Revision A2 NCT3107S 8. TYPICAL OPERATING CHARACTERISTICS AND WAFEFORMS AVIN Operating Current vs AVIN AIVIN Shutdown Current vs AVIN 400 180 390 170 160 370 Current (uA) 360 350 340 150 140 130 120 330 110 320 100 310 2.5 3.0 3.5 4.0 4.5 5.0 2.5 5.5 3.0 3.5 4.0 5.0 5.5 4.0 5.0 6.0 VTT vs VDDQ 3000 3000 2500 2500 2000 2000 VTT (mV) VTT (mV) VREF vs VDDQ 1500 1500 1000 1000 500 500 0 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.0 1.0 2.0 VDDQ (V) VTT_VREF_VOS vs AVIN VTT_VREF_VOS vs AVIN 8.9 8.4 758 8.8 8.3 VOS 904 760 8.2 902 8.1 900 8.0 VTT 898 7.9 756 7.7 742 4.5 5.0 8.3 VTT 746 894 4.0 8.4 748 744 3.5 8.5 750 7.8 3.0 8.6 VOS 752 896 2.5 8.7 VREF 754 VTT (mV) VREF 8.5 Offset Voltage (mV) 908 906 3.0 VDDQ (V) 910 VTT (mV) 4.5 Voltage (V) Voltage (V) 5.5 8.1 8.0 2.5 AVIN (V) 8.2 Offset Voltage (mV) Current (uA) 380 3.0 3.5 4.0 4.5 5.0 5.5 AVIN (V) -11- Publication Date: Nov., 2011 Revision A2 NCT3107S VREF vs IREF 0.918 0.770 0.916 0.914 0.768 0.765 0.912 VREF (V) VREF (V) VREF vs IREF 0.910 0.908 0.906 Continuous Load 0.904 0.902 0.763 0.760 0.758 Continuous Load 0.755 0.753 0.900 0.750 -20 -16 -12 -8 -4 0 4 8 12 16 20 -20 -16 -12 -8 IREF (mA) 4 8 12 16 20 VREF Sinking Current Limit vs AVIN 140 120 120 100 Curent (mA) 100 Curent (mA) 0 IREF (mA) VREF Sourcing Current Limit vs AVIN 80 60 40 80 60 40 20 20 0 2.5 3.0 3.5 4.0 4.5 5.0 0 2.5 5.5 3.0 3.5 4.0 4.5 5.0 5.5 AVIN (V) AVIN (V) VTT vs IVTT VTT vs IVTT 0.950 0.790 0.940 0.780 0.930 0.770 0.920 VTT (V) VTT (V) -4 0.910 0.900 0.760 0.750 0.740 0.890 0.880 Continuous Load -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 Continuous Load 0.730 0.870 2.0 IVTT (A) -12- 0.720 -2.0 -1.5 -1.0 -0.5 0.0 0.5 IVTT (A) 1.0 1.5 2.0 Publication Date: Nov., 2011 Revision A2 NCT3107S AVIN Shutdown Current vs AVIN AVIN Operating Current vs AVIN 430 190 410 -40°C 0°C 180 -40°C 170 370 Current (uA) Current (uA) 390 25°C 350 330 85°C 310 160 150 140 120 270 110 3.0 3.5 4.0 4.5 5.0 5.5 25°C 130 290 250 2.5 0°C 85°C 100 2.5 3.0 3.5 4.0 Voltage (V) VTT vs IVTT 5.0 5.5 VTT vs IVTT 0.775 0.930 85°C 0.925 0.765 0°C VTT (V) 0.915 25°C 0.910 85°C 0.770 0.920 VTT (V) 4.5 Voltage (V) 0.905 0°C 0.760 25°C 0.755 0.750 0.900 -40°C 0.745 0.895 -40°C 0.740 0.890 -100 -75 -50 -25 0 25 50 75 -100 -75 100 -50 -25 0 25 50 75 100 IVTT (mA) IVTT (mA) SD# Threshold vs AVIN 1.8 1.6 1.4 VIH SD# (V) 1.2 1.0 0.8 VIL 0.6 0.4 0.2 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVIN (V) -13- Publication Date: Nov., 2011 Revision A2 NCT3107S Operating Waveforms AVIN=2.5V, PVIN=VDDQ=1.8V, COUT=10uF MLCC Sourcing DDR2 Sinking IOUT=10mA -> 1.5A DDR2 Sourcing DDR3 IOUT=-10mA -> -1.5A Sinking IOUT=10mA -> 1.2A DDR3 Sourcing IOUT=-10mA -> -1.2A Sinking -14- Publication Date: Nov., 2011 Revision A2 NCT3107S DDR2 DDR3 COUT=10uF, MLCC COUT=10uF, MLCC IOUT=-1.5A -> 1.5A IOUT=-1.2A -> 1.2A Sourcing Sourcing Sinking Sinking DDR2 DDR3 COUT=220uF, electrolytic cap. COUT=220uF, electrolytic cap. IOUT=-1.5A -> 1.5A IOUT=-1.2A -> 1.2A Sourcing Sinking Sourcing Sinking -15- Publication Date: Nov., 2011 Revision A2 NCT3107S 9. PACKAGE DIMENSION Taping Specification -16- Publication Date: Nov., 2011 Revision A2 NCT3107S 8 Pin ESOP Package 10. ORDERING INFORMATION Part Number Supplied as Production Flow T Shape: 2,500 units/T&R Commercial, -40°C to + 85°C Package Type 8PIN ESOP (Green Package) NCT3107S 11. TOP MARKING SPECIFICATION 3 1 0 7 S 046AX Pin 1 index 1st Line: Nuvoton logo 2nd Line: 3107S (NCT3107S) 3rd line: Tracking code z 046: packages assembled in Year 2010, week 46 z A: assembly house ID. z X: IC version. (A means A; B means B and C means C…etc. -17- Publication Date: Nov., 2011 Revision A2 NCT3107S 12. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A0 2010/12/17 All First Published A1 2011/1/17 8 Add PCB Layout Guideline 1. Modified Recommended Land Pattern A2 2011/11/10 8, 16, 17 & 19 2. Modified Thermal Pad Dimension 3. Modified Ordering Information 4. Modified Importance Notice -18- Publication Date: Nov., 2011 Revision A2 NCT3107S Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. -19- Publication Date: Nov., 2011 Revision A2