SG3525M/TR

SG3525 Pulse Width Modulator Control Circuit The SG3525 pulse width modulator control circuit offers improved performance and lower external parts count when implemented for controlling all types of switching power supplies. The on−chip +5.1 V reference is trimmed to
1% and the error amplifier has an input common−mode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors. A sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. A wide range of deadtime can be programmed by a single resistor connected between the CT and Discharge pins. This device also features built−in soft−start circuitry, requiring only an external timing capacitor. A shutdown pin controls both the soft−start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft−start recycle with longer shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft−start capacitor when VCC is below nominal. The output stages are totem−pole design capable of sinking and sourcing in excess of 200 mA. The output stage of the SG3525 features NOR logic resulting in a low output for an off−state. 16 1 DIP−16 16 1 SOP−16L Features • • • • • • • • • 8.0 V to 35 V Operation 5.1 V
1.0% Trimmed Reference 100 Hz to 400 kHz Oscillator Range Separate Oscillator Sync Pin Adjustable Deadtime Control Input Undervoltage Lockout Latching PWM to Prevent Multiple Pulses Pulse−by−Pulse Shutdown Dual Source/Sink Outputs:
400 mA Peak ORDERING INFORMATION DEVICE Package Type MARKING Packing Packing Qty SG3525N DIP16 SG3525 TUBE 1000/box SG3525M/TR SOP16 SG3525 REEL 2500/reel http://www.hgsemi.com.cn 1 2018 JUN SG3525 PIN CONNECTIONS Inv. Input 1 16 Vref Noninv. Input 2 15 VCC Sync 3 14 Output B OSC. Output 4 13 VC CT 5 12 Ground RT 6 11 Output A Discharge 7 10 Shutdown Soft−Start 8 9 Compensation (Top View) SOP-16/DIP-16 16 Vref 15 Reference Regulator VCC 12 VC 13 To Internal Circuitry Under− Voltage Lockout Ground OSC Output NOR 4 3 Sync RT Output A Q 6 F/F Oscillator Q NOR 5 CT Discharge 14 Output B 7 R 9 Compensation 11 1 INV. Input 2 Noninv. Input − Error Amp + + − PWM − S Latch SG3525 Output Stage S 50A VREF 8 CSoft−Start 10 Shutdown 5.0k 5.0k Figure 1. Representative Block Diagram http://www.hgsemi.com.cn 2 2018 JUN SG3525 MAXIMUM RATINGS Symbol Value Unit Supply Voltage Rating VCC +40 Vdc Collector Supply Voltage VC +40 Vdc Logic Inputs −0.3 to +5.5 V Analog Inputs −0.3 to VCC V ±500 mA 50 mA 5.0 mA Output Current, Source or Sink IO Reference Output Current Iref Oscillator Charging Current Power Dissipation TA = +25°C (Note 1) TC = +25°C (Note 2) PD mW 1000 2000 Thermal Resistance, Junction−to−Air RJA 100 °C/W Thermal Resistance, Junction−to−Case RJC 60 °C/W TJ +150 °C Tstg −55 to +125 °C TSolder +300 °C Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 seconds) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Derate at 10 mW/°C for ambient temperatures above +50°C. 2. Derate at 16 mW/°C for case temperatures above +25°C. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit Supply Voltage Characteristics VCC 8.0 35 Vdc Collector Supply Voltage VC 4.5 35 Vdc Output Sink/Source Current (Steady State) (Peak) IO 0 0 ±100 ±400 Reference Load Current Iref 0 20 mA Oscillator Frequency Range fosc 0.1 400 kHz Oscillator Timing Resistor RT 2.0 150 k Oscillator Timing Capacitor CT 0.001 0.2 F Deadtime Resistor Range RD 0 500  Operating Ambient Temperature Range TA 0 +70 °C mA APPLICATION INFORMATION Shutdown Options Since both the compensation and soft−start terminals (Pins 9 and 8) have current source pull−ups, either can readily accept a pull−down signal which only has to sink a maximum of 100 A to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions: the PWM http://www.hgsemi.com.cn 3 latch is immediately set providing the fastest turn−off signal to the outputs; and a 150 A current sink begins to discharge the external soft−start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft−start capacitor, thus, allowing, for example, a convenient implementation of pulse−by−pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn−on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. 2018 JUN SG3525 ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 3], unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Reference Output Voltage (TJ = +25°C) Vref 5.00 5.10 5.20 Vdc Line Regulation (+8.0 V ≤ VCC ≤ +35 V) Regline − 10 20 mV Load Regulation (0 mA ≤ IL ≤ 20 mA) Regload − 20 50 mV Temperature Stability
Vref/
T − 20 − mV
Vref 4.95 − 5.25 Vdc Short Circuit Current (Vref = 0 V, TJ = +25°C) ISC − 80 100 mA Output Noise Voltage (10 Hz ≤ f ≤ 10 kHz, TJ = +25°C) Vn − 40 200 Vrms Long Term Stability (TJ = +125°C) (Note 4) S − 20 50 mV/khr − ±2.0 ±6.0 % REFERENCE SECTION Total Output Variation Includes Line and Load Regulation over Temperature OSCILLATOR SECTION (Note 5, unless otherwise noted.) Initial Accuracy (TJ = +25°C) Frequency Stability with Voltage (+8.0 V ≤ VCC ≤ +35 V)
fosc DVCC − ±1.0 ±2.0 % Frequency Stability with Temperature
fosc DT − ±0.3 − % Minimum Frequency (RT = 150 k, CT = 0.2 F) fmin − 50 − Hz Maximum Frequency (RT = 2.0 k, CT = 1.0 nF) fmax 400 − − kHz Current Mirror (IRT = 2.0 mA) 1.7 2.0 2.2 mA Clock Amplitude 3.0 3.5 − V Clock Width (TJ = +25°C) 0.3 0.5 1.0 s Sync Threshold 1.2 2.0 2.8 V − 1.0 2.5 mA Sync Input Current (Sync Voltage = +3.5 V) ERROR AMPLIFIER SECTION (VCM = +5.1 V) Input Offset Voltage VIO − 2.0 10 mV Input Bias Current IIB − 1.0 10 A Input Offset Current IIO − − 1.0 A DC Open Loop Gain (RL ≥ 10 M) AVOL 60 75 − dB Low Level Output Voltage VOL − 0.2 0.5 V High Level Output Voltage VOH 3.8 5.6 − V Common Mode Rejection Ratio (+1.5 V ≤ VCM ≤ +5.2 V) CMRR 60 75 − dB Power Supply Rejection Ratio (+8.0 V ≤ VCC ≤ +35 V) PSRR 50 60 − dB Minimum Duty Cycle DCmin − − 0 % Maximum Duty Cycle DCmax 45 49 − % Input Threshold, Zero Duty Cycle (Note 5) Vth 0.6 0.9 − V Input Threshold, Maximum Duty Cycle (Note 5) Vth − 3.3 3.6 V Input Bias Current IIB − 0.05 1.0 A PWM COMPARATOR SECTION 3. Tlow = 0° Thigh = +70°C 4. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 5. Tested at fosc = 40 kHz (RT = 3.6 k, CT = 0.01 F, RD = 0 ). http://www.hgsemi.com.cn 4 2018 JUN SG3525 ELECTRICAL CHARACTERISTICS (continued) Characteristics Symbol Min Typ Max Unit Soft−Start Current (Vshutdown = 0 V) 25 50 80 A Soft−Start Voltage (Vshutdown = 2.0 V) − 0.4 0.6 V Shutdown Input Current (Vshutdown = 2.5 V) − 0.4 1.0 mA − − 0.2 1.0 0.4 2.0 18 17 19 18 − − 7.0 8.0 V SOFT−START SECTION OUTPUT DRIVERS (Each Output, VCC = +20 V) Output Low Level (Isink = 20 mA) (Isink = 100 mA) VOL V Output High Level (Isource = 20 mA) (Isource = 100 mA) VOH Under Voltage Lockout (V8 and V9 = High) VUL 6.0 V IC(leak) − − 200 A Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 100 600 ns Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 300 ns Shutdown Delay (VDS = +3.0 V, CS = 0, TJ = +25°C) tds − 0.2 0.5 s Supply Current (VCC = +35 V) ICC − 14 20 mA Collector Leakage, VC = +35 V (Note 6) 6. Applies to SG3525 only, due to polarity of output pulses. Vref 16 0.1 Clock PWM ADJ. 13 Flip/ Flop 3 O s c i l l a t o r RT 6 Deadtime 1.5k 7 Ramp 0.009 100 5 Out A 11 A 1.0k, 1.0W (2) 14 B 0.001 0.1 VC 0.1 Sync 1.0k VCC 0.1 4 3.0k 15 Reference Regulator Out B Comp 10k 1 = VIO 2 = 1(+) 3 = 1(−) 1 2 − V/I Meter + 12 PWM GND 0.01 50A + 2 1 3 2 5.0F − 5.0k E/A 5.0k + 1 2 3 Softstart 8 1 3 1 2 3 9 10 Vref 2.0k DUT Shutdown Figure 2. Lab Test Fixture http://www.hgsemi.com.cn 5 2018 JUN SG3525 200 R D , DEAD TIME RESISTOR (
) Ω 500 RT, TIMING RESISTOR (k Ω ) 100 50 * RD = 0  20 10 5 6 5.0 RD * RT 7 300 200 100 CT 2.0 0 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000 0.2 0.5 1.0 1 − 2 + 50 100 200 9 CP RZ RZ = 20 k 40 20 0 −20 1.0 10 100 1.0 k 10 k 100 k 1.0 M 4.0 3.5 VCC = +20 V TJ = +25°C 3.0 2.5 2.0 1.5 Source Sat, (VC−VOH) 1.0 Sink Sat, (VOL) 0.5 0 0.01 10 M f, FREQUENCY (Hz) 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 IO, OUTPUT SOURCE OR SINK CURRENT (A) Figure 5. Error Amplifier Open Loop Frequency Response Figure 6. Output Saturation Characteristics 15 16 VCC Q5 Q1 Q8 7.4k Q6 5 3 Sync 7 Discharge Q2 Q3 Q3 6 12 GND 20 Figure 4. Oscillator Discharge Time versus RD 60 CT 10 Figure 3. Oscillator Charge Time versus RT 80 RT 5.0 DISCHARGE TIME (s) 100 Vref 2.0 CHARGE TIME (s) V sat , SATURATION VOLTAGE (V) A VOL, VOLTAGE GAIN (dB) 400 2.0k Q9 2.0k Ramp To PWM 14k Q11 Q10 25k 5.0pF Blanking Q14 To Output 400A Q4 23k Q7 1.0k 1.0k Q12 Q13 3.0k 250 Inverting Q1 Input 1 Noninverting Input 2 200A Q4 Q2 To PWM Comparator 100A 5.8V 30 9 Compensation 4 OSC Output Figure 7. Oscillator Schematic http://www.hgsemi.com.cn Figure 8. Error Amplifier Schematic 6 2018 JUN SG3525 13 VCC VC Q7 Q5 Q9 Q10 Q4 5.0k Vref 11, 14 Q11 Output Q8 Q6 2.0k Q1 Q2 5.0k Clock 10k Q3 Q6 Omitted in SG3527 10k F/F PWM Figure 9. Output Circuit (1/2 Circuit Shown) Q1 +Vsupply To Output Filter +Vsupply R1 R1 R2 VC A 13 VC A SG3525 11 GND For single−ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem−pole source transistors on alternate oscillator cycles. Q2 R3 In conventional push−pull bipolar designs, forward base drive is controlled by R1−R3. Rapid turn−off times for the power devices are achieved with speed−up capacitors C1 and C2. Figure 10. Single−Ended Supply Figure 11. Push−Pull Configuration +Vsupply R1 Q1 11 Q1 T1 13 11 SG3525 14 C1 T1 VC A SG3525 GND B B 12 12 VC A T1 Q1 R2 C2 14 14 GND 13 11 SG3525 B +Vsupply C1 13 Q2 GND B 12 12 R1 T2 Q2 14 C2 R2 The low source impedance of the output drivers provides rapid charging of power FET input capacitance while minimizing external components. Low power transformers can be driven directly by the SG3525. Automatic reset occurs during deadtime, when both ends of the primary winding are switched to ground. Figure 12. Driving Power FETS Figure 13. Driving Transformers in a Half−Bridge Configuration http://www.hgsemi.com.cn 7 2018 JUN SG3525 Important statement: Huaguan Semiconductor Co,Ltd. reserves the right to change the products and services provided without notice. Customers should obtain the latest relevant information before ordering, and verify the timeliness and accuracy of this information. Customers are responsible for complying with safety standards and taking safety measures when using our products for system design and machine manufacturing to avoid potential risks that may result in personal injury or property damage. Our products are not licensed for applications in life support, military, aerospace, etc., so we do not bear the consequences of the application of these products in these fields. Our documentation is only permitted to be copied without any tampering with the content, so we do not accept any responsibility or liability for the altered documents. http://www.hgsemi.com.cn 8 2018 JUN