ETA3560

ETA3560 1A, 1.5MHz Step-Down Converter in DFN2X2-6 Package DESCRIPTION FEATURES The ETA3560 is a high-efficiency, DC-to-DC step-down switching regulator, capable of delivering up to 1A of output current. The devices operate from an input voltage range of 2.6V to 5.5V and provide output voltages from 0.6V to VIN, making the ETA3560 ideal for low voltage power conversions. Running at a fixed frequency of 1.5MHz allows the use of small inductance value and low DCR inductors, thereby achieving higher efficiencies. Other external components, such as ceramic input and output caps, can also be small due to higher switching frequency, while maintaining exceptional low noise output voltages. Built-in EMI reduction circuitry makes this converter ideal power supply for RF applications. Internal soft-start control circuitry reduces inrush current. Short-circuit and thermal-overload protection improves design reliability. ETA3560 is housed in a tiny DFN2X2-6L package       Up to 96% Efficiency Up to 1A Max Output Current 1.5MHz Frequency Light Load operation Internal Compensation Tiny DFN2X2-6L Package APPLICATIONS      MIDs, Tablet PC Set Top Boxes USB ports/Hubs Hot Swaps Cellphones ORDERING INFORMATION PART # ETA3560D2G PACKAGE PIN DFN2X2-6 TOP MARK DIYW TYPICAL APPLICATION VIN 2.6V to 5.5V 10μF 4 5 SW EN VOUT 1.8V/1A 1 2.2μH 100K FB GND 3 ŋ IN 22pF Optional 10μF 50K 6 100% 95% 90% 85% 80% 75% 70% 65% 60% 55% 50% 45% 40% Efficiency Vs IOUT VIN=2.7V VIN=3.6V VIN=5V VOUT=1.8V 0.001 1.8V/1A 1.5MHz Step-Down Converter 0.01 0.1 1 IOUT (A) Outperform with Efficiency www.ETAsolution.com Proprietary Information DO NOT Distribute 1 ETA3560 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS (Note: Exceeding these limits may damage the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability.) SW 1 NC 2 FB 3 GND 7 6 GND 5 VIN 4 EN IN, SW, FB, EN Voltage ............................................–0.3V to 6.5V SW to ground current …………………….…….…..Internally limited Maximum Power Dissipation…………………..………………….650mW Operating Temperature Range …….................…–40°C to 85°C Storage Temperature Range ……………………….–55°C to 150° Thermal Resistance θJA θJC DFN2X2-6…………………………………………..165…….…45 ........oC/W DFN2x2-6 ELECTRICAL CHACRACTERISTICS (VIN = 3.6V, unless otherwise specified. Typical values are at TA = 25oC.) PARAMETER Input Voltage Range Input UVLO Input Supply Current Input Shutdown Current FB Feedback Voltage FB Input Current Output Voltage Range Load Regulation Line Regulation Switching Frequency NMOS Switch On Resistance PMOS Switch On Resistance PMOS Switch Current Limit SW Leakage Current EN Input Current EN Input Low Voltage EN Input High Voltage CONDITIONS MIN 2.6 Rising, Hysteresis=90mV VFB =0.65V VIN =2.5 to 5V TYP 2.31 40 0.588 0.6 0.01 0.6 VOUT =1.8V, IOUT From 0.2A to 0.4A VIN =2.7 to 5.5V MAX 6 2.45 70 1 0.612 VIN 0.1 0.2 1.5 200 280 ISW =200mA ISW =200mA 1.5 VIN=5.5V,VSW =0 or 5.5V,EN= GND 10 1 0.4 1.5 UNITS V V μA μA V μA V % %/V MHz mΩ mΩ A μA μA V V PIN DESCRIPTION PIN # 1 2 3 NAME SW NC FB 4 5 6, 7 EN IN GND DESCRIPTION Inductor Connection. Connect an inductor Between SW and the regulator output. Not connected, No internal connecting wire to any pad of the chip Feedback Input. Connect an external resistor divider from the output to FB and GND to set the output to a voltage between 0.6V and VIN Enable pin for the IC. Drive this pin high to enable the part, low to disable. Supply Voltage. Bypass with a 10μF ceramic capacitor to GND Ground, The thermal pad (Pin No,7) is Ground too Outperform with Efficiency www.ETAsolution.com Proprietary Information DO NOT Distribute 2 ETA3560 TYPICAL CHARACTERISTICS VIN=3.8V VIN=4V VIN=5V VOUT=3.3V 0.001 0.01 0.1 Efficiency Vs IOUT 100% 95% 90% 85% 80% 75% 70% 65% 60% 55% 50% 45% 40% 1 ŋ Efficiency Vs IOUT 100% 95% 90% 85% 80% 75% 70% 65% 60% 55% 50% 45% 40% ŋ ŋ (Typical values are at TA = 25OC unless otherwise specified.) VIN=2.7V VIN=3.6V 0.001 0.01 IOUT (A) 1.84 1.84 1.83 1.83 1.82 1.82 VOUT (V) VOUT 1 VIN=3.6V 1.81 VIN=5V VOUT=1.2V 0.001 0.01 0.1 1 IOUT (A) Load Transient Response VIN=3.6V, VOUT=1.2V,IOUT= 0.2A to 1A VOUT Vs VIN 1.85 1.8 0.1 VIN=2.7V IOUT (A) VOUT Vs IIOUT 1.85 VIN=5V VOUT=1.8V Efficiency Vs IOUT 100% 95% 90% 85% 80% 75% 70% 65% 60% 55% 50% 45% 40% IOUT=500mA VOUT 1.81 1.8 VOUT=1.8V 1.79 ISW 1.79 1.78 1.78 0 0.2 0.4 0.6 0.8 1 2.5 IOUT(mA) 3 3.5 4.5 5 2ms/div VIN (V) Load Transient Response VIN=5V, VOUT=3.3V,IOUT= 0.5A to 1A Load Transient Response VIN=3.6V, VOUT=1.8V,IOUT= 0.2A to 1A VOUT VOUT 4 Heavy Load Switching Waveform VIN=3.6V, VOUT=1.8V,IOUT= 0.5A VOUT (AC) ISW VSW ISW 1ms/div 2ms/div 500ns/div Outperform with Efficiency www.ETAsolution.com Proprietary Information DO NOT Distribute 3 ETA3560 TYPICAL CHARACTERISTICS (Typical values are at TA = 25OC unless otherwise specified.) Startup Waveform with EN Turn on VIN=5V, VOUT=3.3V Into 1A Resistive Load VIN VIN VEN Shutdown Waveform with EN Tied to IN VIN=5V, VOUT=3.3V, 1A Resistive Load Startup Waveform with EN Tied to IN VIN=5V, VOUT=3.3V Into 1A Resistive Load VOUT VOUT VOUT VSW VSW ISW VSW ISW ISW 50μs/div 2ms/div Startup Waveform with EN Tied to IN VIN=5V, VOUT=1.8V Into NoLoad 200s/div Short Circuit Recovery VIN=5V, VOUT=3.3V Short Circuit Response VIN=5V, VOUT=3.3V VIN VOUT VEN VOUT VOUT ISW ISW ISW 100μs/div 50μs/div 50s/div FUNCTION DESCRIPTION The ETA3560 high efficiency switching regulator is a small, simple, DC-to-DC step-down converter capable of delivering up to 1A of output current. The device operates in pulse-width modulation (PWM) at 1.5MHz from a 2.6V to 5.5V input voltage and provides an output voltage from 0.6V to VIN, making the ETA3560 ideal for on-board post-regulation applications. An internal synchronous rectifier improves efficiency and eliminates the typical Schottky free-wheeling diode. Using the on resistance of the internal highside MOSFET to sense switching currents eliminates current-sense resistors, further improving efficiency and cost. Loop Operation ETA3560 uses a PWM current-mode control scheme. An open-loop comparator compares the integrated voltage-feedback signal against the sum of the amplified current-sense signal and the slope compensation ramp. At each rising edge of the internal clock, the internal high-side MOSFET turns on until the PWM comparator terminates the on cycle. During this on-time, current ramps up through the inductor, sourcing current to the output and storing energy in the inductor. The current mode feedback system regulates the peak inductor current as a function of the output voltage error signal. During the off cycle, the internal high-side Pchannel MOSFET turns off, and the internal low-side N-channel MOSFET turns on. The inductor releases the stored energy as its current ramps down while still providing current to the output. Outperform with Efficiency www.ETAsolution.com Proprietary Information DO NOT Distribute 4 ETA3560 Current Sense An internal current-sense amplifier senses the current through the high-side MOSFET during on time and produces a proportional current signal, which is used to sum with the slope compensation signal. The summed signal then is compared with the error amplifier output by the PWM comparator to terminate the on cycle. Current Limit There is a cycle-by-cycle current limit on the high-side MOSFET. When the current flowing out of SW exceeds this limit, the highside MOSFET turns off and the synchronous rectifier turns on. ETA3560 utilizes a frequency fold-back mode to prevent overheating during short-circuit output conditions. The device enters frequency fold-back mode when the FB voltage drops below 200mV, limiting the current to IPEAK and reducing power dissipation. Normal operation resumes upon removal of the short-circuit condition. Soft-start ETA3560 has an internal soft-start circuitry to reduce supply inrush current during startup conditions. When the device exits under-voltage lockout (UVLO), shutdown mode, or restarts following a thermal-overload event, the l soft-start circuitry slowly ramps up current available at SW. UVLO and Thermal Shutdown If IN drops below 2.4V, the UVLO circuit inhibits switching. Once IN rises above 2.6V, the UVLO clears, and the soft-start sequence activates. Thermal-overload protection limits total power dissipation in the device. When the junction temperature exceeds TJ= +160°C, a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns the device on again after the junction temperature cools by 15°C, resulting in a pulsed output during continuous overload conditions. Following a thermal-shutdown condition, the soft-start sequence begins. DESIGN PROCEDURE Setting Output Voltages Output voltages are set by external resistors. The FB threshold is 0.6V. RTOP = RBOTTOM x [(VOUT / 0.6) - 1] Input Capacitor and Output Capacitor Selection The input capacitor in a DC-to-DC converter reduces current peaks drawn from the battery or other input power source and reduces switching noise in the controller. The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source. Input ripple with a ceramic capacitor is approximately as follows: VRIPPLE = IL(PEAK)[1 / (2π x fOSC x CIN)] If the capacitor has significant ESR, the output ripple component due to capacitor ESR is as follows: VRIPPLE(ESR) = IL(PEAK) x ESR The output capacitor keeps output ripple small and ensures control-loop stability. The output capacitor must also have low impedance at the switching frequency. Ceramic, polymer, and tantalum capacitors are suitable, with ceramic exhibiting the lowest ESR and high-frequency impedance. Inductor Selection A reasonable inductor value (LIDEAL) can be derived from the following: LIDEAL = [2(VIN) x D(1 - D)] / IOUT x fOSC Outperform with Efficiency www.ETAsolution.com Proprietary Information DO NOT Distribute 5 ETA3560 BLOCK DIAGRAM IN EN + UVLO & Thermal shutdown 0.6V Ref ISense - + + Comp Network Σ - EA PWM Logic Anti-ShootThrough Driver SW Slope Comp 1.5MHz OSC + Vcomp - FB GND PCB LAYOUT GUIDE PCB layout is very important to achieve stable operation. It is highly recommended to duplicate EVB layout for optimum performance. If change is necessary, please follow these guidelines and take following DEMO Board for reference. 1) Keep the path of switching current short and minimize the loop area formed by input cap, high-side MOSFET and low-side MOSFET. 2) Input ceramic capacitors are suggested to be put as close to the Vin pin as possible 3) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 4) Rout SW away from sensitive analog areas such as FB. 5) Connect IN, SW, and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. Outperform with Efficiency www.ETAsolution.com Proprietary Information DO NOT Distribute 6 ETA3560 PACKAGE OUTLINE DFN2X2-6 PACKAGE OUTLINE AND DIMENSIONS Outperform with Efficiency www.ETAsolution.com Proprietary Information DO NOT Distribute 7