RTL8370NI-VB-CG
LAYER 2 MANAGED 8-PORT 10/100/1000
SWITCH CONTROLLER
DRAFT DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 0.1
13 August 2019
Track ID: JATR-XXXX-XX
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8370NI-VB
Draft Datasheet
COPYRIGHT
©2019 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
ELECTROSTATIC DISCHARGE (ESD) WARNING
This product can be damaged by Electrostatic Discharge (ESD). When handling, care must be taken.
Damage due to inappropriate handling is not covered by warranty.
Do not open the protective conductive packaging until you have read the following, and are at an
approved anti-static workstation.
Use an approved anti-static mat to cover your work surface
Use a conductive wrist strap attached to a good earth ground
Always discharge yourself by touching a grounded bare metal surface or approved anti-static mat
before picking up an ESD-sensitive electronic component
If working on a prototyping board, use a soldering iron or station that is marked as ESD-safe
Always disconnect the microcontroller from the prototyping board when it is being worked on
REVISION HISTORY
Revision
0.1
Release Date
2019/08/13
Summary
First release.
Layer 2 Managed 8-port 10/100/1000 Switch Controller
i
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
Table of Contents
1.
GENERAL DESCRIPTION .............................................................................................................................................. 1
2.
FEATURES ......................................................................................................................................................................... 3
3.
SYSTEM APPLICATIONS ............................................................................................................................................... 5
3.1.
8-PORT 1000BASE-T SWITCH ...................................................................................................................................... 5
4.
BLOCK DIAGRAM ........................................................................................................................................................... 6
5.
PIN ASSIGNMENTS ......................................................................................................................................................... 7
5.1.
5.2.
5.3.
6.
PIN DESCRIPTIONS ...................................................................................................................................................... 11
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
7.
MEDIA DEPENDENT INTERFACE PINS ......................................................................................................................... 11
PARALLEL LED PINS ................................................................................................................................................. 12
SCAN MODE LED PINS .............................................................................................................................................. 14
SERIAL MODE LED PINS............................................................................................................................................ 15
SPI FLASH PINS ......................................................................................................................................................... 15
CONFIGURATION STRAPPING PINS ............................................................................................................................. 15
CONFIGURATION STRAPPING PINS (STRP_DISAUTOLOAD, STRP_DIS_8051, STRP_EN_FLASH) ................... 17
MISCELLANEOUS PINS ............................................................................................................................................... 17
TEST PINS .................................................................................................................................................................. 18
POWER AND GND PINS .............................................................................................................................................. 18
PHYSICAL LAYER FUNCTIONAL OVERVIEW...................................................................................................... 19
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
8.
PIN ASSIGNMENTS ....................................................................................................................................................... 7
PACKAGE IDENTIFICATION ........................................................................................................................................... 7
PIN ASSIGNMENT TABLE .............................................................................................................................................. 8
MDI INTERFACE ........................................................................................................................................................ 19
1000BASE-T TRANSMIT FUNCTION ........................................................................................................................... 19
1000BASE-T RECEIVE FUNCTION .............................................................................................................................. 19
100BASE-TX TRANSMIT FUNCTION........................................................................................................................... 19
100BASE-TX RECEIVE FUNCTION ............................................................................................................................. 20
10BASE-T TRANSMIT FUNCTION ............................................................................................................................... 20
10BASE-T RECEIVE FUNCTION .................................................................................................................................. 20
AUTO-NEGOTIATION FOR UTP .................................................................................................................................. 20
CROSSOVER DETECTION AND AUTO CORRECTION ..................................................................................................... 21
POLARITY CORRECTION ............................................................................................................................................. 21
GENERAL FUNCTION DESCRIPTION ...................................................................................................................... 22
8.1.
RESET ........................................................................................................................................................................ 22
8.1.1. Hardware Reset .................................................................................................................................................... 22
8.1.2. Software Reset ...................................................................................................................................................... 22
8.2.
IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................ 22
8.3.
HALF DUPLEX FLOW CONTROL ................................................................................................................................. 23
8.3.1. Back-Pressure Mode ............................................................................................................................................ 23
8.4.
SEARCH AND LEARNING ............................................................................................................................................ 23
8.5.
SVL AND IVL/SVL ................................................................................................................................................... 24
8.6.
ILLEGAL FRAME FILTERING ....................................................................................................................................... 24
8.7.
IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL ............................................................................. 24
8.8.
BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL ..................................................................................... 25
8.9.
PORT SECURITY FUNCTION ........................................................................................................................................ 25
8.10.
MIB COUNTERS ......................................................................................................................................................... 25
8.11.
PORT MIRRORING ...................................................................................................................................................... 25
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8.12.
VLAN FUNCTION ...................................................................................................................................................... 26
8.12.1.
Port-Based VLAN ............................................................................................................................................ 26
8.12.2.
IEEE 802.1Q Tag-Based VLAN ....................................................................................................................... 26
8.12.3.
Protocol-Based VLAN ..................................................................................................................................... 27
8.12.4.
Port VID .......................................................................................................................................................... 27
8.13.
QOS FUNCTION .......................................................................................................................................................... 28
8.13.1.
Input Bandwidth Control ................................................................................................................................. 28
8.13.2.
Priority Assignment ......................................................................................................................................... 28
8.13.3.
Priority Queue Scheduling............................................................................................................................... 28
8.13.4.
IEEE 802.1p/Q and DSCP Remarking ............................................................................................................ 29
8.13.5.
ACL-Based Priority ......................................................................................................................................... 29
8.14.
IGMP & MLD SNOOPING FUNCTION......................................................................................................................... 30
8.15.
IEEE 802.1X FUNCTION ............................................................................................................................................. 30
8.15.1.
Port-Based Access Control .............................................................................................................................. 30
8.15.2.
Authorized Port-Based Access Control ........................................................................................................... 30
8.15.3.
Port-Based Access Control Direction .............................................................................................................. 30
8.15.4.
MAC-Based Access Control............................................................................................................................. 30
8.15.5.
MAC-Based Access Control Direction ............................................................................................................ 30
8.15.6.
Optional Unauthorized Behavior..................................................................................................................... 31
8.15.7.
Guest VLAN ..................................................................................................................................................... 31
8.16.
IEEE 802.1D FUNCTION ............................................................................................................................................ 31
8.17.
EMBEDDED 8051 ........................................................................................................................................................ 31
8.18.
REALTEK CABLE TEST (RTCT) ................................................................................................................................. 32
8.19.
LED INDICATOR ........................................................................................................................................................ 32
8.19.1.
Parallel LED Mode.......................................................................................................................................... 33
8.19.2.
Scan LED Mode ............................................................................................................................................... 34
8.19.3.
Serial LED Mode ............................................................................................................................................. 35
8.20.
GREEN ETHERNET ...................................................................................................................................................... 38
8.20.1.
Link-On and Cable Length Power Saving ....................................................................................................... 38
8.20.2.
Link-Down Power Saving ................................................................................................................................ 38
8.21.
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ............................................................................... 38
9.
INTERFACE DESCRIPTIONS ...................................................................................................................................... 40
9.1.
9.2.
9.3.
9.4.
10.
I2C MASTER FOR EEPROM AUTO-LOAD .................................................................................................................. 40
I2C-LIKE SLAVE INTERFACE FOR EXTERNAL CPU TO ACCESS RTL8370NI-VB ...................................................... 41
SLAVE MII MANAGEMENT SMI INTERFACE FOR EXTERNAL CPU TO ACCESS RTL8370NI-VB ............................... 42
SPI FLASH INTERFACE ............................................................................................................................................. 42
ELECTRICAL CHARACTERISTICS...................................................................................................................... 43
10.1.
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 43
10.2.
RECOMMENDED OPERATING RANGE.......................................................................................................................... 43
10.3.
THERMAL CHARACTERISTICS .................................................................................................................................... 44
10.3.1.
LQFP-128-EPAD ............................................................................................................................................ 44
10.4.
DC CHARACTERISTICS ............................................................................................................................................... 45
10.5.
AC CHARACTERISTICS ............................................................................................................................................... 46
10.5.1.
I2C Master for EEPROM Auto-Load Timing Characteristics ......................................................................... 46
10.5.2.
I2C-Like Slave Mode for External CPU Access Interface Timing Characteristics ......................................... 48
10.5.3.
Slave MII Management SMI for External CPU Access Interface Timing Characteristics .............................. 49
10.5.4.
Serial Shift Mode LED Interface Timing Characteristics ................................................................................ 50
10.5.5.
SPI FLASH Interface Timing Characteristics ................................................................................................. 51
10.6.
POWER AND RESET CHARACTERISTICS ...................................................................................................................... 52
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11.
11.1.
12.
MECHANICAL DIMENSIONS ................................................................................................................................. 53
RTL8370NI-VB: LQFP 128-PIN E-PAD PACKAGE .................................................................................................. 53
ORDERING INFORMATION ................................................................................................................................... 54
List of Tables
TABLE 1. PIN ASSIGNMENT TABLE ................................................................................................................................................ 8
TABLE 2. MEDIA DEPENDENT INTERFACE PINS ........................................................................................................................... 11
TABLE 3. PARALLEL LED PINS ................................................................................................................................................... 12
TABLE 4. SCAN MODE LED PINS ................................................................................................................................................ 14
TABLE 5. SERIAL MODE LED PINS .............................................................................................................................................. 15
TABLE 6. SPI FLASH PINS ............................................................................................................................................................ 15
TABLE 7. CONFIGURATION STRAPPING PINS ............................................................................................................................... 15
TABLE 8. CONFIGURATION STRAPPING PINS (STRP_DISAUTOLOAD, STRP_DIS_8051, STRP_EN_FLASH) ..................... 17
TABLE 9. MISCELLANEOUS PINS ................................................................................................................................................. 17
TABLE 10. TEST PINS .................................................................................................................................................................... 18
TABLE 11. POWER AND GND PINS ................................................................................................................................................ 18
TABLE 12. MEDIA DEPENDENT INTERFACE PIN MAPPING............................................................................................................. 21
TABLE 13. IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL ............................................................................... 24
TABLE 14. LED DEFINITIONS........................................................................................................................................................ 32
TABLE 15. RTL8231 SHIFT REGISTER MODE STRAPPING PINS CONFIGURATION ......................................................................... 37
TABLE 16. SLAVE MII MANAGEMENT SMI ACCESS FORMAT....................................................................................................... 42
TABLE 17. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................. 43
TABLE 18. RECOMMENDED OPERATING RANGE ........................................................................................................................... 43
TABLE 19. ASSEMBLY DESCRIPTION ............................................................................................................................................. 44
TABLE 20. MATERIAL PROPERTIES ............................................................................................................................................... 44
TABLE 21. SIMULATION CONDITIONS ........................................................................................................................................... 44
TABLE 22. THERMAL PERFORMANCE OF E-PAD LQFP-128 ON PCB UNDER STILL AIR CONVECTION .......................................... 45
TABLE 23. THERMAL PERFORMANCE OF E-PAD LQFP-128 ON PCB UNDER FORCED CONVECTION ............................................. 45
TABLE 24. DC CHARACTERISTICS................................................................................................................................................. 45
TABLE 25. I2C MASTER FOR EEPROM AUTO-LOAD TIMING CHARACTERISTICS ........................................................................ 47
TABLE 26. I2C-LIKE SLAVE FOR EXTERNAL CPU ACCESS INTERFACE TIMING CHARACTERISTICS.............................................. 48
TABLE 27. SLAVE SMI (MDC/MDIO) TIMING CHARACTERISTICS AND REQUIREMENTS ............................................................. 49
TABLE 28. SERIAL SHIFT MODE LED AC TIMING ........................................................................................................................ 50
TABLE 29. SPI FLASH AC TIMING .............................................................................................................................................. 51
TABLE 30. POWER AND RESET CHARACTERISTICS ........................................................................................................................ 52
TABLE 31. ORDERING INFORMATION ............................................................................................................................................ 54
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List of Figures
FIGURE 1. 8-PORT 1000BASE-T SWITCH ....................................................................................................................................... 5
FIGURE 2. BLOCK DIAGRAM .......................................................................................................................................................... 6
FIGURE 3. RTL8370NI-VB PIN ASSIGNMENTS ............................................................................................................................. 7
FIGURE 4. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION .................................................................................................. 21
FIGURE 5. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART.................................................................................. 27
FIGURE 6. RTL8370NI-VB MAX-MIN SCHEDULING DIAGRAM ................................................................................................ 29
FIGURE 7. PULL-UP AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED........................................................................... 33
FIGURE 8. PULL-UP AND PULL-DOWN OF LED PINS FOR BI-COLOR LED................................................................................... 33
FIGURE 9. SCAN MODE LED CONNECTION DIAGRAM (GROUP A: SINGLE-COLOR LED (LED0))............................................... 34
FIGURE 10. SCAN MODE LED CONNECTION DIAGRAM (GROUP B: BI-COLOR LED (LED1 & LED2)) ........................................ 34
FIGURE 11. RTL8370NI-VB SERIAL LED MODE SHIFT SEQUENCE (PER-PORT THREE SINGLE-COLOR LED) ............................. 35
FIGURE 12. RTL8370NI-VB+74HC164 SERIAL LED CONNECTION DIAGRAM (PER-PORT THREE SINGLE-COLOR LED) ........... 36
FIGURE 13. RTL8231 SERIAL LED OUTPUT DATA SEQUENCE ..................................................................................................... 36
FIGURE 14. RTL8370NI-VB SERIAL LED MODE SHIFT SEQUENCE (PER-PORT TWO SINGLE-COLOR LEDS) ............................... 37
FIGURE 15. RTL8370NI-VB SERIAL LED MODE SHIFT SEQUENCE (PER-PORT ONE SINGLE-COLOR LED) ................................. 38
FIGURE 16. I2C START AND STOP COMMAND ............................................................................................................................... 40
FIGURE 17. I2C MASTER FOR EEPROM AUTO-LOAD INTERFACE CONNECTION EXAMPLE .......................................................... 40
FIGURE 18. 8-BIT EEPROM SEQUENTIAL READ .......................................................................................................................... 40
FIGURE 19. 16-BIT EEPROM SEQUENTIAL READ ........................................................................................................................ 40
FIGURE 20. I2C-LIKE SLAVE FOR EXTERNAL CPU ACCESS INTERFACE CONNECTION EXAMPLE ................................................. 41
FIGURE 21. I2C-LIKE SLAVE INTERFACE WRITE COMMAND ........................................................................................................ 41
FIGURE 22. I2C-LIKE SLAVE INTERFACE READ COMMAND .......................................................................................................... 41
FIGURE 23. SLAVE MII MANAGEMENT SMI INTERFACE CONNECTION EXAMPLE......................................................................... 42
FIGURE 24. SPI FLASH INTERFACE CONNECTION EXAMPLE ....................................................................................................... 42
FIGURE 25. I2C MASTER FOR EEPROM AUTO-LOAD TIMING CHARACTERISTICS ....................................................................... 46
FIGURE 26. I2C MASTER FOR EEPROM AUTO-LOAD POWER ON TIMING .................................................................................... 46
FIGURE 27. I2C MASTER FOR EEPROM AUTO-LOAD TIMING ..................................................................................................... 47
FIGURE 28. I2C-LIKE SLAVE MODE FOR EXTERNAL CPU ACCESS INTERFACE TIMING CHARACTERISTICS ................................. 48
FIGURE 29. MDIO SOURCED BY MASTER (EXTERNAL CPU) ........................................................................................................ 49
FIGURE 30. MDIO SOURCED BY SLAVE (RTL8370NI-VB) .......................................................................................................... 49
FIGURE 31. SERIAL SHIFT MODE LED TIMING CHARACTERISTICS ............................................................................................... 50
FIGURE 32. SPI FLASH TIMING CHARACTERISTICS ..................................................................................................................... 51
FIGURE 33. POWER AND RESET CHARACTERISTICS ....................................................................................................................... 52
Layer 2 Managed 8-port 10/100/1000 Switch Controller
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Draft Datasheet
1.
General Description
The RTL8370NI-VB-CG is an LQFP128 E-PAD, high-performance 8-port Gigabit Ethernet switch. The
RTL8370NI-VB features low-power integrated 8-port Giga-PHYs that support 1000Base-T, 100Base-T,
and 10Base-T.
The embedded packet storage SRAM in the RTL8370NI-VB features superior memory management
technology to efficiently utilize memory space. The RTL8370NI-VB integrates a 4096-entry look-up
table with a 4-way XOR Hashing algorithm for address searching and learning. The table provides
read/write access from the Slave I2C-like interface or Slave MII Management interface, and each of the
entries can be configured as a static entry. The entry aging time is between 200 and 400 seconds. Sixteen
Filtering Databases are used to provide Independent VLAN Learning and Shared VLAN Learning
(IVL/SVL) functions.
The RTL8370NI-VB supports standard 802.3x flow control frames for full duplex, and optional
backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the
availability of system resources, including the packet buffers and transmitting queues. The RTL8370NIVB supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to nonblocked ports only. For IP multicast applications, the RTL8370NI-VB can forward IPv4 IGMPv1/v2/v3
and IPv6 MLDv1/v2 snooping protocol packets.
In order to support flexible traffic classification, the RTL8370NI-VB supports 96-entry ACL rule check
and multiple actions options. Each port can optionally enable or disable the ACL rule check function. The
ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an
ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value
in 802.1q/Q tag, and rate policing. The rate policing mechanism supports from 8Kbps to 1Gbps (in 8Kbps
steps).
In Bridge operation the RTL8370NI-VB supports 16 sets and four statuses: disable, block, learning, and
forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol.
To meet security and management application requirements, the RTL8370NI-VB supports IEEE 802.1x
Port-based/MAC-based Access Control. For those ports that do not pass IEEE 802.1x authentication, the
RTL8370NI-VB provides a Port-based/MAC-based Guest VLAN function for them to access limited
network resources. A 1-set Port Mirroring function is configured to mirror traffic (RX, TX, or both)
appearing on one of the switch’s ports. Support is provided on each port for multiple RFC MIB Counters,
for easy debug and diagnostics.
To improve real-time or multimedia networking applications, the RTL8370NI-VB supports eight priority
assignments for each received packet. These are based on (1) Port-based priority; (2) 802.1p/Q VLAN tag
priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority; (5) CVLAN-based priority;
(6) SVLAN-based priority; and (7) SMAC-based/LUTFWD-based priority. Each output port supports a
weighted ratio of eight priority queues to fit bandwidth requirements in different applications. The input
bandwidth control function helps limit per-port traffic utilization. There is one leaky bucket for average
packet rate control for each queue of all ports. Queue scheduling algorithm can use Strict Priority (SP) or
Weighted Fair Queue (WFQ) or mixed.
The RTL8370NI-VB provides a 4096-entry VLAN table for 802.1Q port-based, tag-based, and protocolbased VLAN operation to separate logical connectivity from physical connectivity. The RTL8370NI-VB
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Draft Datasheet
supports four Protocol-based VLAN configurations that can optionally select EtherType, LLC, and
RFC1042 as the search key. Each port may be set to any topology.
In embedded system applications, CPU may want to know the input port of the incoming packet. The
RTL8370NI-VB supports an option to insert a VLAN tag with VID=Port VID (PVID) on each egress port.
The RTL8370NI-VB also provides an option to admit VLAN tagged packets with a specific PVID only.
If this function is enabled, the RTL8370NI-VB will drop all non-tagged packets and packets with an
incorrect PVID.
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Features
2.
Single-chip 8-port gigabit non-blocking
switch architecture
Embedded 8-port 10/100/1000Base-T PHY
Each port supports full duplex
10/100/1000M connectivity (half duplex
only supported in 10/100M mode)
Full-duplex and half-duplex operation with
IEEE 802.3x flow control and backpressure
Supports 9216-byte jumbo packet length
forwarding at wire speed
Supports Port-based, Tag-based, and
Protocol-based VLAN
Up to 4 Protocol-based VLAN entries
Supports per-port and per-VLAN egress
VLAN tagging and un-tagging
Supports IVL, SVL, and IVL/SVL
Supports 4096-entry MAC address table
with 4-way hash algorithm, and 64-entry
CAM
Up to 4096 L2/L3 Filtering Database
Supports Spanning Tree port behavior
configuration
Supports Realtek Cable Test (RTCT)
function
IEEE 802.1w Rapid Spanning Tree
Supports 96-entry ACL Rules
IEEE 802.1s Multiple Spanning Tree
with up to 16 Spanning Tree instances
Search keys support physical port,
Layer2, Layer3, and Layer4 information
Actions support mirror, redirect,
dropping, priority adjustment, traffic
policing, CVLAN decision, and SVLAN
assignment
Supports IEEE 802.1x Access Control
Protocol
Port-Based Access Control
MAC-Based Access Control
Guest VLAN
Supports 5 types of user defined ACL
rule format for 96 ACL rules
Optional per-port enable/disable of ACL
function
Supports per port Input Bandwidth
Control
Optional setting of per-port action to
take when ACL mismatch
Traffic classification based on IEEE
802.1p/Q priority definition, physical
Port, IP DSCP field, ACL definition,
VLAN based priority, MAC based
priority, and SVLAN based priority
Eight Priority Queues per port
Per queue flow control
Min-Max Scheduling
Strict Priority and Weighted Fair Queue
(WFQ) to provide minimum bandwidth
Supports Quality of Service (QoS)
Supports IEEE 802.1Q VLAN
Supports 4096 VLANs and 32 Extra
Enhanced VLANs
Supports Un-tag definition in each
VLAN
Supports VLAN policing and VLAN
forwarding decision
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One leaky bucket to constrain the
average packet rate of each queue
Supports rate limiting (64 shared meters,
with 8kpbs granulation)
Supports RFC MIB Counter
MIB-II (RFC 1213)
Ethernet-Like MIB (RFC 3635)
Interface Group MIB (RFC 2863)
RMON (RFC 2819)
Bridge MIB (RFC 1493)
Bridge MIB Extension (RFC 2674)
Supports Stacking VLAN and Port Isolation
with 8 Enhanced Filtering Databases
Supports 64 SVLANs
Supports 32 L2/IPv4 Multicast mappings
to SVLAN
Supports 4 IEEE 802.3ad Link aggregation
port groups
Supports OAM and EEE LLDP (Energy
Efficient Ethernet Link Layer Discovery
Protocol
Supports Loop Detection
Security Filtering
Layer 2 Managed 8-port 10/100/1000 Switch Controller
4
Disable learning for each port
Disable learning-table aging for each
port
Drop unknown DA for each port
Broadcast/Multicast/Unknown DA storm
control protects system from attack by
hackers
Supports Realtek Green Ethernet features
Link-On Cable Length Power Saving
Link-Down Power Saving
Each port supports 3 parallel LED or scan
LED or serial shift LED outputs
Supports I2C-like Slave interface or Slave
MII Management interface to access
configuration register
Supports 16K-byte EEPROM space for
configuration
Integrated 8051 microprocessor
Supports SPI Flash Interface
25MHz crystal input
RTL8370NI-VB: LQFP 128-pin E-PAD
package
Supports IEEE 802.1ad Stacking VLAN
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Draft Datasheet
3.
System Applications
8-Port 1000Base-T Switch
3.1. 8-Port 1000Base-T Switch
Address Table
MIB Counter
Packet Buffer
Queue Manager
EEPROM
Host/I2C-like
Slave
ALE
ACL
Giga
MAC 0
Giga
MAC 1
Giga
MAC 2
Giga
MAC 3
Giga
MAC 4
Giga
MAC 5
Giga
MAC 6
Giga
MAC 7
Giga
PHY 0
Giga
PHY 1
Giga
PHY 2
Giga
PHY 3
Giga
PHY 4
Giga
PHY 5
Giga
PHY 6
Giga
PHY 7
RJ-45
Jack
RJ-45
Jack
RJ-45
Jack
RJ-45
Jack
RJ-45
Jack
RJ-45
Jack
RJ-45
Jack
RJ-45
Jack
Figure 1. 8-Port 1000Base-T Switch
Layer 2 Managed 8-port 10/100/1000 Switch Controller
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Block Diagram
4.
RTL8370NI-VB Block Diagram
UTP
UTP
UTP
UTP
UTP
UTP
UTP
UTP
Giga-PHY
PCS
P0
GMAC
Giga-PHY
PCS
P1
GMAC
Giga-PHY
PCS
P2
GMAC
Giga-PHY
PCS
P3
GMAC
Giga-PHY
PCS
P4
GMAC
Giga-PHY
PCS
P5
GMAC
Giga-PHY
PCS
P6
GMAC
Giga-PHY
PCS
P7
GMAC
SRAM
Controller
Queue
Managment
Packet Buffer
SRAM
Linking Lists
4096 MAC
Address Table
Lookup
Engine
4096 VLAN
Table
LED
LED
GNIC
MAC
GNIC
8051
PLL
I2C Host
Flash Interface
SPI
FLASH
25MHz
Crystal
I2C
Slave
Control
Registers
+
MIB Counter
SCK/SDA
Figure 2. Block Diagram
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P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
AVDDH
AGND
MDIREF
AVDDL
AVDDH
DVDDL
DVDDL
DVDDL
DVDDL
AVDDH
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN
AVDDL
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
AVDDH
P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
AVDDH
SDA / MMD_MDIO
SCK / MMD_MDC
nRESET
XTALI
XTALO
AVDDH
DVDDL
LED_CK / P0LED0 / SLED_P4B / STRP_SMI_SEL_0
LED_DA / P0LED1 / SLED_G2A
DVDDL
P0LED2 / SLED_P0_4A / GPIO2 / STRP_EN_PHY
P1LED1 / SLED_P1_5A / STRP_EN_EEE
P1LED0 / SLED_P2_6A / STRP_MID29
P1LED2 / SLED_P3_7A / STRP_SMI_SEL_1
P2LED1 / SLED_G1B / GPIO4
P2LED0 / SLED_P0B / STRP_DISAUTOLOAD
P2LED2 / SLED_P1B / STRP_DIS_8051
P3LED0 / SLED_P2B / STRP_EN_FLASH
P3LED2 / SLED_P3B / STRP_EN_PWRLIGHT
P3LED1 / SLED_G1A / GPIO5
P4LED1 / SLED_P5B / GPIO6
P4LED0 / SLED_P6B / STRP_EEPROM_MOD
P4LED2 / SLED_P7B / GPIO3
DVDDL
DVDDIO
DVDDL
P5LED1
P5LED0
P5LED2 / GPIO0
P6LED1 / GPIO7
P6LED0 / GPIO1
P6LED2 / nSPI_F_CS
P7LED1 / SPI_F_D1
P7LED0 / SPI_F_D0
P7LED2 / SPI_F_CLK
GPIO9
GPIO8
RTL8370NI-VB
Draft Datasheet
5.
Pin Assignments
5.1. Pin Assignments
P0MDIAP
P0MDIAN
P0MDIBP
P0MDIBN
AVDDL
P0MDICP
P0MDICN
P0MDIDP
P0MDIDN
AVDDH
P1MDIAP
P1MDIAN
P1MDIBP
P1MDIBN
AVDDL
P1MDICP
P1MDICN
P1MDIDP
P1MDIDN
PLLVDDL0
ATESTCK0
P2MDIAP
P2MDIAN
P2MDIBP
P2MDIBN
AVDDL
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RTL8370NI
XXXXXXX
GXXXB TAIWAN
E-PAD: GND
LQFP 128 E-PAD
Layer 2 Managed 8-port 10/100/1000 Switch Controller
7
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AVDDH
P7MDIDN
P7MDIDP
P7MDICN
P7MDICP
AVDDL
P7MDIBN
P7MDIBP
P7MDIAN
P7MDIAP
AVDDH
P6MDIDN
P6MDIDP
P6MDICN
P6MDICP
AVDDL
P6MDIBN
P6MDIBP
P6MDIAN
P6MDIAP
PLLVDDL1
P5MDIDN
P5MDIDP
P5MDICN
P5MDICP
AVDDL
Package Size 14mm x 20mm
Figure 3. RTL8370NI-VB Pin Assignments
5.2. Package Identification
Green package is indicated by the ‘G’ in GXXXB (Figure 3). The version is indicated by the ‘B’.
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
5.3. Pin Assignment Table
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input Pin
AI: Analog Input Pin
O: Output Pin
AO: Analog Output Pin
I/O: Bi-Direction Input/Output Pin
AI/O: Analog Bi-Direction Input/Output Pin
P: Digital Power Pin
AP: Analog Power Pin
G: Digital Ground Pin
AG: Analog Ground Pin
IPU: Input Pin With Pull-Up Resistor;
OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75K Ohm)
(Typical Value = 75K Ohm)
IPD: Input Pin With Pull-Down Resistor;
OPD: Output Pin With Pull-Down Resistor;
(Typical Value = 75K Ohm)
(Typical Value = 75K Ohm)
IS: Input Pin With Schmitt Trigger
Name
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
AVDDH
AGND
MDIREF
AVDDL
AVDDH
DVDDL
Table 1. Pin Assignment Table
Pin No. Type
Name
1
AI/O
DVDDL
2
AI/O
DVDDL
3
AI/O
DVDDL
4
AI/O
AVDDH
5
AP
P4MDIAP
6
AI/O
P4MDIAN
7
AI/O
P4MDIBP
8
AI/O
P4MDIBN
9
AI/O
AVDDL
10
AP
P4MDICP
11
AI/O
P4MDICN
12
AI/O
P4MDIDP
13
AI/O
P4MDIDN
14
AI/O
AVDDH
15
AP
P5MDIAP
16
AG
P5MDIAN
17
AO
P5MDIBP
18
AP
P5MDIBN
19
AP
AVDDL
20
P
P5MDICP
Layer 2 Managed 8-port 10/100/1000 Switch Controller
8
Pin No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Type
P
P
P
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
Name
P5MDICN
P5MDIDP
P5MDIDN
PLLVDDL1
P6MDIAP
P6MDIAN
P6MDIBP
P6MDIBN
AVDDL
P6MDICP
P6MDICN
P6MDIDP
P6MDIDN
AVDDH
P7MDIAP
P7MDIAN
P7MDIBP
P7MDIBN
AVDDL
P7MDICP
P7MDICN
P7MDIDP
P7MDIDN
AVDDH
GPIO8
GPIO9
P7LED2/SPI_F_CLK
P7LED0/SPI_F_D0
P7LED1/SPI_F_D1
P6LED2/nSPI_F_CS
P6LED0/GPIO1
P6LED1/GPIO7
P5LED2/GPIO0
P5LED0
P5LED1
DVDDL
DVDDIO
DVDDL
P4LED2/SLED_P7B/GPIO3
P4LED0/SLED_P6B/
STRP_EEPROM_MOD
P4LED1/SLED_P5B/GPIO6
P3LED1/SLED_G1A/GPIO5
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Type
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
P
P
P
I/OPU
I/OPU
81
82
I/OPU
I/OPU
Layer 2 Managed 8-port 10/100/1000 Switch Controller
Name
P3LED2/SLED_P3B/
STRP_EN_PWRLIGHT
P3LED0/SLED_P2B/
STRP_EN_FLASH
P2LED2/SLED_P1B/
STRP_DIS_8051
P2LED0/SLED_P0B/
STRP_DISAUTOLOAD
P2LED1/SLED_G1B/GPIO4
P1LED2/SLED_P3_7A/
STRP_SMI_SEL_1
P1LED0/SLED_P2_6A/
STRP_MID29
P1LED1/SLED_P1_5A/STRP_EN
_EEE
P0LED2/SLED_P0_4A/GPIO2/
STRP_EN_PHY
DVDDL
LED_DA/P0LED1/SLED_G2A
LED_CK/P0LED0/SLED_P4B/
STRP_SMI_SEL_0
DVDDL
AVDDH
XTALO
XTALI
nRESET
SCK/MMD_MDC
SDA/MMD_MDIO
AVDDH
P0MDIAP
P0MDIAN
P0MDIBP
P0MDIBN
AVDDL
P0MDICP
P0MDICN
P0MDIDP
P0MDIDN
AVDDH
P1MDIAP
P1MDIAN
P1MDIBP
P1MDIBN
AVDDL
P1MDICP
P1MDICN
9
Pin No.
83
Type
I/OPU
84
I/OPU
85
I/OPU
86
I/OPU
87
88
I/OPU
I/OPU
89
I/OPU
90
I/OPU
91
I/OPU
92
93
94
P
I/OPU
I/OPU
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
P
AP
AO
AI
IS
I/OPU
I/OPU
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
Name
P1MDIDP
P1MDIDN
PLLVDDL0
ATESTCK0
P2MDIAP
Pin No.
120
121
122
123
124
Type
AI/O
AI/O
AP
AO
AI/O
Layer 2 Managed 8-port 10/100/1000 Switch Controller
Name
P2MDIAN
P2MDIBP
P2MDIBN
AVDDL
GND
10
Pin No.
125
126
127
128
EPAD
Type
AI/O
AI/O
AI/O
AP
G
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
6.
Pin Descriptions
6.1. Media Dependent Interface Pins
Table 2. Media Dependent Interface Pins
Pin Name
P0MDIAP/N
P0MDIBP/N
P0MDICP/N
P0MDIDP/N
P1MDIAP/N
P1MDIBP/N
P1MDICP/N
P1MDIDP/N
P2MDIAP/N
P2MDIBP/N
P2MDICP/N
P2MDIDP/N
P3MDIAP/N
P3MDIBP/N
P3MDICP/N
P3MDIDP/N
P4MDIAP/N
P4MDIBP/N
P4MDICP/N
P4MDIDP/N
Pin No.
Type
Drive Description
103
104
105
106
108
109
110
111
113
114
115
116
118
119
120
121
124
125
126
127
1
2
3
4
6
7
8
9
11
12
13
14
25
26
27
28
30
31
32
33
AI/O
(mA)
10
Port 0 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-Tx and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
AI/O
10
Port 1 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-Tx and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
AI/O
10
Port 2 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-Tx and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
AI/O
10
Port 3 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-Tx and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
AI/O
10
Port 4 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-Tx and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
Layer 2 Managed 8-port 10/100/1000 Switch Controller
11
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
Pin Name
P5MDIAP/N
P5MDIBP/N
P5MDICP/N
P5MDIDP/N
P6MDIAP/N
P6MDIBP/N
P6MDICP/N
P6MDIDP/N
P7MDIAP/N
P7MDIBP/N
P7MDICP/N
P7MDIDP/N
Pin No.
Type
Drive Description
35
36
37
38
40
41
42
43
45
46
47
48
50
51
52
53
55
56
57
58
60
61
62
63
AI/O
(mA)
10
Port 5 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-Tx and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
AI/O
10
Port 6 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-Tx and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
AI/O
10
Port 7 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is
transmitted and received on all four pairs. For 100Base-Tx and
10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
MDIX can reverse the pairs MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination
resistor.
6.2. Parallel LED Pins
Table 3. Parallel LED Pins
Pin Name
Pin No.
Type
Drive Description
P7LED2/
SPI_F_CLK
67
I/OPU
(mA)
-
P7LED0/
SPI_F_D0
P7LED1/
SPI_F_D1
P6LED2/
nSPI_F_CS
P6LED0/GPIO1
68
I/OPU
-
69
I/OPU
-
70
I/OPU
-
71
I/OPU
-
P6LED1/GPIO7
72
I/OPU
-
P5LED2/GPIO0
73
I/OPU
-
Port 7 LED2 Output Signal.
P7LED2 indicates information is defined by register or EEPROM.
Port 7 LED0 Output Signal.
P7LED0 indicates information is defined by register or EEPROM.
Port 7 LED1 Output Signal.
P7LED1 indicates information is defined by register or EEPROM.
Port 6 LED2 Output Signal.
P6LED2 indicates information is defined by register or EEPROM.
Port 6 LED0 Output Signal.
P6LED0 indicates information is defined by register or EEPROM.
Port 6 LED1 Output Signal.
P6LED1 indicates information is defined by register or EEPROM.
Port 5 LED2 Output Signal.
P5LED2 indicates information is defined by register or EEPROM.
Layer 2 Managed 8-port 10/100/1000 Switch Controller
12
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
Pin Name
Pin No.
Type
Drive Description
P5LED0
74
I/OPU
(mA)
-
P5LED1
75
I/OPU
-
P4LED2
79
I/OPU
-
P4LED0/
STRP_EEPROM_
MOD
P4LED1/GPIO6
80
I/OPU
-
81
I/OPU
-
P3LED1/GPIO5
82
I/OPU
-
P3LED2/
STRP_EN_PWRL
IGHT
P3LED0/
STRP_EN_FLAS
H
P2LED2/
STRP_DIS_8051
P2LED0/
STRP_DISAUTO
LOAD
P2LED1/GPIO4
83
I/OPU
-
84
I/OPU
-
Port 3 LED0 Output Signal.
P3LED0 indicates information is defined by register or EEPROM.
85
I/OPU
-
86
I/OPU
-
Port 2 LED2 Output Signal.
P2LED2 indicates information is defined by register or EEPROM.
Port 2 LED0 Output Signal.
P2LED0 indicates information is defined by register or EEPROM.
87
I/OPU
-
P1LED2/
STRP_SMI_SEL_
1
P1LED0/
STRP_MID29
88
I/OPU
-
89
I/OPU
-
P1LED1/
STRP_EN_EEE
P0LED2/GPIO2/
STRP_EN_PHY
P0LED1/
LED_DA
P0LED0/
LED_CK/
STRP_SMI_SEL_
0
90
I/OPU
-
91
I/OPU
-
93
I/OPU
-
94
I/OPU
-
Port 5 LED0 Output Signal.
P5LED0 indicates information is defined by register or EEPROM.
Port 5 LED1 Output Signal.
P5LED1 indicates information is defined by register or EEPROM.
Port 4 LED2 Output Signal.
P4LED2 indicates information is defined by register or EEPROM.
Port 4 LED0 Output Signal.
P4LED0 indicates information is defined by register or EEPROM.
Port 4 LED1 Output Signal.
P4LED1 indicates information is defined by register or EEPROM.
Port 3 LED1 Output Signal.
P3LED1 indicates information is defined by register or EEPROM.
Port 3 LED2 Output Signal.
P3LED2 indicates information is defined by register or EEPROM.
Port 2 LED1 Output Signal.
P2LED1 indicates information is defined by register or EEPROM.
Port 1 LED2 Output Signal.
P1LED2 indicates information is defined by register or EEPROM.
Port 1 LED0 Output Signal.
P1LED0 indicates information is defined by register or EEPROM.
Port 1 LED1 Output Signal.
P1LED1 indicates information is defined by register or EEPROM.
Port 0 LED2 Output Signal.
P0LED2 indicates information is defined by register or EEPROM.
Port 0 LED1 Output Signal.
P0LED1 indicates information is defined by register or EEPROM.
Port 0 LED0 Output Signal.
P0LED0 indicates information is the same as P7LED0 and is defined
by register or EEPROM.
Layer 2 Managed 8-port 10/100/1000 Switch Controller
13
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
6.3. Scan Mode LED Pins
Table 4. Scan Mode LED Pins
Pin Name
Pin No.
Type
Drive Description
(mA)
SLED_G1A/P3LED1
82
I/OPU
Scan Mode LED Group A G1A Output Signal.
/GPIO5
SLED_G2A/LED_DA
93
I/OPU
Scan Mode LED Group A G2A Output Signal.
/P0LED1
SLED_P0_4A/GPIO2
91
I/OPU
Scan Mode LED Group A P0_4A Output Signal.
/STRP_EN_PHY/
P0LED2
SLED_P1_5A
90
I/OPU
Scan Mode Group A LED P1_5A Output Signal.
/P1LED1/
STRP_EN_EEE
SLED_P2_6A/
89
I/OPU
Scan Mode LED Group A P2_6A Output Signal.
P1LED0/
STRP_MID29
SLED_P3_7A
88
I/OPU
Scan Mode LED Group A P3_7A Output Signal.
/P1LED2/
STRP_SMI_SEL_1
SLED_G1B/P2LED1
87
I/OPU
Scan Mode LED Group B G1B Output Signal.
/GPIO4
SLED_P0B/P2LED0
86
I/OPU
Scan Mode LED Group B P0B Output Signal.
/STRP_DISAUTOLO
AD
SLED_P1B/P2LED2
85
I/OPU
Scan Mode LED Group B P1B Output Signal.
/STRP_DIS_8051
SLED_P2B/P3LED0/
84
I/OPU
Scan Mode LED Group B P2B Output Signal.
STRP_EN_FLASH
SLED_P3B/P3LED2/
83
I/OPU
Scan Mode LED Group B P3B Output Signal.
STRP_EN_PWRLIGH
T
SLED_P4B/LED_CK
94
I/OPU
Scan Mode LED Group B P4B Output Signal.
/P0LED0/
STRP_SMI_SEL_0
SLED_P5B/P4LED1
81
I/OPU
Scan Mode LED Group B P5B Output Signal.
/GPIO6
SLED_P6B/P4LED0
80
I/OPU
Scan Mode LED Group B P6B Output Signal.
/STRP_EEPROM_MO
D
SLED_P7B/P4LED2
79
I/OPU
Scan Mode LED Group B P7B Output Signal.
/GPIO3
Note: See section 8.19.2 Scan LED Mode, page 34 for details.
Layer 2 Managed 8-port 10/100/1000 Switch Controller
14
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
6.4. Serial Mode LED Pins
Table 5. Serial Mode LED Pins
Pin Name
LED_DA/ P0LED1
LED_CK/P0LED0/
STRP_SMI_SEL_0
Pin No.
Type
Drive Description
93
94
I/OPU
I/OPU
(mA)
-
Serial Shift Mode LED Data Signal.
Serial Shift Mode LED Clock Signal.
6.5. SPI Flash Pins
Table 6. SPI Flash Pins
Pin Name
Pin No.
Type
Drive Description
nSPI_F_CS/P6LED2
SPI_F_D1/P7LED1
70
69
I/OPU
I/OPU
(mA)
8
8
SPI_F_D0/P7LED0
68
I/OPU
8
SPI_F_CLK/P7LED2
67
I/OPU
8
SPI FLASH chip select signal.
In Serial I/O Mode
SPI Serial FLASH Serial Data Output (RTL8370NI-VB input
pin)
In Dual I/O Mode
SPI FLASH bi-directional pin (this is MSB)
In Serial I/O Mode
SPI Serial FLASH Serial Data Input (RTL8370NI-VB output
pin)
In Dual I/O Mode
SPI FLASH bi-directional pin (this is LSB)
SPI FLASH Clock.
6.6. Configuration Strapping Pins
Table 7. Configuration Strapping Pins
Pin Name
STRP_EEPROM_MOD/
P4LED0
Pin No.
80
Type
I/OPU
Description
EEPROM Mode Selection.
Pull Up: EEPROM 24Cxx Size greater than 16Kbits (24C32~)
Pull Down: EEPROM 24Cxx Size less than or equal to 16Kbit
(24C02~24C16).
Note: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
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Pin Name
STRP_EN_PWRLIGHT/
P3LED2
Pin No.
83
Type
I/OPU
STRP_EN_FLASH/
P3LED0
84
I/OPU
STRP_DIS_8051/P2LED2
85
I/OPU
STRP_DISAUTOLOAD/
P2LED0
86
I/OPU
STRP_SMI_SEL_1/
P1LED2
88
I/OPU
STRP_SMI_SEL_0/
P0LED0
94
I/OPU
Description
Enable LED Power On Light.
Pull Up: Enable LED Power On Light upon power on or reset
Pull Down: Disable LED Power On Light upon power on or reset
Note: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
Enable SPI Flash Interface
Pull Up: Enable SPI Flash Interface upon power on or reset
Pull Down: Disable SPI Flash Interface upon power on or reset
Note 1: Please Refer chapter 6.7 for detail description.
Note 2: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
Disable Embedded 8051.
Pull Up: Disable embedded 8051 upon power on or reset
Pull Down: Enable embedded 8051 upon power on or reset
Note 1: Please Refer chapter 6.7 for detail description.
Note 2: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
Disable EEPROM or SPI FLASH Auto download.
Pull Up: Disable EEPROM or SPI FLASH auto download upon
power on or reset
Pull Down: Enable EEPROM or SPI FLASH auto download upon
power on or reset
Note1: Please Refer chapter 6.7 for detail description.
Note2: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
External CPU Access Interface Selection.
STRP_SMI_SEL[1:0]:
00：LSB I2C mode
01：MSB I2C mode
10：Slave MII Management MDC/MDIO
11：Realtek I2C-like mode
Note: These pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
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Pin Name
STRP_MID29/P1LED0
Pin No.
89
Type
I/OPU
STRP_EN_EEE/P1LED1
90
I/OPU
STRP_EN_PHY/P0LED2
91
I/OPU
Description
Select Slave MII Management MDC/MDIO Device ID.
Pull Down: MDC/MDIO DEVID=0 upon power on or reset
Pull Up: MDC/MDIO DEVID=29 upon power on or reset
Note: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
EEE Enable/Disable
Pull Up: Enable MAC/PHY 100Base-TX & 1000Base-T EEE upon
power on or reset
Pull Down: Disable MAC/PHY 100Base-TX & 1000Base-T EEE
upon power on or reset
Note: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
Enable Embedded PHY.
Pull Up: Enable embedded PHY upon power on or reset
Pull Down: Disable embedded PHY upon power on or reset
Note: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active.
6.7. Configuration Strapping Pins (STRP_DISAUTOLOAD,
STRP_DIS_8051, STRP_EN_FLASH)
Table 8. Configuration Strapping Pins (STRP_DISAUTOLOAD, STRP_DIS_8051, STRP_EN_FLASH)
STRP_DIS STRP_EN
STRP_DISAUTOLOAD
Initial Stage (Power On or Reset) Loading Data
_8051
_FLASH
From
To
0
0
0
EEPROM
Embedded 8051 Instruction Memory
0
0
1
SPI FLASH
Embedded 8051 Instruction Memory
0
1
0
EEPROM
Register
1
Irrelevant
Irrelevant Do Nothing
Do Nothing
6.8. Miscellaneous Pins
Table 9. Miscellaneous Pins
Pin Name
XTALI
Pin No.
98
Type
AI
Description
25MHz Crystal Clock Input Pin.
25MHz +/-50ppm tolerance crystal reference input.
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Pin Name
XTALO
Pin No.
97
Type
AO
MDIREF
17
AO
GPIO8
GPIO9
GPIO1/P6LED0
GPIO7/P6LED1
GPIO0/P5LED2
GPIO3/P4LED2
GPIO6/P4LED1
GPIO5/P3LED1
GPIO4/P2LED1
GPIO2/P0LED2
SCK/MMD_MDC
65
66
71
72
73
79
81
82
87
91
100
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
SDA/MMD_MDI
O
nRESET
101
I/OPU
99
IS/PU
Description
25MHz Crystal Clock Output Pin.
25MHz +/-50ppm tolerance crystal output.
Reference Resistor.
A 2.49K ohm (1%) resistor must be connected between MDIREF and
GND.
General Purpose Input/Output Interfaces IO8.
General Purpose Input/Output Interfaces IO9.
General Purpose Input/Output Interfaces IO1.
General Purpose Input/Output Interfaces IO7.
General Purpose Input/Output Interfaces IO0.
General Purpose Input/Output Interfaces IO3.
General Purpose Input/Output Interfaces IO6.
General Purpose Input/Output Interfaces IO5.
General Purpose Input/Output Interfaces IO4.
General Purpose Input/Output Interfaces IO2.
EEPROM I2C Host Interface Clock/Slave I2C-like Interface
Clock/Slave MII Management Interface Clock
EEPROM I2C Host Interface Data/Slave I2C-like Interface
Data/Slave MII Management Interface Data
System Reset Input Pin.
When low active will reset the RTL8370NI-VB.
6.9. Test Pins
Table 10. Test Pins
Pin Name
ATESTCK0
Pin No.
123
Type
AO
Description
Reserved for Internal Use. Must be left floating.
6.10. Power and GND Pins
Table 11. Power and GND Pins
Pin Name
DVDDIO
DVDDL
AVDDH
AVDDL
PLLVDDL0
PLLVDDL1
GND
AGND
Pin No.
77
20, 21, 22, 23, 76,
78, 92, 95
5, 15, 19, 24, 34, 54,
64, 96, 102, 112
10, 18, 29, 39, 49,
59, 107, 117, 128
122
44
EPAD
16
Type
P
P
Description
Digital I/O High Voltage Power.
Digital Low Voltage Power.
AP
Analog High Voltage Power.
AP
Analog Low Voltage Power.
AP
AP
G
AG
PLL0 Low Voltage Power.
PLL1 Low Voltage Power.
GND.
Analog GND.
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7.
Physical Layer Functional Overview
7.1. MDI Interface
The RTL8370NI-VB embeds eight Gigabit Ethernet PHYs in one chip. Each port uses a single common
MDI interface to support 1000Base-T, 100Base-Tx, and 10Base-T. This interface consists of four signal
pairs-A, B, C, and D. Each signal pair consists of two bi-directional pins that can transmit and receive at
the same time. The MDI interface has internal termination resistors, and therefore reduces BOM cost and
PCB complexity. For 1000Base-T, all four pairs are used in both directions at the same time. For 10/100
links and during auto-negotiation, only pairs A and B are used.
7.2. 1000Base-T Transmit Function
The 1000Base-TX transmit function performs 8B/10B coding, scrambling, and 4D-PAM5 encoding.
These code groups are passed through a waveform-shaping filter to minimize EMI effects, and are
transmitted onto 4-pair CAT5 cable at 125MBaud/s through a D/A converter.
7.3. 1000Base-T Receive Function
Input signals from the media pass through the sophisticated on-chip hybrid circuit to subtract the
transmitted signal from the input signal for effective reduction of near-end echo. The received signal is
then processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. The 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz.
The RX MAC retrieves the packet data from the internal receive MII/GMII interface and sends it to the
packet buffer manager.
7.4. 100Base-TX Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling,
NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then
scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such
that EMI effects can be reduced significantly.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit
stream is driven onto the network media in the form of MLT-3 signaling. The MLT-3 multi-level
signaling technology moves the power spectrum energy from high frequency to low frequency, which
also reduces EMI emissions.
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7.5. 100Base-TX Receive Function
The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to
compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to
convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error
rate. A de-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL
circuit. Finally, the converted parallel data is fed into the MAC.
7.6. 10Base-T Transmit Function
The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The
internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external
filter.
7.7. 10Base-T Receive Function
The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit
detects the signal level is above squelch level.
7.8. Auto-Negotiation for UTP
The RTL8370NI-VB obtains the states of duplex, speed, and flow control ability for each port in UTP
mode through the auto-negotiation mechanism defined in the IEEE 802.3 specifications. During autonegotiation, each port advertises its ability to its link partner and compares its ability with advertisements
received from its link partner. By default, the RTL8370NI-VB advertises full capabilities (1000Full,
100Full, 100Half, 10Full, 10Half) together with flow control ability.
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7.9. Crossover Detection and Auto Correction
The RTL8370NI-VB automatically determines whether or not it needs to crossover between pairs (see
Table 12) so that an external crossover cable is not required. When connecting to another device that does
not perform MDI crossover, when necessary, the RTL8370NI-VB automatically switches its pin pairs to
communicate with the remote device. When connecting to another device that does have MDI crossover
capability, an algorithm determines which end performs the crossover function.
The crossover detection and auto correction function can be disabled via register configuration. The pin
mapping in MDI and MDI Crossover mode is given below.
Pairs
A
B
C
D
Table 12. Media Dependent Interface Pin Mapping
MDI
MDI Crossover
1000Base-T
100Base-TX
10Base-T
1000Base-T
100Base-TX
A
TX
TX
B
RX
B
RX
RX
A
TX
C
Unused
Unused
D
Unused
D
Unused
Unused
C
Unused
10Base-T
RX
TX
Unused
Unused
7.10. Polarity Correction
The RTL8370NI-VB automatically corrects polarity errors on the receiver pairs in 1000Base-T and
10Base-T modes. In 100Base-TX mode, the polarity is irrelevant.
In 1000Base-T mode, receive polarity errors are automatically corrected based on the sequence of idle
symbols. Once the de-scrambler is locked, the polarity is also locked on all pairs. The polarity becomes
unlocked only when the receiver loses lock.
In 10Base-T mode, polarity errors are corrected based on the detection of valid spaced link pulses. The
detection begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The
polarity becomes unlocked when the link is down.
Link Partner
Switch Controller
+
RX _
TX
+
_ TX
_
+
+
_
+
_ RX
Figure 4. Conceptual Example of Polarity Correction
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General Function Description
8.
8.1. Reset
8.1.1.
Hardware Reset
In a power-on reset, an internal power-on reset pulse is generated and the RTL8370NI-VB will start the
reset initialization procedures. These are:
Determine various default settings via the hardware strap pins at the end of the nRESET signal
Autoload the configuration from EEPROM if EEPROM is detected
Complete the embedded SRAM BIST process
Initialize the packet buffer descriptor allocation
Initialize the internal registers and prepare them to be accessed by the external CPU
8.1.2.
Software Reset
The RTL8370NI-VB supports two software resets; a chip reset and a soft reset.
8.1.2.1 CHIP_RESET
When CHIP_RESET is set to 0b1 (write and self-clear), the chip will take the following steps:
1. Download configuration from strap pin and EEPROM
2. Start embedded SRAM BIST (Built-In Self Test)
3. Clear all the Lookup and VLAN tables
4. Reset all registers to default values
5. Restart the auto-negotiation process
8.1.2.2 SOFT_RESET
When SOFT_RESET is set to 0b1 (write and self-clear), the chip will clear the FIFO and re-start the
packet buffer link list.
8.2. IEEE 802.3x Full Duplex Flow Control
The RTL8370NI-VB supports IEEE 802.3x flow control in 10/100/1000M modes. Flow control can be
decided in two ways:
When Auto-Negotiation is enabled, flow control depends on the result of NWay
When Auto-Negotiation is disabled, flow control depends on register definition
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8.3. Half Duplex Flow Control
In half-duplex mode, the CSMA/CD media access method is the means by which two or more stations
share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the
medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If
the message collides with that of another station, then each transmitting station intentionally transmits for
an additional predefined period to ensure propagation of the collision throughout the system. The station
remains silent for a random amount of time (backoff) before attempting to transmit again.
When a transmission attempt has terminated due to a collision, it is retried until it is successful. The
scheduling of the retransmissions is determined by a controlled randomization process called “truncated
binary exponential backoff”. At the end of enforcing a collision (jamming), the switch delays before
attempting to retransmit the frame. The delay is an integer multiple of slot time (512 bit times). The
number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed
random integer ‘r’ in the range:
0 ≤ r < 2k
where:
k = min (n, backoffLimit). The backoffLimit for the RTL8370NI-VB is 9.
The half-duplex back-off algorithm in the RTL8370NI-VB does not have the maximum retry count
limitation of 16 (as defined in IEEE 802.3). This means packets in the switch will not be dropped if the
back-off retry count is over 16.
8.3.1.
Back-Pressure Mode
In Back-Pressure mode, the RTL8370NI-VB sends a 12-byte jam pattern (preamble+SFD+4bytes 0xAA)
to collide with incoming packets when congestion control is activated. RTL8370NI-VB supports
48PASS1 function, which receives one packet after 48 consecutive jam collisions (data collisions are not
included in the 48). Enable this function to prevent port partition after 63 consecutive collisions (data
collisions + consecutive jam collisions).
8.4. Search and Learning
Search
When a packet is received, the RTL8370NI-VB uses the destination MAC address, Filtering Identifier
(FID) and enhanced Filtering Identifier (FID) to search the 4096-entry look-up table. The 48-bit MAC
address, 4-bit FID and 3-bit EFID use a hash algorithm to calculate a 12-bit index value. The
RTL8370NI-VB uses the index to compare the packet MAC address with the entries (MAC addresses) in
the look-up table. This is the ‘Address Search’. If the destination MAC address is not found, the switch
will broadcast the packet according to VLAN configuration.
Learning
The RTL8370NI-VB uses the source MAC address, FID, and EFID of the incoming packet to hash into a
12-bit index. It then compares the source MAC address with the data (MAC addresses) in this index. If
there is a match with one of the entries, the RTL8370NI-VB will update the entry with new information.
If there is no match and the 4096 entries are not all occupied by other MAC addresses, the RTL8370NILayer 2 Managed 8-port 10/100/1000 Switch Controller
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VB will record the source MAC address and ingress port number into an empty entry. This process is
called ‘Learning’.
The RTL8370NI-VB supports a 64-entry Content Addressable Memory (CAM) to avoid look-up table
hash collisions. When all 4K entries in the look-up table index are occupied, the source MAC address can
be learned into the 64-entry CAM. If both the look-up table and the CAM are full, the source MAC
address will not be learned in the RTL8370NI-VB.
Address aging is used to keep the contents of the address table correct in a dynamic network topology.
The look-up engine will update the time stamp information of an entry whenever the corresponding
source MAC address appears. An entry will be invalid (aged out) if its time stamp information is not
refreshed by the address learning process during the aging time period. The aging time of the
RTL8370NI-VB is between 200 and 400 seconds (typical is 300 seconds).
8.5. SVL and IVL/SVL
The RTL8370NI-VB supports a 4K-group Filtering Identifier (FID) for L2 search and learning. In default
operation, all VLAN entries belong to the same FID. This is called Shared VLAN Learning (SVL). If
VLAN entries are configured to different FIDs, then the same source MAC address with multiple FIDs
can be learned into different look-up table entries. This is called Independent VLAN Learning and Shared
VLAN Learning (IVL/SVL).
8.6. Illegal Frame Filtering
Illegal frames such as CRC error packets, runt packets (length maximum length) will be discarded by the RTL8370NI-VB. The maximum packet length may be
set to 1522, 1536, 1552, or 16384 bytes.
8.7. IEEE 802.3 Reserved Group Addresses Filtering Control
The RTL8370NI-VB supports the ability to drop/forward IEEE 802.3 specified reserved group MAC
addresses: 01-80-C2-00-00-00 to 01-80-C2-00-00-2F. The default setting enables forwarding of these
reserved group MAC address control frames. Frames with group MAC address 01-80-C2-00-00-01
(802.3x Pause) and 01-80-C2-00-00-02 (802.3ad LACP) will always be filtered. Table 13 shows the
Reserved Multicast Address (RMA) configuration mode from 01-80-C2-00-00-00 to 01-80-C2-00-00-2F.
Table 13. IEEE 802.3 Reserved Group Addresses Filtering Control
Assignment
Bridge Group Address
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation
IEEE Std 802.3ad Slow Protocols-Multicast Address
IEEE Std 802.1X PAE Address
All LANs Bridge Management Group Address
GMRP Address
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Value
01-80-C2-00-00-00
01-80-C2-00-00-01
01-80-C2-00-00-02
01-80-C2-00-00-03
01-80-C2-00-00-10
01-80-C2-00-00-20
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Assignment
GVRP Address
Undefined 802.1 Bridge Address
Value
01-80-C2-00-00-21
01-80-C2-00-00-04
|
01-80-C2-00-00-0F
01-80-C2-00-00-22
|
01-80-C2-00-00-2F
Undefined GARP Address
8.8. Broadcast/Multicast/Unknown DA Storm Control
The RTL8370NI-VB enables or disables per-port broadcast/multicast/unknown DA storm control by
setting registers (default is disabled). After the receiving rate of broadcast/multicast/unknown DA packets
exceeds a reference rate, all other broadcast/multicast/unknown DA packets will be dropped. The
reference rate is set via register configuration.
8.9. Port Security Function
The RTL8370NI-VB supports three types of security function to prevent malicious attacks:
Per-port enable/disable SA auto-learning for an ingress packet
Per-port enable/disable look-up table aging update function for an ingress packet
Per-port enable/disable drop all unknown DA packets
8.10. MIB Counters
The RTL8370NI-VB supports a set of counters to support management functions.
MIB-II (RFC 1213)
Ethernet-Like MIB (RFC 3635)
Interface Group MIB (RFC 2863)
RMON (RFC 2819)
Bridge MIB (RFC 1493)
Bridge MIB Extension (RFC 2674)
8.11. Port Mirroring
The RTL8370NI-VB supports one set of port mirroring functions for all ports. The TX, or RX, or both
TX/RX packets of the source port can be monitored from a mirror port.
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8.12. VLAN Function
The RTL8370NI-VB supports 4K VLAN groups. These can be configured as port-based VLANs,
IEEE 802.1Q tag-based VLANs, and Protocol-based VLANs. Two ingress-filtering and egress-filtering
options provide flexible VLAN configuration:
Ingress Filtering
Acceptable frame types of the ingress process can be set to ‘admit all’, ‘admit untagged only’, and
‘admit tagged only’
‘Admit’ or ‘Discard’ frames associated with a VLAN for which that port is not in the member set
Egress Filtering
‘Forward’ or ‘Discard’ Leaky VLAN frames between different VLAN domains
‘Forward’ or ‘Discard’ Multicast VLAN frames between different VLAN domains
The VLAN tag can be inserted or removed at the output port. The RTL8370NI-VB will insert a Port VID
(PVID) for untagged frames, or remove the tag from tagged frames. The RTL8370NI-VB also supports a
special insert VLAN tag function to separate traffic from the WAN and LAN sides in Router and
Gateway applications.
In embedded system applications, the CPU may want to know which input port this packet came from.
The RTL8370NI-VB supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on
egress. Using this function, VID information carried in the VLAN tag will be changed to PVID. The
RTL8370NI-VB also provides an option to admit VLAN tagged packets with a specific PVID only. If
this function is enabled, it will drop non-tagged packets and packets with an incorrect PVID.
8.12.1.
Port-Based VLAN
This default configuration of the VLAN function can be modified via an I2C-like Slave or Slave MII
Management interface. The 4096-entry VLAN Table designed into the RTL8370NI-VB provides full
flexibility for users to configure the input ports to associate with different VLAN groups. Each input port
can join with more than one VLAN group.
Port-based VLAN mapping is the simplest implicit mapping rule. Each ingress packet is assigned to a
VLAN group based on the input port. It is not necessary to parse and inspect frames in real-time to
determine their VLAN association. All the packets received on a given input port will be forwarded to
this port’s VLAN members.
8.12.2.
IEEE 802.1Q Tag-Based VLAN
The RTL8370NI-VB supports 4K VLAN entries to perform 802.1Q tag-based VLAN mapping. In
802.1Q VLAN mapping, the RTL8370NI-VB uses a 12-bit explicit identifier in the VLAN tag to
associate received packets with a VLAN. The RTL8370NI-VB compares the explicit identifier in the
VLAN tag with the 4K VLAN Table to determine the VLAN association of this packet, and then
forwards this packet to the member set of that VLAN. Two VIDs are reserved for special purposes. One
of them is all 1’s, which is reserved and currently unused. The other is all 0’s, which indicates a priority
tag. A priority-tagged frame should be treated as an untagged frame.
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When ‘802.1Q tag aware VLAN’ is enabled, the RTL8370NI-VB performs 802.1Q tag-based VLAN
mapping for tagged frames, but still performs port-based VLAN mapping for untagged frames. If ‘802.1Q
tag aware VLAN’ is disabled, the RTL8370NI-VB performs only port-based VLAN mapping both on
non-tagged and tagged frames. The processing flow when ‘802.1Q tag aware VLAN’ is enabled is
illustrated below.
Two VLAN ingress filtering functions are supported in registers by the RTL8370NI-VB. One is the
‘VLAN tag admit control’. The other is ‘VLAN member set ingress filtering’, which will drop frames if
the ingress port is not in the member set.
8.12.3.
Protocol-Based VLAN
The RTL8370NI-VB supports a 4-group Protocol-based VLAN configuration. The packet format can be
RFC 1042, LLC, or Ethernet, as shown in Figure 5. There are 4 configuration tables to assign the frame
type and corresponding field value. Taking IP packet configuration as an example, the user can configure
the frame type to be ‘Ethernet’ and value to be ‘0x0800’. Each table will index to one of the entries in the
4K-entry VLAN table. The packet stream will match the protocol type and the value will follow the
VLAN member configuration of the indexed entry to forward the packets.
Ethernet
DA/SA
TYPE
……
RFC_1042
DA/SA
Length
AA- AA-03
00-00-00
LLC_Other
DA/SA
Length
DSAP/SSAP
……
TYPE
……
Frame Input
Type/Length is
00-00~05-FF?
6 bytes after
Type/Length are
AA-AA-03-00-00-00?
No
No
Frame Type
= Ethernet
Frame Type
= LLC_ Other
Frame Type
= RFC_1042
Figure 5. Protocol-Based VLAN Frame Format and Flow Chart
8.12.4.
Port VID
In a router application, the router may want to know which input port this packet came from. The
RTL8370NI-VB supports Port VID (PVID) for each port to insert a PVID in the VLAN tag for untagged
or priority tagged packets on egress. When 802.1Q tag-aware VLAN is enabled, VLAN tag admit control
is enabled, and non-PVID Discard is enabled at the same time. When these functions are enabled, the
RTL8370NI-VB will drop non-tagged packets and packets with an incorrect PVID.
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8.13. QoS Function
The RTL8370NI-VB supports 8 priority queues and input bandwidth control. Packet priority selection
can depend on Port-based priority, 802.1p/Q Tag-based priority, IPv4/IPv6 DSCP-based priority, and
ACL-based priority. When multiple priorities are enabled in the RTL8370NI-VB, the packet’s priority
will be assigned based on the priority selection table.
Each queue has one leaky bucket for Average Packet Rate. Per-queue in each output port can be set as
Strict Priority (SP) or Weighted Fair Queue (WFQ) for packet scheduling algorithm.
8.13.1.
Input Bandwidth Control
Input bandwidth control limits the input bandwidth. When input traffic is more than the RX Bandwidth
parameter, this port will either send out a ‘pause ON’ frame, or drop the input packet depending on
register setup. Per-port input bandwidth control rates can be set from 8Kbps to 1Gbps (in 8Kbps steps).
8.13.2.
Priority Assignment
Priority assignment specifies the priority of a received packet according to various rules. The
RTL8370NI-VB can recognize the QoS priority information of incoming packets to give a different
egress service priority.
The RTL8370NI-VB identifies the priority of packets based on several types of QoS priority information:
Port-based priority
802.1p/Q-based priority
IPv4/IPv6 DSCP-based priority
ACL-based priority
VLAN-based priority
MAC-based priority
SVLAN-based priority
8.13.3.
Priority Queue Scheduling
The RTL8370NI-VB supports MAX-MIN packet scheduling.
Packet scheduling offers two modes:
APR leaky bucket, which specifies the average rate of one queue
Weighted Fair Queue (WFQ), which decides which queue is selected in one slot time to guarantee the
minimal packet rate of one queue
In addition, each queue of each port can select Strict Priority or WFQ packet scheduling according to
packet scheduling mode. Figure 6 shows the RTL8370NI-VB packet-scheduling diagram.
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Guaranteed Max.
Guaranteed Min.
APR Leaky
Bucket
WFQ Leaky Bucket
Queue 0
Queue 1
Scheduler
Queue 7
Figure 6. RTL8370NI-VB MAX-MIN Scheduling Diagram
8.13.4.
IEEE 802.1p/Q and DSCP Remarking
The RTL8370NI-VB supports the IEEE 802.1p/Q and IP DSCP (Differentiated Services Code Point)
remarking function. When packets egress from one of the 8 queues, the packet’s 802.1p/Q priority and IP
DSCP can optionally be remarked to a configured value. Each output queue has a 3-bit 802.1p/Q, and a 6bit IP DSCP value configuration register.
8.13.5.
ACL-Based Priority
The RTL8370NI-VB supports 96-entry ACL (Access Control List) rules. When a packet is received, its
physical port, Layer2, Layer3, and Layer4 information are recorded and compared to ACL entries.
If a received packet matches multiple entries, the entry with the lowest address is valid. If the entry is
valid, the action bit and priority bit will be applied.
If the action bit is ‘Drop’, the packet will be dropped. If the action bit is ‘CPU’, the packet will be
trapped to the CPU instead of forwarded to non-CPU ports (except where it will be dropped by rules
other than the ACL rule)
If the action bit is ‘Permit’, ACL rules will override other rules
If the action bit is ‘Mirror’, the packet will be forwarded to the mirror port and the L2 lookup result
destination port. The mirror port indicates the port configured in the port mirror mechanism
The priority bit will take effect only if the action bit is ‘CPU’, ‘Permit’, and ‘Mirror’. The Priority bit
is used to determine the packet queue ID according to the priority assignment mechanism
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8.14. IGMP & MLD Snooping Function
The RTL8370NI-VB can trap all IGMP and MLD packets to the CPU port. The CPU processes these
packets, gets the IP multicast group information of all ports, and writes the correct multicast entry to the
lookup table via I2C-like Slave interface or Slave MII Management interface.
8.15. IEEE 802.1x Function
The RTL8370NI-VB supports IEEE 802.1x Port-based/MAC-based Access Control.
Port-Based Access Control for each port
Authorized Port-Based Access Control for each port
Port-Based Access Control Direction for each port
MAC-Based Access Control for each port
MAC-Based Access Control Direction
Optional Unauthorized Behavior
Guest VLAN
8.15.1.
Port-Based Access Control
Each port of the RTL8370NI-VB can be set to 802.1x port-based authenticated checking function usage
and authorized status. Ports with 802.1X unauthorized status will drop received/transmitted frames.
8.15.2.
Authorized Port-Based Access Control
If a dedicated port is set to 802.1x port-based access control, and passes the 802.1x authorization, then its
port authorization status can be set to authorized.
8.15.3.
Port-Based Access Control Direction
Ports with 802.1X unauthorized status will drop received/transmitted frames only when port authorization
direction is ‘BOTH’. If the authorization direction of an 802.1X unauthorized port is IN, incoming frames
to that port will be dropped, but outgoing frames will be transmitted.
8.15.4.
MAC-Based Access Control
MAC-Based Access Control provides authentication for multiple logical ports. Each logical port
represents a source MAC address. There are multiple logical ports for a physical port. When a logical port
or a MAC address is authenticated, the relevant source MAC address has the authorization to access the
network. A frame with a source MAC address that is not authenticated by the 802.1x function will be
dropped or trapped to the CPU.
8.15.5.
MAC-Based Access Control Direction
Unidirectional and Bi-directional control are two methods used to process frames in 802.1x. As the
system cannot predict which port the DA is on, a system-wide MAC-based access control direction setup
is provided for determining whether receiving or bi-direction must be authorized.
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If MAC-based access control direction is BOTH, then received frames with unauthenticated SA or
unauthenticated DA will be dropped. When MAC-based access control direction is IN, only received
frames with unauthenticated SA will be dropped.
8.15.6.
Optional Unauthorized Behavior
Both in Port-Based Network Access Control and MAC-Based Access Control, a whole system control
setup is provided to determine unauthorized frame dropping, trapping to CPU, or tagging as belonging to
a Guest VLAN (see the following ‘Guest VLAN’ section).
8.15.7.
Guest VLAN
When the RTL8370NI-VB enables the Port-based or MAC-based 802.1x function, and the connected PC
does not support the 802.1x function or does not pass the authentication procedure, the RTL8370NI-VB
will drop all packets from this port.
The RTL8370NI-VB also supports one Guest VLAN to allow unauthorized ports or packets to be
forwarded to a limited VLAN domain. The user can configure one VLAN ID and member set for these
unauthorized packets.
8.16. IEEE 802.1D Function
When using IEEE 802.1D, the RTL8370NI-VB supports 16 sets and four status for each port for CPU
implementation 802.1D (STP) and 802.1s (MSTP) function:
Disabled: The port will not transmit/receive packets, and will not perform learning
Blocking: The port will only receive BPDU spanning tree protocol packets, but will not transmit any
packets, and will not perform learning
Learning: The port will receive any packet, including BPDU spanning tree protocol packets, and will
perform learning, but will only transmit BPDU spanning tree protocol packets
Forwarding: The port will transmit/receive all packets, and will perform learning
The RTL8370NI-VB also supports a per-port transmission/reception enable/disable function. Users can
control the port state via register.
8.17. Embedded 8051
An 8051 MCU is embedded in the RTL8370NI-VB to support management functions. The 8051 MCU
can access all of the registers in the RTL8370NI-VB through the internal bus. With the Network Interface
Circuit (NIC) acting as the data path, the 8051 MCU connects to the switch core and can transmit frames
to or receive frames from the Ethernet network. The features of the 8051 MCU are listed below:
256 Bytes fast internal RAM
On-chip 48K data memory
On-chip 16K code memory
Supports code-banking
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12KBytes NIC buffer
EEPROM read/write ability
8.18. Realtek Cable Test (RTCT)
The RTL8370NI-VB physical layer transceivers use DSP technology to implement the Realtek Cable
Test (RTCT) feature. The RTCT function can be used to detect short, open or impedance mismatch in
each differential pair. The RTL8370NI-VB also provides LEDs to indicate test status and results.
8.19. LED Indicator
The RTL8370NI-VB supports parallel mode LEDs, scan mode LEDs and serial mode LEDs for each port.
Each port has three LED indicators, LED0, LED1, and LED2. Each may have different indicator
information (defined in Table 14). Upon reset, the RTL8370NI-VB supports chip diagnostics and LED
operation test by blinking all LEDs once.
LED Statuses
LED_Off
Dup/Col
Link/Act
Spd1000
Spd100
Spd10
Spd1000/Act
Spd100/Act
Spd10/Act
Spd100 (10)/Act
Act
Table 14. LED Definitions
Description
LED always off.
Duplex/Collision, Indicator. Blinking when collision occurs. Low for full duplex, and high for
half-duplex mode.
Link, Activity Indicator. Low for link established. Link/Act Blinking when the corresponding
port is transmitting or receiving.
1000Mbps Speed Indicator. Low for 1000Mbps.
100Mbps Speed Indicator. Low for 100Mbps.
10Mbps Speed Indicator. Low for 10Mbps.
1000Mbps Speed/Activity Indicator. Low for 1000Mbps. Blinking when the corresponding
port is transmitting or receiving.
100Mbps Speed/Activity Indicator. Low for 100Mbps. Blinking when the corresponding port
is transmitting or receiving.
10Mbps Speed/Activity Indicator. Low for 10Mbps. Blinking when the corresponding port is
transmitting or receiving.
10/100Mbps Speed/Activity Indicator. Low for 10/100Mbps. Blinking when the corresponding
port is transmitting or receiving.
Activity Indicator. Act blinking when the corresponding port is transmitting or receiving.
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8.19.1.
Parallel LED Mode
The RTL8370NI-VB supports parallel LED mode. The parallel LED pin also supports pin strapping
configuration functions. The PnLED0, PnLED1, and PnLED2 pins are dual-function pins; input operation
for configuration upon reset, and output operation for LED after reset. If the pin input is pulled high upon
reset, the pin output is active low after reset. If the pin input is pulled down upon reset, the pin output is
active high after reset. Typical values for pull-up/pull-down resistors are 4.7K.
The PnLED1 can be combined with PnLED0 or PnLED2 as a Bi-color LED.
LED_PnLED1 should operate with the same polarity as other Bi-color LED pins. For example:
P0LED1 should pull up upon reset if P0LED1 is combined with P0LED2 as a Bi-color LED, and
P0LED2 input is pulled high upon reset. In this configuration, the output of these pins is active low
after reset
P0LED1 should be pulled down upon reset if P0LED1 is combined with P0LED2 as a Bi-color LED,
and P0LED2 input is pulled down upon reset. In this configuration, the output of these pins is active
high after reset
Pull-Down
Pull-Up
DVDDIO
4.7K
ohm
LED Pin
470 ohm
RTL8370NI-VB
470 ohm
4.7K
ohm
RTL8370NI-VB
LED Pin
LED Pins Output Active High
LED Pins Output Active Low
Figure 7. Pull-Up and Pull-Down of LED Pins for Single-Color LED
Pull-Down
Pull-Up
SPD 1000
4.7K
ohm
DVDDIO
SPD 100
470ohm
470ohm
RTL8370 NI-VB
Yellow
SPD100
4.7K ohm
RTL8370NI-VB
Green
Yellow
SPD1000
4.7K
ohm
Green
4.7K ohm
LED Pins Output Active High
LED Pins Output Active Low
Figure 8. Pull-Up and Pull-Down of LED Pins for Bi-Color LED
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8.19.2.
Scan LED Mode
The RTL8370NI-VB provides scan LED mode to reduce LED pins but keep the same number of LED
indicators as parallel LED mode. Each port includes one bi-color and one single-color LED. The bi-color
LED consists of LED1 & LED 2 (Figure 10) and the single-color LED is driven by LED0 (Figure 9).
In the bi-color LED circuit, a 30K ohm parallel-connected resistor must be used if the strapping pin on
either side of the bi-color LED is pulled low. Otherwise it is not required. Some Scan mode LED pins also
support strapping pins and will not affect the LED polarity.
SLED_P3/ 7A
P3 LED 0
P7 LED 0
SLED_P2/ 6 A
Controller
P2 LED 0
P6 LED 0
SLED_P1/ 5 A
P1 LED 0
P5 LED 0
SLED_P0/ 4 A
P0 LED 0
P4 LED 0
0 ohm
0 ohm
0 ohm
0 ohm
S1LED_ G 2 A
S1LED_ G1 A
Figure 9. Scan Mode LED Connection Diagram (Group A: Single-Color LED (LED0))
30K ohm
SLED _ P 7 B
SLED _ P 6 B
SLED _ P 5 B
SLED _ P 4 B
P 7 LED 2
Yellow
30K ohm
P 6 LED 2
Yellow
30K ohm
P 5 LED 2
Yellow
30K ohm
P 4 LED 2
Yellow
30K ohm
P 3 LED 2
Yellow
30K ohm
P 2 LED 2
Yellow
30K ohm
P 1 LED 2
Yellow
30K ohm
P 0 LED 2
Yellow
Controller
SLED _ P 3 B
SLED _ P 2 B
SLED _ P 1 B
SLED _ P 0 B
Green
P 7 LED 1
Green
P 6 LED 1
Green
P5 LED 1
Green
P4 LED 1
Green
P3 LED 1
Green
P2 LED 1
Green
P1 LED 1
Green
P0 LED 1
SLED _ G 1 B
Figure 10. Scan Mode LED Connection Diagram (Group B: Bi-Color LED (LED1 & LED2))
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8.19.3.
Serial LED Mode
The RTL8370NI-VB supports serial shift LED mode to show the speed, link status and other information
of the port status.
In serial led mode, the RTL8370NI-VB supports per-port one/two/three single-color LED. The serial
LED default is per-port three single-color LED, and the RTL8370NI-VB support 8-port (port0~port7)
LED.
8.19.3.1 Serial Shift LED Default Mode, Per-Port Three Single-Color LED
T3=16ms
T2=2.538us
T1 = 108ns
T4 = (0.4~0.6) * T1
LED_CK
LED_DA
P7
P6
P5
P3
P2
P1
P0
P4
P7
P6
P5
P3
P2
P1
P0
P4
P7
P6
P5
P3
P2
P1
P0
P4
LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED2 LED2 LED2 LED2 LED2 LED2 LED2 LED2
P7
P5
P6
LED0 LED0 LED0
Figure 11. RTL8370NI-VB Serial Led Mode Shift Sequence (Per-Port Three Single-Color LED)
A 74HC164 8-Bit Serial-In, Parallel-Out Shift Register captures the per-port link status and diagnostic
information. The related circuit design is shown in the following diagram.
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3.3V
LED_DA
3.3V
LED_CK
A
B
CLK
P0_LED2
P1_LED2
QA
QB
P2_LED2
P3_LED2
P4_LED2
QC
74HC164
The first
74HC164
QD
QE
P5_LED2
P6_LED2
QF
QG
P7_LED2
QH
A
B
CLK
3.3V
LED_CK
P0_LED1
P1_LED1
P2_LED1
QA
QB
QC
74HC164
The second
74HC164
P3_LED1
P4_LED1
P5_LED1
P6_LED1
QD
QE
QF
QG
P7_LED1
QH
A
B
CLK
3.3V
LED_CK
P0_LED0
P1_LED0
P2_LED0
QA
QB
QC
74HC164
The third
74HC164
470 ohm
P3_LED0
P4_LED0
P5_LED0
P6_LED0
QD
QE
QF
QG
P7_LED0
QH
Figure 12. RTL8370NI-VB+74HC164 Serial LED Connection Diagram (Per-Port Three Single-Color LED)
The RTL8231’s shift register mode can reserve the serial data, and output parallel data in order. There are
36 shift registers in the RTL8231. The output data sequence is shown below:
LED Pin Output
LED[0]
SI
D
Q
LED[1]
D
Q
LED[2]
D
Q
LED[35]
D
Q
SO
CLK_IN
Figure 13. RTL8231 Serial LED Output Data Sequence
To latch the current serial data received at the SI pin, and shift the preceding data to the next stage at the
each rising edge of the serial clock, first the serial data is input to the RTL8231, and then output from the
pin 15 LED[0]. At the last shift register, the serial data is output to the LED[35] pin and the SO pin at the
same time.
The strapping pin configuration of the RTL8231 in Shift Register Mode is shown in Table 15.
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Table 15. RTL8231 Shift Register Mode Strapping Pins Configuration
Pin Name
Pin
Type
LED[0]/Dis_SMI
15
I/OPD
SO/MOD[1]
16
I/O
LED[15]/MOD[0]
42
I/ OPU
Configuration
for Serial LED
Mode
Description
Select RTL8231 in the SMI mode or Shift Register mode.
0: SMI mode.(default)
1: Shift register mode
MOD[1:0] defines the parallel output initial value after
finish reset.
2b’00: LED[15] initial high, others parallel output initial
low.
2b’01: All parallel output initial high.
2b’10: LED[0] initial high, others parallel output initial
low.
2b’11: LED[15] initial low, others parallel output initial
high.
Pull high
Pull low
Pull high
8.19.3.2 Serial Shift LED, Per-Port Two Single-Color LEDs
T3=16ms
T2=1.674us
T1 = 108ns
T4 = (0.4~0.6) * T1
LED_CK
LED_DA
P7
P6
P5
P3
P2
P1
P0
P4
P7
P6
P5
P3
P2
P1
P0
P4
LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED1 LED1 LED1 LED1 LED1 LED1 LED1 LED1
P7
P5
P6
LED0 LED0 LED0
Figure 14. RTL8370NI-VB Serial Led Mode Shift Sequence (Per-Port Two Single-Color LEDs)
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8.19.3.3 Serial Shift LED, Per-Port One Single-Color LED
T3=16ms
T2=810ns
T1 = 108ns
T4 = (0.4~0.6) * T1
LED_CK
LED_DA
P7
P6
P5
P3
P2
P1
P0
P4
LED0 LED0 LED0 LED0 LED0 LED0 LED0 LED0
P7
P5
P6
LED0 LED0 LED0
Figure 15. RTL8370NI-VB Serial Led Mode Shift Sequence (Per-Port One Single-Color LED)
8.20. Green Ethernet
8.20.1.
Link-On and Cable Length Power Saving
The RTL8370NI-VB provides link-on and dynamic detection of cable length and dynamic adjustment of
power required for the detected cable length. This feature provides high performance with minimum
power consumption.
8.20.2.
Link-Down Power Saving
The RTL8370NI-VB implements link-down power saving on a per-port basis, greatly cutting power
consumption when the network cable is disconnected. After it detects an incoming signal, it wakes up
from link-down power saving and operates in normal mode.
8.21. IEEE 802.3az Energy Efficient Ethernet (EEE) Function
The RTL8370NI-VB support IEEE 802.3az Energy Efficient Ethernet ability for 1000Base-T, 100BaseTX in full duplex operation, and 10Base-T in full/half duplex mode.
The Energy Efficient Ethernet (EEE) optional operational mode combines the IEEE 802.3 Media Access
Control (MAC) sub-layer with 100Base-T and 1000Base-T Physical Layers defined to support operation
in Low Power Idle mode. When Low Power Idle mode is enabled, systems on both sides of the link can
disable portions of the functionality and save power during periods of low link utilization.
For 1000Base-T PHY: Supports Energy Efficient Ethernet with the optional function of Low Power
Idle
For 100Base-TX PHY: Supports Energy Efficient Ethernet with the optional function of Low Power
Idle
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The RTL8370NI-VB MAC uses Low Power Idle signaling to indicate to the PHY, and to the link partner,
that a break in the data stream is expected, and components may use this information to enter power
saving modes that require additional time to resume normal operation. Similarly, it informs the LPI Client
that the link partner has sent such an indication.
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Interface Descriptions
9.
9.1. I2C Master for EEPROM Auto-load
The EEPROM interface of the RTL8370NI-VB uses the serial bus I2C to read the Serial EEPROM.
When the RTL8370NI-VB is powered up, it drives SCK and SDA to read the configuration/code data
from the EEPROM by strapping configuration.
SCK
SDA
START
STOP
Figure 16. I2C Start and Stop Command
3.3V
NC-1.5K ohm
I2C Master
SCK
EERPOM
EEPROM_SCL
3.3V
1.5K ohm
SDA
EEPROM_SDA
4.7K ohm
STRP_DISAUTOLOAD
Figure 17. I2C Master for EEPROM Auto-load Interface Connection Example
The EEPROM can be divided into two sizes: 2Kb~16Kb and 32Kb~512Kb. The address of the small size
EEPROM is 8-bits, however the larger EEPROM has word-high addressing and word-low addressing,
and it is 16-bits (two bytes). The RTL8370NI-VB supports these two types EEPROM.
1 CONTROL BYTE
S
1
0
1
0
0
0
R/ A
0 W# C
(0) K
1 ADDRESS BYTE
The 1st DATA BYTE
1 CONTROL BYTE
A
C
K
ADDR[7:0]
S
1
0
1
0
0
R/ A
0 W# C
(1) K
0
MSB to LSB
ACK by
Slave(EEPROM)
N
O
A
C P
K
A
C
K
MSB to LSB
ACK by
Slave(EEPROM)
The 2nd DATA BYTE
MSB to LSB
ACK by
Slave(EEPROM)
ACK by Master
NOACK by Master
Figure 18. 8-Bit EEPROM Sequential Read
1 CONTROL BYTE
S
1
0
1
0
0
0
R/ A
0 W# C
(0) K
The 1st ADDRESS
BYTE (Word High
Addressing)
The 2nd ADDRESS
BYTE (Word Low
Addressing)
A
C
K
ADDR[15:8]
MSB to LSB
ACK by
Slave(EEPROM)
ADDR[7:0]
1 CONTROL BYTE
A
C
K
S
1
0
1
0
0
0
MSB to LSB
ACK by
Slave(EEPROM)
The 1st DATA BYTE
R/ A
0 W# C
(1) K
The 2nd DATA BYTE
A
C
K
MSB to LSB
ACK by
Slave(EEPROM)
ACK by
Slave(EEPROM)
N
O
A
C P
K
MSB to LSB
ACK by Master
NOACK by Master
Figure 19. 16-Bit EEPROM Sequential Read
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9.2. I2C-Like Slave Interface for External CPU to Access
RTL8370NI-VB
When EEPROM auto-load is completed, the RTL8370NI-VB registers can be accessed via SCK and
SDA (I2C-Like) via an external CPU (Decided by Strapping Configuration).
3.3V
1.5K ohm
I2C Slave
External CPU
S_SCK
M_SCL
3.3V
1.5K ohm
S_SDA
M_SDA
3.3V
4.7K ohm*
STRP_SMI_SEL_1
4.7K ohm*
STRP_SMI_SEL_0
Figure 20. I2C-Like Slave for External CPU Access Interface Connection Example
1 CONTROL BYTE
S
1
0
1
1
1
R/ A
0 W# C
(0) K
0
The 1st ADDRESS
BYTE (reg_addr[7:0])
The 2nd ADDRESS
BYTE (reg_addr[15:8])
A
C
K
ADDR[7:0]
MSB to LSB
ACK by Slave
The 2nd DATA BYTE
(write_data[15:8])
A
C
K
ADDR[15:8]
MSB to LSB
ACK by Slave
The 1st DATA BYTE
(write_data[7:0])
A
C
K
MSB to LSB
ACK by Slave
A
C P
K
MSB to LSB
ACK by Slave
ACK by Slave
Figure 21. I2C-Like Slave Interface Write Command
1 CONTROL BYTE
S
1
0
1
1
1
0
R/ A
0 W# C
(1) K
The 1st ADDRESS
BYTE (reg_addr[7:0])
ADDR[7:0]
MSB to LSB
ACK by Slave
The 2nd ADDRESS
BYTE (reg_addr[15:8])
A
C
K
ADDR[15:8]
MSB to LSB
ACK by Slave
ACK by Slave
The 1st DATA BYTE
(read_data[7:0])
A
C
K
The 2nd DATA BYTE
(read_data[15:8])
A
C
K
MSB to LSB
N
O
A
C P
K
MSB to LSB
ACK by Master
NOACK by Master
Figure 22. I2C-Like Slave Interface Read Command
Layer 2 Managed 8-port 10/100/1000 Switch Controller
41
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
9.3. Slave MII Management SMI Interface for External CPU to
Access RTL8370NI-VB
The RTL8370NI-VB registers can be accessed via Slave MDC and MDIO via an external CPU (Decided
by Strapping Configuration).
SMI Slave
External CPU
33 ohm
S_MDC
M_MDC
3.3V
1.5K ohm
S_MDIO
M_MDIO
3.3V
4.7K ohm
STRP_SMI_SEL_1
4.7K ohm
STRP_SMI_SEL_0
Figure 23. Slave MII Management SMI Interface Connection Example
Table 16. Slave MII Management SMI Access Format
Management Frame Fields
PRE
ST
OP
DEVAD
REGAD
TA
DATA
IDLE
1…1
01
10
AAAAA
RRRRR
Z0
DDDDDDDDDDDDDDDD
Z
Read
1…1
01
01
AAAAA
RRRRR
10
DDDDDDDDDDDDDDDD
Z
Write
Note: The Slave needs no less than 32bit Preambles (PRE) for accessing a slave via the Slave SMI interface default. An
External CPU can configure the Slave to enable preamble suppression function, and then the Slave does not need preamble
for accessing a slave.
9.4. SPI FLASH Interface
The RTL8370NI-VB supports a Serial IO and Dual IO mode SPI Interface to connect SPI FLASH. The
RTL8370NI-VB only supports 3-byte address mode access. 4Mbyte capacity of SPI FLASH is ideal for
RTL8370NI-VB application.
Controller
SPI FLASH
SPI_F_CLK
CLK
NC-4.7K ohm
nSPI_F_CS
3.3V
/CS
SPI_F_D1
DO(IO1)
SPI_F_D0
DI(IO0)
Figure 24. SPI FLASH Interface Connection Example
Layer 2 Managed 8-port 10/100/1000 Switch Controller
42
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
10.
Electrical Characteristics
10.1. Absolute Maximum Ratings
WARNING: Absolute Maximum Ratings are limits beyond which Electrical Overstress (EOS) damage
can occur. Permanent damage may be caused to the device, or device reliability can be affected.
All voltages are specified reference to GND unless otherwise specified.
Table 17. Absolute Maximum Ratings
Parameter
Min
Junction Temperature (Tj)
Storage Temperature
-45
DVDDIO_2, DVDDIO_0, DVDDIO_1, AVDDH, Supply
GND-0.3
Referenced to GND and AGND
DVDDL, AVDDL, PLLVDDL0, PLLVDDL1 Supply Referenced
GND-0.3
to GND, AGND, PLLGND0, and PLLGND1
Digital Input Voltage
GND-0.3
Max
+125
+125
Units
C
C
+3.63
V
+1.21
V
VDDIO+0.3
V
10.2. Recommended Operating Range
Table 18. Recommended Operating Range
Parameter
Min
Typical
Ambient Operating Temperature (Ta)
-40
DVDDIO, AVDDH Supply Voltage Range
3.135
3.3
DVDDL, AVDDL, PLLVDDL0, PLLVDDL1 Supply Voltage
1.045
1.1
Range
Layer 2 Managed 8-port 10/100/1000 Switch Controller
43
Max
85
3.465
Units
C
V
1.155
V
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
10.3. Thermal Characteristics
10.3.1.
LQFP-128-EPAD
10.3.1.1 Assembly Description
Package
PCB
Table 19. Assembly Description
Type
E-Pad LQFP128
Dimension (L x W)
14 x 20 mm
Thickness
1.4 mm
PCB Dimension (L x W)
130 x 75mm
PCB Thickness
1.6 mm
2-Layer:
- Top layer (1oz): 20% coverage of Cu
- Bottom layer (1oz): 75% coverage of Cu
4-Layer:
Number of Cu Layer-PCB
- 1st layer (1oz): 20% coverage of Cu
- 2nd layer (1oz): 80% coverage of Cu
- 3rd layer (1oz): 80% coverage of Cu
- 4th layer (1oz): 75% coverage of Cu
10.3.1.2 Material Properties
Item
Package
Die
Silver Paste
Lead Frame
Mold Compound
PCB
Table 20. Material Properties
Material
Thermal Conductivity K (W/m-k)
Si
147
1033BF
2.5
CDA7025
168
7372
0.88
Cu
400
FR4
0.2
10.3.1.3 Simulation Conditions
Table 21. Simulation Conditions
2.6W
2L (2S)/4L (2S2P)
Air Flow = 0, 1, 2 m/s
Input Power
Test Board (PCB)
Control Condition
Layer 2 Managed 8-port 10/100/1000 Switch Controller
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Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
10.3.1.4 Thermal Performance of E-Pad LQFP-128 on PCB under Still Air Convection
Table 22. Thermal Performance of E-Pad LQFP-128 on PCB under Still Air Convection
θJA
θJB
θJC
ΨJT
ΨJB
4L PCB
18.2
8.2
7.5
2.5
8.8
2L PCB
30.1
10.0
8.9
3.4
11
Note:
θJA: Junction to ambient thermal resistance
θJB: Junction to board thermal resistance
θJC: Junction to case thermal resistance
ΨJT: Junction to top center of package thermal characterization
ΨJB: Junction to bottom surface center of PCB thermal characterization
10.3.1.5 Thermal Performance of E-Pad LQFP-128 on PCB under Forced Convection
Table 23. Thermal Performance of E-Pad LQFP-128 on PCB under Forced Convection
Air Flow (m/s)
0
1
2
θJA
18.2
15.2
14.2
4L PCB
ΨJT
2.5
2.8
3.5
ΨJB
8.8
8.6
8.3
θJA
30.1
25.9
24.2
2L PCB
ΨJT
3.4
4.5
5.6
ΨJB
11
10.7
10.5
10.4. DC Characteristics
Table 24. DC Characteristics
SYM
Min
Typical
Max
System Idle (No UTP Port Link Up, 1 System Power LED)
Power Supply Current for VDDH
IDVDDIO, IAVDDH
41
Power Supply Current for VDDL
IDVDDL, IAVDDL,
165
IPLLVDDL
Total Power Consumption for All Ports
PS
316.8
1000M Active (8 UTP Ports Link Up, 1 System Power LED, 8 Activity LEDs, 8 Speed LEDs)
Power Supply Current for VDDH
IDVDDIO, IAVDDH
530
Power Supply Current for VDDL
IDVDDL, IAVDDL,
881
IPLLVDDL
Total Power Consumption for All Ports
PS
2718.1
100M Active (8 UTP Ports Link Up, 1 System Power LED, 8 Activity LEDs, 8 Speed LEDs)
Power Supply Current for VDDH
IDVDDIO, IAVDDH
201
Power Supply Current for VDDL
IDVDDL, IAVDDL,
282
IPLLVDDL
Total Power Consumption for All Ports
PS
973.5
10M Active (8 UTP Ports Link Up, 1 System Power LED, 8 Activity LEDs)
Power Supply Current for VDDH
IDVDDIO, IAVDDH
242
Parameter
Layer 2 Managed 8-port 10/100/1000 Switch Controller
45
Units
mA
mA
mW
mA
mA
mW
mA
mA
mW
mA
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
Parameter
Power Supply Current for VDDL
SYM
Min
IDVDDL, IAVDDL,
IPLLVDDL
Total Power Consumption for All Ports
PS
VDDIO=3.3V
TTL Input High Voltage
Vih
1.9
TTL Input Low Voltage
Vil
Output High Voltage
Voh
2.7
Output Low Voltage
Vol
Output Low Voltage
Vol
Note: DVDDIO=3.3V, AVDDH=3.3V, DVDDL=1.1V, AVDDL=1.1V PLLVDDL=1.1V.
Typical
200
Max
-
Units
mA
1020
-
mW
-
0.7
0.6
0.4
V
V
V
V
V
10.5. AC Characteristics
10.5.1.
I2C Master for EEPROM Auto-Load Timing Characteristics
Tsck
t1
t2
SCK
t3 t4
SDA
t5 t6
t7
Data Output
Data Output
Data Input
t8
Data Input
t11
Figure 25. I2C Master for EEPROM Auto-Load Timing Characteristics
t9
nRESET
SCK
SDA
Figure 26. I2C Master for EEPROM Auto-Load Power on Timing
Layer 2 Managed 8-port 10/100/1000 Switch Controller
46
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
t10
SCK
SDA
Data Valid
Start
Condition
Stop
Condition
Figure 27. I2C Master for EEPROM Auto-Load Timing
Table 25. I2C Master for EEPROM Auto-Load Timing Characteristics
Symbol
Description
Type
Min
Typical
Max
Tsck
SCK Clock Period
O
9
t1
SCK High Time
O
4.05
4.5
t2
SCK Low Time
O
4.05
4.5
t3
START Condition Setup Time
O
2
t4
START Condition Hold Time
O
2
t5
Data Input Hold Time
I
0
t6
Data Input Setup Time
I
10
t7
Data output delay
O
2.15
2.35
t8
STOP Condition Setup Time
O
2
t9
SCK/SDA Active from Reset Ready
O
76.8
t10
8K-bits EEPROM Auto-Load Time
O
236
t11
Time the bus is free before new START
O
10
SCK Rise Time (10% to 90%)
O
100
SCK Fall Time (90% to 10%)
O
100
Duty Cycle
O
40
50
60
Note: t9, and t10 are measured with the ATMEL AT24C08 EEPROM.
Layer 2 Managed 8-port 10/100/1000 Switch Controller
47
Units
µs
µs
µs
µs
µs
ns
ns
µs
µs
ms
ms
µs
ns
ns
%
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
10.5.2.
I2C-Like Slave Mode for External CPU Access Interface Timing
Characteristics
t1
t2
SCK
t3
SDA
t4
t5
Data Input
t6
t7
Data Input
t8
t9
Data Output
Figure 28. I2C-Like Slave Mode for External CPU Access Interface Timing Characteristics
Table 26. I2C-Like Slave for External CPU Access Interface Timing Characteristics
Symbol
Description
Type
Min
Typical
Max
t1
SCK High Time
I
4.0
t2
SCK Low Time
I
4.0
t3
START Condition Setup Time
I
0.25
t4
START Condition Hold Time
I
0.25
t5
Data Input Hold Time
I
0
t6
Data Input Setup Time
I
100
t7
Clock to Data Output Delay
O
10
100
t8
STOP Condition Setup Time
I
0.25
t9
Time the bus is free before new START
I
0.5
-
Layer 2 Managed 8-port 10/100/1000 Switch Controller
48
Units
µs
µs
µs
µs
µs
ns
ns
µs
µs
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
10.5.3.
Slave MII Management SMI for External CPU Access Interface
Timing Characteristics
The RTL8370NI-VB supports MDIO slave mode. The Master (the RTL8370NI-VB link partner CPU)
can access the Slave (RTL8370NI-VB) registers via the MDIO interface. The MDIO is a bi-directional
signal that can be sourced by the Master or the Slave. In a write command, the Master sources the MDIO
signal. In a read command, the Slave sources the MDIO signal.
The timing characteristics of the Master (the RTL8370NI-VB link partner CPU) are provided by the
Master when the Master sources the MDIO signal (Write command)
The timing characteristics of the Slave (RTL8370NI-VB) are provided by the RTL8370NI-VB when
the RTL8370NI-VB sources the MDIO signal (Read command)
t1
VIH
MDC
VIL
VIH
MDIO
VIL
t2
t3
Figure 29. MDIO Sourced by Master (External CPU)
VIH
MDC
VIL
VIH
MDIO
VIL
t4
Figure 30. MDIO Sourced by Slave (RTL8370NI-VB)
Table 27. Slave SMI (MDC/MDIO) Timing Characteristics and Requirements
Parameter
SYM Description/Condition
Type Min Typical
MDC Clock Period
t1
Clock Period
I
125
MDIO to MDC Rising Setup
t2
Input Setup Time
I
8
Time (Write Data)
MDIO to MDC Rising Hold
t3
Input Hold Time
I
8
Time (Write Data)
MDC to MDIO Delay Time
t4
Clock (Rising Edge) to Data Delay
O
0
(Read Data)
Time
Layer 2 Managed 8-port 10/100/1000 Switch Controller
49
Max
-
Units
ns
-
ns
-
ns
80
ns
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
10.5.4.
Serial Shift Mode LED Interface Timing Characteristics
Tcyc
LED_CK
tsetup:O
LED_DA
thold:O
V ih(max)
V ih( min)
Vih(max)
Vih(min)
Data Output
Figure 31. Serial Shift Mode LED Timing Characteristics
Table 28. Serial Shift Mode LED AC Timing
Mode and Description
Symbol
Min
Input High Voltage
Vih
2.0
Input Low Voltage
Vil
Serial LED_CK Clock Cycle
Tcyc
Shift
Duty
Cycle
of
the
LED_CK
Duty
45
LED
LED_DA to LED_CK Output Setup Time
tsetup:O
40
LED_DA to LED_CK Output Hold Time
thold:O
20
Layer 2 Managed 8-port 10/100/1000 Switch Controller
50
Typical
108
50
-
Max
0.8
55
-
Units
V
V
ns
%
ns
ns
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
10.5.5.
SPI FLASH Interface Timing Characteristics
tSLCH
tCHSH
SPI_CS#
SPI_SCK
tsetup:O thold:O
SPI_SI (Output)
tsetup:I
thold:I
MSB
High-Z
Data In
SPI_SO (Input)
Figure 32. SPI FLASH Timing Characteristics
Table 29. SPI FLASH AC Timing
Symbol Description
Type
Min
fSPI_SCK Clock Frequency of the SPI_SCK
O
Duty
Duty Cycle of the SPI_SCK
O
45
tSLCH
CS# Active Setup Time
O
6
tCHSH
CS# Active Hold Time
O
6
tsetup:O
Data Output Setup Time
O
5
thold:O
Data Output Hold Time
O
6
tsetup:I
Data Input Setup Time
I
2
thold:I
Data Input Hold Time
I
0
Test Condition: FSPI_SCK=62.5MHz
Layer 2 Managed 8-port 10/100/1000 Switch Controller
51
Typical
62.5
50
-
Max
55
-
Units
MHz
%
ns
ns
ns
ns
ns
ns
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
10.6. Power and Reset Characteristics
t1
t3
DVDDL
AVDDL
PLLVDDL0
PLLVDDL1
DVDDIO
AVDDH
t2
t4
nRESET
Figure 33. Power and Reset Characteristics
Parameter
Reset Delay Time
Reset Low Time
VDDL Power Rising Settling
Time
VDDH Power Rising
Settling Time
Table 30. Power and Reset Characteristics
SYM Description/Condition
Type
t1
The duration from all powers steady to
I
the reset signal released to high.
t2
The duration of reset signal remain low
time for issuing a reset to the
I
RTL8370NI-VB.
t3
DVDDL, AVDDL, PLLVDDL0 and
I
PLLVDDL1 power rising settling time.
t4
DVDDIO and AVDDH power rising
I
settling time.
Layer 2 Managed 8-port 10/100/1000 Switch Controller
52
Min
Typical
Max
Units
10
-
-
ms
10
-
-
ms
0.5
-
100
ms
0.5
-
100
ms
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
11.
Mechanical Dimensions
11.1. RTL8370NI-VB: LQFP 128-Pin E-PAD Package
Thermally Enhanced Low-profile Quad Flat Package (LQFP) 128 Leads 14x20mm Outline.
Symbol
Dimension in mm
Nom
Max
A
1.60
A1
0.15
A2
1.40
1.45
b
0.2
0.27
D
22.00BSC
D1
20.00BSC
D2/E 2
5.60
6.60
7.50
E
16.00BSC
E1
14.00BSC
e
0.50BSC
L
0.45
0.60
0.75
L1
1.00REF
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MS-26.
Min
0.05
1.35
0.17
Layer 2 Managed 8-port 10/100/1000 Switch Controller
53
Min
0.002
0.053
0.007
0.220
0.018
Dimension in inch
Nom
0.055
0.009
0.866BSC
0.787BSC
0.260
0.630BSC
0.551BSC
0.020BSC
0.024
0.039REF
Max
0.063
0.006
0.057
0.011
0.295
0.030
Track ID: JATR-XXXX-XX Rev. 0.1
RTL8370NI-VB
Draft Datasheet
12.
Ordering Information
Table 31. Ordering Information
Part Number
Package
RTL8370NI-VB-CG
LQFP 128-Pin E-PAD ‘Green’ Package
Note: See page 7 for package identification information.
Status
-
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com
Layer 2 Managed 8-port 10/100/1000 Switch Controller
54
Track ID: JATR-XXXX-XX Rev. 0.1
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