CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
Shanghai Chipanalog Microelectronics Co., Ltd.
CA-IS398x Isolated Octal Industrial Digital Input
1.
Features
•
Accepts Industry Standard Input Types
Compliant to IEC 61131-2 Input Types 1, 2, and 3
High Integration
Eight input channels with serializer (CA-IS3980S)
Eight input channels with parallel-output s (CAIS398xP)
Support up to 2Mbps Data Rates
Integrated Digital Glitch and Debounce Filters with 0
to 100ms Selectable Delay Time
High transient immunity:
±300kV/µs CMTI for the low-speed channels
±50kV/µs CMTI for the high-speed channels
2500VRMS Integrated Isolation Reduces BOM and
Footprint
SPI-Compatible Serial Interface (CA-IS3980S only)
2.25V to 5.5V Single Supply , Eliminates the Need For
Field-side Power Supply
-40°C to 125°C Ambient Operating Temperature
8.66mm x 3.91mm 20-pin SSOP Package
Safety Regulatory Approvals (pending)
DIN VVDE V 0884-10 Basic isolation
UL1577 certification, 2500 VRMS insulation
CSA according to GB4943.1-2011 certification
TUV according to EN61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A2:2013 certifications
•
•
•
•
•
•
•
•
•
•
2.
Applications
•
•
•
•
•
Digital Input Modules for PLCs
Industrial, Building, and Process Automation
Motor Control
CNC Control
Industrial data acquisition
feature up to 2.5kVRMS isolation rating and ±300kV/μs
typical CMTI (low-speed channels), provide high
electromagnetic immunity, low propagation delay and low
jitter.
The CA-IS398x devices operate over the supply range of
2.25V to 5.5V on logic side, no power supply required on
field side. The logic output level is set by supply voltage
independently, easy to connect with 2.5V, 3.3V and 5V
controller interface. The CA-IS3980S industrial interface
serializer translates, conditions and serializes the eight 24V
digital inputs to CMOS-compatible signals through the SPI
port required by microcontrollers; While the CA-IS398xP
devices translate eight 24V industrial digital inputs to eight
CMOS-compatible parallel outputs. All devices provide
isolated digital outputs and all digital inputs can be
current-sinking or current sourcing industrial inputs
(bidirectional inputs) from sensors and switches used in
industrial, process, and building automation. For robust
operation in industrial environments, each input of the CAIS398x with parallel outputs includes a glitch and
debounce filters with fixed delay time; The CA-IS3980S
features programmable debounce filters, allow flexible
debouncing and filtering of sensor outputs based on the
application. Also, for systems with more than eight sensor
inputs, CA-IS3980S is capable of daisy-chaining multiple
devices and have up to 128 inputs sharing the same
isolated SPI interface. A simplified block diagram for the
CA-IS398x is shown in the figure below.
The CA-IS398x family of devices are specified over -40°C to
+125°C operating temperature range and are available in
20-pin SSOP package. Also see the Ordering Information
for suffixes associated output interface and filter delay
time configuration options.
Device information
Part number
3.
General Description
The CA-IS398x family of isolated octal digital inputs are
optimized for industrial 24V digital input applications. All
devices can be configured for Type 1, Type 2, or Type 3
inputs with a few external components and each channel
can sink and source current. The isolation channels based
on Chipanalog’s advanced capacitive isolation technology
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
CA-IS3980
CA-IS3988
Package
Package size (NOM)
SSOP20(Y)
8.66mm x 3.91mm
1
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
Shanghai Chipanalog Microelectronics Co., Ltd.
Simplified Block Diagram
CA-IS3980P
4.
2
2
A3
3
A4
4
COM
5
COM
6
A5
7
A6
8
A7
9
A8
10
e
20
e
19
e
18
e
17
16
15
B1
A1
1
e
20
MISO
B2
A2
2
e
19
MOSI
B3
A3
3
e
18
NSS
B4
A4
4
e
17
SCLK
VDD
COM
5
16
VDD
GND
COM
6
15
GND
B5
A5
7
e
14
MOSI_THRU
Isolation Barrier
1
A2
Isolation Barrier
A1
CA-IS3980S
SPI
e
14
e
13
B6
A6
8
e
13
NC
e
12
B7
A7
9
e
12
NC
e
11
B8
A8
10
e
11
NC
Ordering Information
Part Number
Output
Interface
Number of Highspeed Channels
Low-pass Filter Debounce Time
Package
Isolation Rating
(kVRMS)
CA-IS3980S
Serial
0
0ms/10ms/30ms/100ms
SSOP20
2.5kVRMS
CA-IS3980P
Parallel
0
0ms
SSOP20
2.5kVRMS
CA-IS3988P
Parallel
8
0ms
SSOP20
2.5kVRMS
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
Shanghai Chipanalog Microelectronics Co., Ltd.
1.
2.
3.
4.
5.
6.
7.
5.
CA-IS3980, CA-IS3988
Contents
Features .............................................................1
Applications ........................................................1
General Description ............................................1
Ordering Information ..........................................2
Revision History ..................................................3
Pin Configuration and Description .......................4
Specifications......................................................5
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
Version 1.05, 2023/05/22
Absolute Maximum Ratings1 ...............................5
ESD Ratings..........................................................5
Recommended Operating Conditions .................5
Thermal Information ...........................................5
Power Rating .......................................................5
Insulation Specifications .....................................6
Safety-Related Certifications ...............................7
Safety Limits1 .......................................................7
Electrical Characteristics .....................................8
Timing Characteristics .........................................9
Typical Operating Characteristics ......................10
8.
9.
Parameter Measurement Information ............... 11
Detailed Description .........................................12
9.1.
9.2.
9.3.
9.4.
10.
11.
12.
13.
14.
Overview ........................................................... 12
Device Operation Modes .................................. 12
Input Filters ....................................................... 13
9.3.1.
Debounce filter selection and delay
configuration .................................................................... 13
9.3.2.
Debounce filter operation modes .................... 13
SPI Interface (CA-IS3980S) ................................ 15
9.4.1.
9.4.2.
9.4.3.
Register Map and Description .......................... 15
SPI Protocol ...................................................... 15
SPI Daisy-Chaining ............................................ 17
Application and Implementation ................ 18
Package Information ..................................21
Soldering Temperature (reflow) Profile ....... 22
Tape and Reel Information ......................... 23
Important statement ..................................24
Revision History
Revision Number
Version 1.00
Version 1.01
Version 1.02
Version 1.03
Version 1.04
Version 1.05
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
Description
N/A
N/A
Updated “ESD Ratings” table, HBM ESD protection changed to ±5000V,
CDM ESD protection changed to ±2000V.
Change POD and Type reel information
Removed part number CA-IS3982x,CA-IS3984x
Updated SPI sync information
Updated VDD UVLO information
Page Changed
N/A
N/A
Page 6
22,24
NA
24
8
3
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
6. Pin Configuration and Description
Shanghai Chipanalog Microelectronics Co., Ltd.
CA-IS3980P / CA-IS3988P
CA-IS3980S
e
20
B1/BH1
A1
1
e
20
MISO
A2/AH2
2
e
19
B2/BH2
A2
2
e
19
MOSI
A3/AH3
3
e
18
B3/BH3
A3
3
e
18
NSS
A4/AH4
4
e
17
B4/BH4
A4
4
e
17
SCLK
COM
5
16
VDD
COM
5
16
VDD
COM
6
15
GND
COM
6
15
GND
A5/AH5
7
e
14
B5/BH5
A5
7
e
14
MOSI_THRU
A6/AH6
8
e
13
B6/BH6
A6
8
e
13
NC
A7/AH7
9
e
12
B7/BH7
A7
9
e
12
NC
A8/AH8
10
e
11
B8/BH8
A8
10
e
11
NC
Isolation Barrier
1
Isolation Barrier
A1/AH1
SPI
Figure 6-1. CA-IS398x Pin Configuration
Table 6-1. CA-IS3980P/CA-IS3982P/CA-IS3984P/CA-IS3988P pin description
CA-IS3980P
1,2,3,4,7,8,9,10
---
Pin Number
CA-IS3988P
--1,2,3,4,7,8,9,10
Pin Name
Type
Description
A1-A8
AH1-AH8
Input
Input
Field input, low-speed channels.
Field input, high-speed channels.
Common, can be connected to ground for
sinking inputs or the field supply for sourcing
inputs.
Logic Outputs, low-speed channels. Indicate
the state (high or low) of A1-A8. If the input
is open, output is Low.
Logic Outputs, high-speed channels. Indicate
the state (high or low) of AH1-AH8. If the
input is open, output is high-impedance.
2.25V to 5.5V logic supply input.
Ground reference for logic side.
5, 6
5, 6
COM
COM
11,12,13,14,
17,18,19,20
---
B1-B8
Output
---
11,12,13,14,
17,18,19,20
BH1-BH8
Output
16
15
16
15
VDD
GND
Power
GND
Table 6-2. CA-IS3980S pin description
Pin Number
CA-IS3980S
1,2,3,4,7,8,9,10
4
Pin Name
Type
A1-A8
Input
5, 6
COM
COM
11, 12, 13
16
15
19
17
18
14
20
NC
VDD
GND
MOSI
SCLK
NSS
MOSI_THRU
MISO
No Connect
Power
GND
Input
Input
Input
Output
Output
Description
Field input, low-speed channels.
Common, can be connected to ground for sinking inputs or the field
supply for sourcing inputs.
Not internally connected.
2.25V to 5.5V logic supply input.
Ground reference for logic side.
SPI serial data input.
SPI serial clock input.
SPI chip-select input.
SPI serial data out for cascading multiple devices (up to 16).
SPI serial data output.
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
Shanghai Chipanalog Microelectronics Co., Ltd.
7. Specifications
7.1.
Absolute Maximum Ratings1
Parameters
Minimum value
Maximum value
Unit
VDD
Power supply voltage
-0.3
6.0
V
IF(AVG)
Ax/AHx Average Input Current
30
mA
VF(AVG)
Ax/AHx Aerage Input Voltage @ 30mA Input Current
2.5
V
VO
Bx/BHx, MISO Output Voltage
-0.5
VDD+0.5
V
IO
Bx/BHx Output Current
-10
10
mA
VI
MOSI、NSS、SCLK Input
-0.5
VDD+0.5
V
TJ
Junction temperature
150
°C
TSTG
Storage temperature range
-65
150
°C
Note:
1.
The stresses listed under “Absolute Maximum Ratings” are stress ratings only, not for functional operation condition. Exposure to absolute
maximum rating conditions for extended periods may cause permanent damage to the device.
7.2.
ESD Ratings
VESD Electrostatic discharge
Value
±5000
±2000
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
Charged device model (CDM), per JEDEC Specification JESD22-C101, all pins
1
Unit
V
V
Note:
1. Per JEDEC document JEP155, 500V HBM allows safe manufacturing of standard ESD control process.
7.3.
Recommended Operating Conditions
Parameters
Power supply voltage
Maximum data rate1, high-speed channel
Minimum data rate2, high-speed channel
Maximum data rate, low-speed channel (+0ms tD)
Minimum data rate, low-speed channel (+0ms tD)
Maximum data rate, low-speed channel (+10ms tD)
Maximum data rate, low-speed channel (+30ms tD)
Maximum data rate, low-speed channel (+100ms tD)
Input start-up current (sinking or sourcing inputs)
Ambient Temperature3
VDD
DR
Min
2.3
Typ
Max
5.5
2
10
250
1
100
33
10
20
125
Unit
V
Mbps
kbps
kbps
kbps
bps
bps
bps
mA
°C
IF(ON)
1.0
TA
-40
Notes:
1. The maximum data rate corresponds to the input signals with 50% duty cycle. If the duty cycle of the input signal is greater than or less
than 50%, the maximum data rate will decrease;
2. If the data rate is too low and the rising / falling edge of the input signal is slow, the output signals may have glitches;
3. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage.
7.4.
Thermal Information
Thermal Metric
RθJA
7.5.
Junction-to-ambient thermal resistance
Unit
105
°C/W
Maximum value
540
Unit
mW
Power Rating
Parameters
Maximum Power Dissipation on input side
PD
20-pin SSOP
Maximum Power Dissipation on output side
Maximum Power Dissipation
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
Test conditions
input current = 30mA/channel, TJ=150°C
VDD=5.5V, CL=15pF, 1MHz 50% duty cycle input,
TJ=150°C
VDD=5.5V, input current = 30mA/channel, TJ=150°C
450
mW
990
mW
5
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
7.6. Insulation Specifications
Parameters
Clearance1
CLR
External
CPG
External Creepage1
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Overvoltage category per IEC 60664-1
DIN V VDE V 0884-11:2017-01
VIORM
Maximum repetitive peak isolation voltage
VIOWM
Maximum operating isolation voltage
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage 2
qpd
Apparent charge 3
CIO
Barrier capacitance, input to output 4
RIO
Isolation resistance 4
Shanghai Chipanalog Microelectronics Co., Ltd.
Test conditions
Shortest terminal-to-terminal distance through air
Shortest terminal-to-terminal distance across the
package surface
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11)；IEC 60112
Per IEC 60664-1
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
AC voltage (bipolar)
AC voltage; time-dependent dielectric breakdown
(TDDB) test
DC voltage
VTEST = VIOTM,
t=60 s (certified);
VTEST = 1.2 × VIOTM,
t=1 s (100% product test)
Test method per IEC 60065, 1.2/50 μs waveform,
VTEST = 1.6 × VIOSM (production test)
Method a, after input/output safety test of the subgroup
2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental test of the subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
Method b, at routine test (100% production test) and
preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
VIO = 0.4 × sin (2πft), f = 1MHz
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Pollution degree
UL 1577
VISO
Maximum withstanding isolation voltage
VTEST = VISO, t = 60 s (qualification)
VTEST = 1.2 × VISO, t = 1 s (100% production test)
Value
SSOP
3.6 (minimum)
UNIT
mm
3.6 (minimum)
mm
8
600
I
I-IV
I- III
μm
V
560
VPK
400
VRMS
566
VDC
3600
VPK
4000
VPK
≤5
≤5
pC
≤5
pF
>1012
>1011
>109
2
2500
Ω
VRMS
Notes:
1.
This coupler is suitable for “safe electrical insulation” only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
2.
Devices are immersed in oil during surge characterization test.
3.
The characterization charge is discharging charge (pd) caused by partial discharge.
4.
Capacitance and resistance are measured with all pins on field-side and logic-side tied together.
6
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
Shanghai Chipanalog Microelectronics Co., Ltd.
7.7. Safety-Related Certifications
VDE (pending)
Certified according to DIN VDE V 0884-11:2017-01.
Certification NO.:Pending
7.8.
Safety Limits1
Parameters
IS
UL
Certified according to UL 1577 Component Recognition Program.
Certification NO.: E511334-20220727
Safety input/output current on
logic side
Test conditions
RθJA = 120 °C/W, VI = 2.75V, TJ = 150°C,
TA=25°C.
RθJA = 120 °C/W, VI = 3.6V, TJ = 150°C,
TA=25°C.
RθJA = 120 °C/W, VI = 5.5V, TJ = 150°C,
TA=25°C.
RθJA = 120 °C/W, TJ = 150°C, TA=25°C.
RθJA = 120 °C/W, TJ = 150°C, TA=25°C.
Min.
Typ.
Max.
80
100
Unit
mA
240
IS
Safety input current on filed side
240
mA
PS
Total safety power dissipation
1200
mW
Maximum safety temperature
150
TS
°C
Note:
1.
Damage to the IC can result in a low-resistance path to ground or to the supply and, without current limiting, the CA-IS398x could dissipate
an excessive amount of power. Excessive power dissipation can damage the die and result in damage to the isolation barrier, potentially
causing downstream issues. This table shows the safety limits for the CA-IS398x.
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
7
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
7.9. Electrical Characteristics
TA = -40 to 125°C, over recommended operating conditions, unless otherwise specified.
Parameters
Test conditions
Filed-side Inputs
IF(TH)
Input current threshold
IHYS
Input current hysteresis
VF(TH)
Field input threshold
VHYS
Input voltage hysteresis
CI
Input capacitance
f=125kHz
Logic-side Supply
VULVO+
VDD undervoltage threshold
VDD rising
VUVLOVDD undervoltage threshold
VDD falling
VHYS(UVLO)
UVLO hysteresis
All inputs = “0”
All inputs = “1”
60kHz, all inputs switching with 50%
IDD
Operating current
duty cycle.
1MHz, all inputs switching with 50%
duty cycle.
Logic-side Inputs
VIL
Input logic-low voltage
SCLK，NSS，MOSI
VIH
Input logic-high voltage
SCLK，NSS，MOSI
VOL
Output logic-low voltage
IOL = 4 mA
VOH
Output logic-high voltage
IOH = -4 mA
IIH
Input leakage current at logic-low
SCLK，NSS，MOSI
IIL
Input leakage current at logic-high
SCLK，NSS，MOSI
8
Shanghai Chipanalog Microelectronics Co., Ltd.
Min.
Typ.
Max.
Unit
460
30
1.0
30
606
76
1.38
73
105
950
200
1.7
130
μA
μA
V
mV
pF
1.85
1.74
2.06
1.92
0.14
4.7
4.6
4.7
2.24
2.10
4.7
7.7
7.7
7.6
7.7
0.8
2.0
0.4
VDD-0.4
-1
-1
1
1
V
mA
V
V
V
V
μA
μA
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
Shanghai Chipanalog Microelectronics Co., Ltd.
7.10. Timing Characteristics
TA = -40 to 125°C, over recommended operating conditions, unless otherwise specified.
Parameters
Test conditions
Signal Channels
Input current rise/fall time=10ns, input
current=10mA, high-speed channels AHx
Input current rise/fall time=10ns, input
current=10mA, low-speed channel Ax (+0ms tD)
Input current rise/fall time=10ns, input
tP
Propagation delay time
current=10mA, low-speed channel Ax (+10ms tD)
Input current rise/fall time=10ns, input
current=10mA, low-speed channel Ax (+30ms tD)
Input current rise/fall time=10ns, input
current=10mA, low-speed channel Ax (+100ms
tD)
AHx high-speed channel
PWD
Pulse width distortion
Ax channel
AHx high-speed channel
Tpsk( P-P)
Propagation delay skew
Part-to-part
Ax channel
AHx high-speed channel
Tpsk
Propagation delay skew
Channel-to-channel
Ax channel
tr, tf
Output rise and fall times
CL=15pF
tSTART
Start-up time
AHx high-speed channel
Common mode transient
CMTI
immunity
Ax channel
SPI Interface
SCLK Clock period
tC
Delay time
SCLK falling to MISO valid
tDO1
Delay time
tDO2
SCLK falling to MISO transition
Delay time
NSS rising to MISO high-Z
tDZ
Setup time
tSU1
Falling edge of NSS to falling edge of SCLK
Hold time
tH1
Rising edge of SCLK to rising edge of NSS
Setup
time
tSU2
MOSI to SCLK rising
Hold time
tH2
SCLK rising to MOSI transition
Delay time
tNSS
NSS delay time
Delay time
tDTHRU
MOSI to MOSI_THRU delay time
Min.
Typ.
Max.
Unit
36
120
ns
5.6
6.7
μs
10
ms
30
ms
100
ms
6
450
-30
-250
-30
-250
25
200
50
ns
ns
ns
ns
ns
ns
ns
μs
kV/μs
kV/μs
+30
+250
+30
+250
3.3
46
50
300
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
25
20
25
20
200
15
tC
SCLK
NSS
tH1
tSU1
tSU2
MOSI
Rx Bit
tNSS
tH2
Rx Bit
Rx Bit
Rx Bit
tDTHRU
MOSI_THRU
Rx Bit
Rx Bit
MISO
Tx Bit
tDO1
Tx Bit
Rx Bit
Tx Bit
Rx Bit
Tx Bit
tDO2
Figure 7-1. SPI Timing Diagram
Note: The timing specifications depicted in this figure apply to each byte of the three byte CA-IS3980S SPI communications packet.
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
9
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
7.11. Typical Operating Characteristics
Shanghai Chipanalog Microelectronics Co., Ltd.
Input Voltage(V)
VI Curve
3.0
2.5
2.0
1.5
TA=125℃
TA=25℃
1.0
TA=-40℃
0.5
0.0
0
5
10
15
20
Input Current(mA)
Figure 7-2. Input Voltage vs. Input Current Over Temperature
Note:
1. Input current and input voltages are absolute values and apply to both sourcing and sinking channel designs.
10
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
Shanghai Chipanalog Microelectronics Co., Ltd.
8. Parameter Measurement Information
CA-IS398x
IIN
Current input
with 50% duty
circle
Ax /AHx
VDD
Bx /BHx
IHYS
tP
VOUT
tP
90%
CL=15pF
COM
IF(TH)
IIN
VOUT
50%
GND
10%
tr
tf
Figure 8-1. Switching Characteristics Test Circuit and Waveform
CA-IS398x
VDD
Input signal
switch
High
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Ax /AHx
Low
Bx /BHx
2.2nF
COM
GND
High Voltage Surge Generator
Figure 8-2. Common-Mode Transient Immunity Test Circuit
11
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
9. Detailed Description
9.1.
Shanghai Chipanalog Microelectronics Co., Ltd.
Overview
The CA-IS398x family of devices is isolated octal digital inputs optimized for industrial 24V digital input applications. These
devices are suitable for high-channel density, digital-input modules for programmable logic controllers and motor control
digital input modules. The CA-IS398x devices provide compliance with IEC 61131-2 Types 1, 2, 3 inputs with a few external
components and can be used to create a bidirectional input module that can sink and source current, see Figure 9-1 the
simplified block diagram for a single CA-IS398x channel. There is a diode bridge and an LED emulator at the front end of each
input channel, see Figure 7-2 Input Voltage vs. Input Current curve to find more details about input operating characteristics.
The internal LED emulator output drives an ON-OFF keying (OOK) modulator, to transfer digital signals across the SiO2 based
isolation barrier between circuits with different power domains. In many applications, this capacitive isolation technology is
replacing optocoupler-based solution because it can reduce the power requirements and take up less board space while
offering the same isolation capability.
Ax/AHx
OOK
Modulator
OOK
Modulator
Jitter
Filter
B
BH
Bx/BHx
COM
Figure 9-1. Simplified block diagram of a single CA-IS398x channel
On the output side, the signal is either passed directly to the output stage in the case of a high-speed channel (BHx), or
the signal is routed through a debounce filter block in the case of a low-speed channel (Bx) for robust operation in industrial
environments. For the CA-IS3980S, there are three debounce filter modes available: deglitch filter mode, low-pass filter mode,
and blanking filter mode. For the parallel outputs devices, the CA-IS398xP, there are four debounce filter delay time options
available: no delay, delays of 10ms, 30ms, or 100 ms, see the Ordering Information for suffixes associated filter configuration
options. Additionally, a built-in low-pass filter delay of 4μs is always present in low-speed channels, regardless of user
configuration options.
The CA-IS398xP/PF/PM/PS devices translate eight 24V industrial digital inputs from sensors and switches used in
industrial, process and building automation to eight CMOS-compatible parallel outputs; while the CA-IS3980S industrial
interface serializer translates, conditions and serializes the eight 24V digital inputs to CMOS-compatible signals required by
microcontrollers and communicate with controllers through the SPI interface. For systems with more than eight sensor inputs,
the CA-IS3980S device is capable of daisy-chaining multiple devices and have up to 128 inputs (16 pieces of CA-IS3980S)
sharing the same isolated SPI interface.
9.2.
Device Operation Modes
The CA-IS398x digital input sense the state (on, high or off, low) of each input (Ax/AHx). The voltages at the Ax/AHx input
pins are compared against internal references to determine whether the sensor is on (logic 1) or off (logic 0), then the devices
translate the eight digital inputs to serial or parallel outputs, see Table 9-1 the truth table of the CA-IS398x.
The CA-IS398x devices include undervoltage lockout (UVLO) to prevent erroneous operation during device startup and
shutdown or when VDD is below its specified operating range. During UVLO, the outputs from the device do not track the
inputs to the device, would be in an undetermined state.
12
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Table 9-1. CA-IS398x Truth Table1
VDD
Powered up
Powered down
Input (Ax/AHx)
Output(Bx/BHx)
H
H
L
L
Open
L
X
Indeterminate2
Note
Normal operation. The outputs track the digital inputs.
Output is logic-low if input open.
If VDD 2.25V; Power down: VDD < VUVLO_.
2.
If VDD < VUVLO_, the output is indeterminate, can be any value within the absolute maximum rating.
9.3.
9.3.1.
Input Filters
Debounce filter selection and delay configuration
The CA-IS398x family isolated digital inputs offer serial outputs and parallel outputs options. A digital glitch filter provides
debouncing and filtering of noisy sensor signals on each low-speed digital input channel. The high-speed channels have no
debounce filtering to reduce the propagation delay. The debounce filter can be configured either through part number
selection for parallel output devices or through the SPI interface (CA-IS3980S only), see the Ordering Information for parallel
outputs devices selection with different filter delay options. For the CA-IS3980S debounce filter delay configuration details, see
Table 9-2. One of four filter delays (0ms, 10ms, 30ms, 100ms) can be independently selected for each channel.
Table 9-2. Debounce filter delay control
FLT_DLY[1:0]
Delay tD(ms)
Description
00
0
No additional debounce filter delay.
01
10
Fast channel debounce filter delay.
10
30
Medium channel debounce filter delay.
11
100
Slow channel debounce filter delay.
Note:
1.
All low-speed channels include a internal 4 μs low-pass debounce filter delay. Additional delay may be added based
on the FLT_DLY0, FLT_DLY1 registers configuration.
9.3.2.
Debounce filter operation modes
In addition to configuring filter delay time, the CA-IS3980S also provide selection between three filtering modes for each
of the digital input channels: deglitch filter, low-pass filter and blanking filter, allow flexible debouncing and filtering of sensor
outputs based on the application, see Table 9-3 for the debounce filter mode setting. All low-speed channels present on
parallel output devices are configured with the low-pass filter mode only.
Table 9-3. Debounce filter mode control
FLT_MODEx[1:0]
Filter mode
00
Deglitch filter
Trailing edge delay filter
01
Low-pass filter
Traditional low-pass filter
1x
Blanking filter
Leading edge delay filter
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Description
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Deglitch filter
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The deglitch filter mode corresponding to FLT_MODEx[1:0] = 00, employs only a simple trailing edge delay commonly
used in digital deglitch filters. In this mode, the device checks that an input is stable for at least the amount of time specified in
the corresponding channel’s debounce delay setting tD. Once the channel’s input has been stable for tD, the channel’s output
assumes the value of the channel’s input. Consequently, if the input is not stable for at least tD, the input change is not sent to
the internal shift register.
Low-pass filter
The low-pass filter corresponding to FLT_MODEx[1:0] = 01, provides a low-pass filtering function on each low-speed input
channel. This is also the mode of the built-in 4μs default filter in all low-speed channels. Under this filter mode, noise rejection
is accomplished through a nonrollover up-down counter where the state of the field digital input controls the counting
direction (up or down). When the channel input has assumed a new value, the counter begins counting up toward the
debounce delay setting tD. If before the count tD is reached the channel’s input returns to its previous value, it counts down. If
the channel input again assumes the new value before the counter reaches 0 (i.e., noise pulse width is less than the time the
channel input had previously assumed a new value), the counter counts up from a non-zero value. The filter output is updated
and assumes the new value when the counter hits the upper limit tD. Using low-pass filter mode, any noise pulse on the
channel input with duration less than the channel’s debounce filter delay setting tD, will be suppressed.
Blanking filter
The blanking filter mode corresponding to FLT_MODEx[1:0] = 1X, provides a leading edge filtering function on each lowspeed input channel. The internal counter is initialized to zero. When the channel input changes, the channel output
immediately assumes the new value, and the counter is reset to the current delay setting tD. Independent of what occurs on
the channel input, the counter begins counting down after this change, leaving the channel blind to changes on the input.
When the counter again reaches zero, the channel’s current input is compared to the channel’s current output. If they are
different the channel output immediately assumes the new value. If they are the same, the channel output will immediately
change on the next new value seen by the channel input. In any cases, a change on the channel input resets the counter to the
current delay setting tD.
Figure 9-2 shows the debounce filter modes timing diagram.
t2
tD – t1
DIN
A
B
A
tD
DOUT|DBNC_MODE=00
(old)
A
t1 + t2
DOUT|DBNC_MODE=01
DOUT|DBNC_MODE=1x
A
(old)
tD
tD
A
B
A
Figure 9-2. Debounce Filter Modes Timing Diagram
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Version 1.05, 2023/05/22
9.4. SPI Interface (CA-IS3980S)
The CA-IS3980S has an SPI compatible interface used to read digital inputs data and configure the filter delay, debounce
mode registers. Each configuration register can be read back to ensure proper configuration. For systems with more than eight
sensor inputs, the CA-IS3980S is capable of daisy-chaining multiple devices and have up to 128 inputs sharing the same
isolated SPI interface.
9.4.1.
Register Map and Description
The CA-IS3980S includes below addressable registers:
1. CHAN_STATUS: input data status register. The internal data serializer comprises a 8-bit shift register, containing 8 bits of
data corresponding to the eight field inputs. The shift register contents are read only (no write capability exists) through
the SPI-compatible interface.
2. FLT_MODE0, FLT_MODE1: the programmable filter mode control bits for A1 to A8, read and write registers, see Table 9-4
for more details.
3. FLT_DLY0, FLT_DLY1: the filter delay configuration bits for A1 to A8, read and write. These registers are used to set one of
four filter delays (0ms, 10ms, 30ms, 100ms) for each channel independently. See Table 9-4 for more details.
Table 9-4. Register Map
Register
Address
Type
CHAN_STATUS
0x0
Read only
FLT_MODE0
0x1
Read and Write
FLT_MODE1
0x2
Read and Write
FLT_DLY0
0x3
Read and Write
FLT_DLY1
0x4
Read and Write
Description
{STATUS[7:0]}, Digital input state, D[x] is the state of the corresponding input pin.
0: D[x] = 0, channel x is driven low.
1: D[x] = 1, channel x is driven high.
Programmable filter mode control bits for A1 to A4, organized as:
{md_ch3[1:0],md_ch2[1:0],md_ch1[1:0],md_ch0[1:0]}
md_chx[1:0] = 00 = deglitch filter; md_chx = 01 = low-pass filter;
md_chx = 1X = blanking filter
Programmable filter mode control bits for A5 to A8, organized as:
{md_ch7[1:0],md_ch6[1:0],md_ch5[1:0],md_ch4[1:0]}
md_chx[1:0] = 00 = deglitch filter; md_chx = 01 = low-pass filter;
md_chx = 1X = blanking filter
Programmable filter delay values for A1 to A4, organized as:
{dly_ch3[1:0], dly_ch2[1:0], dly_ch1[1:0], dly_ch0[1:0]}
dly_chx[1:0] = 00 = 0ms; dly_chx[1:0] = 01 = 10ms;
dly_chx[1:0] = 10 = 30ms, dly_chx[1:0] = 11 = 100ms.
Programmable filter delay values for A5 to A8, organized as:
{dly_ch7[1:0], dly_ch6[1:0], dly_ch5[1:0], dly_ch4[1:0]}
dly_chx[1:0] = 00 = 0ms; dly_chx[1:0] = 01 = 10ms;
dly_chx[1:0] = 10 = 30ms, dly_chx[1:0] = 11 = 100ms.
9.4.2. SPI Protocol
The CA-IS3980S communicates with microcontrollers through an SPI-compatible 4-wire serial interface. The interface has
three inputs: clock (SCLK), chip select (NSS), and data in (MOSI), and one output, data out (MISO). An additional MOSI_THRU
output is provided to facilitate the cascading of up to 16 CA-IS3980S devices. The CA-IS3980S devices are the slave device in an
SPI communication with the microcontroller being the master. The NSS input is used to initiate and terminate a data transfer.
SCLK is used to synchronize data movement between the master (microcontroller) and the slave devices. NSS must be low to
clock data into or out of the device, and MOSI must be stable when sampled on the rising edge of SCLK. MISO and MOSI_THRU
are stable on the rising edge of SCLK. The CA-IS3980S ignores all activity on SCLK and DIN except when NSS is low. Please see
Figure 7-1 SPI timing diagram and Timing Characteristics to find more details.
The CA-IS3980S SPI communication packet is composed of three serial bytes, byte0, byte 1 and byte 2, see Figure 9-3 for a
SPI communication packet. In this sequence, byte 0 is the control byte, and specifies the operation to be performed as well as
the device to be selected in a daisy-chain organization. The CID[3:0] is device ID for each CA-IS3980S in daisy chain. This field
should be set to all zeros by the SPI master in non daisy-chained operation. Next, byte 1 specifies the address of the internal
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CA-IS3980S SPI register to be accessed (read or write). If the write address provided does not correspond to a physically
available internal register, no internal CA-IS3980S register update will occur in the SPI write operation; while if the read
address provided does not correspond to a physically available internal register, all zeroes will be returned as the read value by
the CA-IS3980S in the SPI read operation. The final byte, byte 2 in the packet consists of either the data to be written into the
addressed CA-IS3980S SPI register (using MOSI), or the data read from the addressed CA-IS3980S SPI register (using MISO).
Data is read from the status/configuration registers or written to the configuration registers MSB first for SPI communication.
The serial clock (SCLK), which is generated by the microcontroller, is active only when NSS is low and during control byte,
address and data transfer to any device on the SPI bus. Control byte, address and data bits are transferred in groups of eight,
MSB first, this means each of the eight bits for this three byte communication packet is captured by the CA-IS3980S on eight
adjacent rising edges of SCLK. If NSS goes high in the middle of a transmission (any time before the 8th bit), the sequence is
aborted, the CA-IS3980S lost synchronization with host SPI and cause communication error. In this case, the target register
value will not be changed. Every time NSS goes low, a new 8-bit stream is expected. (i.e., data does not get written to internal
registers). However, if more than 8 bits data are clocked into the CA-IS3980S in the last byte, the target register data will be
uncertain, need to rebuild synchronization with SPI host.
Take NSS high and SPI host issue clock signal to rebuild SPI communication. The SCLK rising edge during NSS high will
reset the internal SPI state machine and build synchronization between the CA-IS3980S and SPI host. After rebuilding
communication with host, NSS goes low and the host issues 8 bits as the first byte (byte0) of the three serial bytes to initiate
communication. Note that, after the synchronization operation, the first byte of SPI (byte0) must be transmitted to initiate
communication.
NSS
SCLK
Control[7:0]
MOSI
Byte 0
Address[7:0]
Data[7:0]
Byte 1
Byte 2
Figure 9-3. SPI Communication Protocol
Table 9-5. SPI communication packet
Control Byte
7
6
5
4
3
2
1
0
BRCT
R/Wb
0
0
CID[0]
CID[1]
CID[2]
CID[3]
Address Byte
7
6
5
4
3
2
1
0
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Data Byte
7
6
5
4
3
2
1
0
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Table 9-6. Bit descriptions for the control byte
Control Byte (byte 0)
16
BIT_7
BIT_6
BIT_5
BIT_4
BIT_3
BIT_2
BIT_1
BIT_0
BRCT
R/Wb
0
0
CID[0]
CID[1]
CID[2]
CID[3]
1 - broadcast (write)
0 – Write the addressed part only
Note: the status of this bit is ignored if
in read operation.
1 - read
0 - write
Reserved
Set to (0,0)
CID[3:0] is daisy-chained device ID
CID[3:0] = 0000 (CID[0:3] = 0000) in non daisy-chained
operation.
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CA-IS3980, CA-IS3988
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Referring to Figure 9-3, in an SPI read operation the control byte will only have bit 6 set to a 1 in a single CA-S3980S device
organization (no daisy chaining). Bit 7 (the broadcast bit) is ignored during a read operation since only one device may be read
at a time in either a single or daisy-chained organization. The read data is provided during the final byte of the three byte read
communication packet to the querying master SPI device through the MISO output, which remains tri-stated at all other times.
In an SPI write operation, if the bit 7 (the broadcast bit) of control byte set to 1, during an SPI write operation, the broadcast
bit forces all daisy-chained CA-IS3980S devices to update the designated internal SPI register with the supplied write data,
regardless of the CA-IS3980S device being addressed using the CID[3:0] field of the control word. If the bit 7 of Byte 0 set to 0,
only have the addressed CA-IS3980S device to update the internal register. The write data is provided by the SPI master during
the final byte of the three byte write communication packet. The CA-IS3980S MISO output remains tri-stated during the entire
SPI write operation.
9.4.3.
SPI Daisy-Chaining
For systems with more than eight sensor inputs, multiple CA-IS3980S devices can be daisy-chained to allow access to all
data inputs through a single serial port. When using a daisy-chain configuration, connect MOSI of SPI master to MOSI of the
first device CA-IS3980S[0] in the chain. Connect SPI master MISO to MISO pin of all CA-IS3980S devices in the chain. For all
middle links, connect MOSI to MOSI_THRU of the previous device and MOSI_THRU to MOSI of the next device. NSS and SCLK
of all devices in the chain should be connected together in parallel, see Figure 9-4 which illustrates a 128-inputs application for
daisy-chaining.
Each CA-IS3980S is assigned a device ID CID[3:0] which is corresponded bit 0 to bit 3 of the control byte, as the address in
daisy chain, see Table 9-7 the device ID for each of CA-IS3980S device. All bits composing an SPI communication packet from
the SPI master are passed directly through by the CA-IS3980S from the MOSI input to the MOSI_THRU output unchanged,
except for the CID[3:0] field of the control byte. As this bit field is passed through the CA-IS3980S, it is decremented by one.
When a given CA-IS3980S device in the daisy chain is presented with the CID[3:0] code of 0000, it is activated as the one to be
addressed slave device, thereby enabling this device. After locking the addressed device, all remaining operations between the
SPI master and the CA-IS3980S activated in this manner proceed as previously discussed in the SPI interface communication
protocol above section for the case of a single CA-IS3980S slave. Please note that the SPI master placed the 4-bit device ID (CID
[3:0]) in control word in reverse order, as shown in Table 9-7, CID[0] is placed at bit 3 and CID[3] placed at bit 0 of the control
byte. When operating the addressing instruction, pay attention to the order of device ID code.
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MOSI_THRU
MISO
NSS
SCLK
MISO
NSS
SCLK
MOSI
MOSI_THRU
CA-IS3980S[15]
MOSI
MISO
NSS
SCLK
MOSI
CA-IS3980S[2]
MOSI_THRU
MISO
NSS
SCLK
MOSI
CA-IS3980S[1]
MOSI_THRU
MISO
NSS
SCLK
MOSI
CA-IS3980S[0]
SPI Master
Figure 9-4. SPI Daisy-Chaining Organization
17
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The CA-IS3980S device supports three kind of control command: broadcast write, only addressed part write, only
addressed part read, see Table 9-8. During the daisy-chain write operation, if the broadcast bit is 0, only the CA-IS3980S device
being addressed using the CID[3:0] field of the control byte in a daisy-chain will be updated. If the broadcast bit is 1 during a
daisy-chain write operation, the CID[3:0] field is ignored, and all CA-IS3980S devices connected in a daisy chain will be updated.
For example, in order to write to CA-IS3980S[12], the control byte would be: Control[7:0] = 00000011, here CID[3:0]=1100.
Note that there is a delay time associated with passing the MOSI input pin of a given CA-IS3980S to the MOSI_THRU output pin.
As a result, the maximum possible SCLK frequency will be reduced based on the number of devices connected in a daisy-chain.
Table 9-7. Device ID for each of CA-IS3980S in the daisy-chain
CAIS3980S[1]
CAIS3980S[2]
CAIS3980S[3]
CAIS3980S[4]
CAIS3980S[5]
CAIS3980S[6]
CAIS3980S[7]
CID[3:0]
CAIS3980S[0]
0000
0001
0010
0011
0100
0101
0110
0111
CID[0:3]1
0000
1000
0100
1100
0010
1010
0110
1110
Device ID
CID[3:0]
CAIS3980S[8]
1000
CAIS3980S[9]
1001
CAIS3980S[10]
1010
CAIS3980S[11]
1011
CAIS3980S[12]
1100
CAIS3980S[13]
1101
CAIS3980S[14]
1110
CAIS3980S[15]
1111
CID[0:3]1
0001
1001
0101
1101
0011
1011
0111
1111
Device ID
Note:
1.
CID[3:0] are dedicated to addressing one of up to 16 CA-IS3980S devices connected in a daisy chain. This four bit field is placed in the
control word by the SPI master in reverse order, CID[0] is placed at bit 3 and CID[3] placed at bit 0 of the control byte.
Table 9-8. Daisy-chain Operation Command
Control Byte (Control[7:0])
Command
BIT_7
BIT_6
BIT_5
BIT_4
BIT_3
BIT_2
BIT_1
BIT_0
BRCT
R/Wb
0
0
CID[0]
CID[1]
CID[2]
CID[3]
Broadcast Write
1
0
0
0
0
0
0
0
Write CA-IS3980S[n]
0
0
0
0
Read CA-IS3980S[n]
0
1
0
0
CID[0:3]
Note: CID[3:0] is the addressed device ID.
10. Application and Implementation
The CA-IS398x devices are complete, isolated digital-input receivers with IEC 61131-2 Type 1, Type 2, and Type 3
characteristics, Figure 10-1 provides the input channel switching characteristics. These devices enable 24 V bipolar digital
inputs to be connected to its input through a resistor divider network, see Figure 10-2 and Figure 10-3 the typical application
circuits for the current sinking inputs and current sourcing inputs respectively. The digital inputs On/Off voltage thresholds at
the device pin are fixed to VF(TH) and (VF(TH) – VHYS), see Electrical Characteristics for the typical threshold value. However the
On/Off voltage thresholds of the field input are determined by the value of the resistor divider R1 and R2 placed between the
field input and the device, and the input current IIN. Please see Table 10-1 for the recommended external resistors of Type 1,
Type 2 and Type 3 sensors or switches based on 24 V DC PLC digital input types as defined by IEC 61131-2.
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Type 1
Type 2
30
Type 3
30
25
30
25
25
ON
ON
ON
20
20
15
15
15
VIN (V)
VIN (V)
VIN (V)
20
10
10
10
5
5
5
OFF
0
OFF
0
-3
OFF
0
5
IIN (mA)
10
15
OFF
0
-3
-3
0
5
10
15
IIN (mA)
20
25
30
0
5
10
15
IIN (mA)
Figure 10-1. Switching Characteristics for IEC 61131-2 Type 1, 2, and 3 24VDC Digital Inputs
Other digital voltage levels and characteristics can be implemented with simple modifications to the resistor divider
network. Note that, the 2.2nF capacitor in Figure 10-2 and Figure 10-3 is used to filter noise on the high-speed channels only.
For the low-speed channels, we do not recommend to use external RC filter at inputs because the capacitor will cause very
high transient voltage under surge condition. The built-in debounce filters can be used to filter noise on the low-speed
channels.
Table 10-1. Recommended external components in the typical application circuit
Resistor network
Type 1
Type 2
Type 3
R1
2.4kΩ
390Ω
750Ω
R2
6.2kΩ
1.5kΩ
2.7kΩ
Note: These recommendations assume a resistor tolerance of 5%, it is highly recommended that a MELF resistor be used.
Field Side
μController
R2
VD
2.2nF
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Ax /AHx
R1
Isolation Barrier
VDD
Sensor
Switch
24V DC
PLC
PLC Digital Input
Bx /BHx
Input
R3
D2
COM
GND
GND
CA-IS398x
Figure 10-2. Typical Application Circuit with Sinking Inputs
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PLC Digital Input
Field Side
PLC
µController
R1
2.2nF
24V DC
Ax /AHx
VD
R2
Isolation Barrier
VDD
Bx /BHx
Input
R3
D2
COM
Sensor
Switch
GND
GND
CA-IS398x
Figure 10-3. Typical Application Circuit with Sourcing Inputs
Designing high-channel count digital inputs modules require cascading multiple CA-IS3980S devices. Simply connect the
serial output (MOSI_THRU) of a leading device with the serial input (MOSI) of a following device without changing the
processor interface, see Figure 10-4 the typical application circuit, also refer SPI Daisy-Chaining section for more details about
the daisy-chain operation.
Ax /AHx
COM
MOSI_THRU
MISO
NSS
SCLK
GND
VDD
MISO
NSS
SCLK
MISO
MOSI_THRU
CA-IS3980S[15]
MOSI
NSS
SCLK
MOSI
GND
VDD
……
MOSI
……
24V DC
COM
Sensor
Switch
24V DC
CA-IS3980S[2]
MOSI_THRU
MISO
NSS
SCLK
GND
VDD
MOSI_THRU
MISO
NSS
SCLK
GND
MOSI
Ax /AHx
Ax /AHx
CA-IS3980S[1]
CA-IS3980S[0]
VDD
……
MOSI
……
Sensor
Switch
24V DC
COM
Sensor
Switch
24V DC
COM
Ax /AHx
Sensor
Switch
μController
Figure 10-4. Typical Application Circuit with Daisy-Chaining
To reduce ripple and the chance of introducing data errors, bypass VDD with at least 0.1μF low-ESR ceramic capacitors to
GND. Place the bypass capacitor as close to the power supply input pin as possible. The PCB designer should keep the
input/output traces as short as possible and keep signal paths low-inductance, avoid using vias. The area underneath the CAIS398x isolation barrier should be free from ground and signal planes.
20
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
Shanghai Chipanalog Microelectronics Co., Ltd.
11. Package Information
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
SSOP20 Package Outline
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
21
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
12. Soldering Temperature (reflow) Profile
Shanghai Chipanalog Microelectronics Co., Ltd.
TP
Max. Ramp Up Rate=3℃/s
Temperature
TL
Tsmax
tP
TC-5℃
tL
Preheat Area
Tsmin
ts
25℃
Time 25℃ to Peak
Time
Figure 12-1. Soldering Temperature (reflow) Profile
Table 12-1. Soldering Temperature Parameter
Profile Feature
Average ramp-up rate(217˚C to Peak)
Time of Preheat temp(from 150˚C to 200 ˚C
Time to be maintained above 217˚C
Peak temperature
Time within 5 ˚C of actual peak temp
Ramp-down rate
Time from 25˚C to peak temp
22
Pb-Free Assembly
3˚C /second max
60-120 second
60-150 second
260 +5/-0 ˚C
30 second
6 ˚C /second max.
8 minutes max
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
Shanghai Chipanalog Microelectronics Co., Ltd.
13. Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
Y0
B0
K0
W
P1
Dimension designed to accommodate the component width
Dimension designed to accommodate the component
length
Dimension designed to accommodate the component
thickness
Overall width of the carrier tape
Pitch between successive cavity centers
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
*All dimensions are nominal.
Device
Package
Type
Package
Drawing
Pins
SPQ
CA-IS3980S
CA-IS3980P
CA-IS3988P
SSOP
SSOP
SSOP
Y
Y
Y
20
20
20
2500
2500
2500
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
Reel
Diameter
(mm)
330
330
330
Reel Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
16.4
16.4
16.4
6.50
6.50
6.50
9.40
9.40
9.40
2.00
2.00
2.00
8.00
8.00
8.00
16.00
16.00
16.00
Pin1
Quadran
t
Q1
Q1
Q1
23
CA-IS3980, CA-IS3988
Version 1.05, 2023/05/22
14. Important statement
Shanghai Chipanalog Microelectronics Co., Ltd.
The above information is for reference only and used for helping Chipanalog customers with design, research and
development. Chipanalog reserves the rights to change the above information due to technological innovation without
advance notice.
All Chipanalog products pass ex-factory test. As for specific practical applications, customers need to be responsible for
evaluating and determining whether the products are applicable or not by themselves. Chipanalog's authorization for
customers to use the resources are only limited to development of the related applications of the Chipanalog products. In
addition to this, the resources cannot be copied or shown, and Chipanalog is not responsible for any claims, compensations,
costs, losses, liabilities and the like arising from the use of the resources.
Trademark information
Chipanalog Inc.® and Chipanalog® are registered trademarks of Chipanalog.
http://www.chipanalog.com
24
Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.
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