SLMi823x
Dual Channel 1A and 4A, 5.0kVRMS Isolated Gate Driver
GENERAL DESCRIPTION
FEATURE
The SLMi823x isolated driver family is an isolated
dual channel gate driver with different configurations.
The SLMi8230/1/3/4 are configured as high-side/lowside drivers, while the SLMi8232/5 are configured as
dual drivers. The peak source output current of
SLMi8230/1/2 is 1.0A and the peak source output
current of SLMi8233/4/5 is 4.0A. Programmable dead
time (DT) feature is available in SLMi8230/1/3/4.
Pulling high the DIS pin shuts down both outputs
simultaneously, and allows for normal operation when
the DIS pin is open or pulled low. As a fail-safe
measure, primary-side logic failures force both
outputs low.
•
•
•
•
1.0A or 4.0A peak source current
40ns (Typ.) propagation delay
18ns (Max.) pulse width distortion
18ns (Max.) delay matching
•
100kV/us (Min.) common mode transient
immunity (CMTI)
Wide input voltage: 3V to 18V
Up to 40V driver output voltage
5V reverse polarity voltage handling capability on
input stage
1500V functional isolation between two drivers
Operating temperature: –40°C to +125°C
Safety certifications:
• 5kVRMS isolation for 1 minute per UL 1577
with SOP16W package
• CQC certification per GB4943.1-2011
• TUV certification per EN/IEC 61010-1:
2010+A1 and EN/IEC 62368-1: 2018
• DIN V VDE 0884-11 (Planned)
•
•
•
•
•
•
The VDDA and VDDB supply voltage are up to 40 V.
A wide input VDDI range from 3 V to 18 V makes the
driver suitable for interfacing with both analog and
digital controllers. All the supply voltage pins have
under voltage lock-out (UVLO) protection.
The SLMi823x has 5.0kVRMS isolation in SOP16W
package per UL1577.
High CMTI, low propagation delay, small size and
flexible configuration make the SLMi823x family is
suitable for a wide range of isolated MOSFET/IGBT
and SiC or GaN FET gate drive applications.
APPLICATION
•
•
•
AC/DC or DC/DC power supplies in server,
telecom and industry
DC/AC solar inverters
EV battery charging
APPLICATION CIRCUIT
VDDB
D1
VDDI
C3
1uF
VDDI
C1
1uF
C2
0.1uF
VBUS
GNDI
VDDA
C6
Q1
VOA
GNDA
VIA
VIB
PWM
CONTROLLER
SLMi8230/3
VDDB
DT
CDT
VDDB
RDT
C4
0.1uF
C5
10uF
GNDB
DIS
Q2
VOB
Figure 1. SLMi8230/3 Application Circuit
Sillumin Semiconductor Co., Ltd. – www.sillumin.com
Rev1.3, Jul 2023
1
SLMi823x
VDDB
D1
VDDI
C3
1uF
VDDI
C1
1uF
C2
0.1uF
VBUS
VDDA
GNDI
C6
Q1
VOA
PWMOUT
PWM
GNDA
SLMi8231/4
PWM
CONTROLLER
VDDB
DT
CDT
VDDB
RDT
C4
0.1uF
C5
10uF
GNDB
Q2
DIS
VOB
Figure 2. SLMi8231/4 Application Circuit
VDDI
VDDI
C1
1uF
Q1
C2
0.1uF
VOA
GNDI
VDDA
VDDA
C3
0.1uF
GNDA
VIA
PWM
CONTROLLER
C4
10uF
VIB
SLMi8232/5
VDDB
VDDB
C5
0.1uF
C6
10uF
GNDB
DIS
Q2
VOB
Figure 3. SLMi8232/5 Application Circuit
Sillumin Semiconductor Co., Ltd. – www.sillumin.com
Rev1.3, Jul 2023
2
SLMi823x
Table of Contents
General Description ....................................................................................................................................................1
Feature ........................................................................................................................................................................1
Application ..................................................................................................................................................................1
Application Circuit .......................................................................................................................................................1
PIN Configuration .......................................................................................................................................................4
PIN Description ...........................................................................................................................................................5
Functional Block Diagram ...........................................................................................................................................7
Ordering Information ...................................................................................................................................................8
Family Overview .........................................................................................................................................................8
Absolute Maximum Ratings1 .......................................................................................................................................9
Recommended Operation Conditions1 .......................................................................................................................9
ESD Ratings ...............................................................................................................................................................9
Thermal Information ..................................................................................................................................................10
Package Specifications .............................................................................................................................................11
Insulation Specifications ...........................................................................................................................................11
Safety Related Certifications ....................................................................................................................................12
Safety LimitING Values .............................................................................................................................................12
Electrical Characteristics (DC) ..................................................................................................................................13
Switching Characteristics (AC) .................................................................................................................................14
Parameter Measurement Information .......................................................................................................................15
Propagation Delay and Pulse Width Distortion .................................................................................................15
Rise and Fall Time Testing ................................................................................................................................15
CMTI Testing .....................................................................................................................................................15
Feature Description ..................................................................................................................................................16
Under Voltage Lockout ......................................................................................................................................16
Disable Input Function .......................................................................................................................................16
Control Input and Output Logic .........................................................................................................................16
Dead-time Program ...........................................................................................................................................17
Application Information .............................................................................................................................................19
Layout .......................................................................................................................................................................20
Package Case Outlines ............................................................................................................................................21
Reflow Profile Guidance ...........................................................................................................................................22
Revision History ........................................................................................................................................................23
Sillumin Semiconductor Co., Ltd. – www.sillumin.com
Rev1.3, Jul 2023
3
SLMi823x
PIN CONFIGURATION
Part Number
SLMi8230/3
SLMi8231/4
SLMi8232/5
Pin Configuration (Top View)
VIA
1
16
VDDA
VIB
2
15
VOA
VDDI
3
14
GNDA
GNDI
4
13
NC
SLMi8230/3
DIS
5
12
NC
DT
6
11
VDDB
NC
7
10
VOB
VDDI
8
9
GNDB
PWM
1
16
VDDA
NC
2
15
VOA
VDDI
3
14
GNDA
GNDI
4
13
NC
SLMi8231/4
DIS
5
12
NC
DT
6
11
VDDB
NC
7
10
VOB
VDDI
8
9
GNDB
VIA
1
16
VDDA
VIB
2
15
VOA
VDDI
3
14
GNDA
GNDI
4
13
NC
SLMi8232/5
DIS
5
12
NC
NC
6
11
VDDB
NC
7
10
VOB
VDDI
8
9
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Rev1.3, Jul 2023
GNDB
4
SLMi823x
PIN DESCRIPTION
Table 1. SLMi8230/3 Pin Description
No.
Pin
Description
1
VIA
Input of driver A. The output of driver A is in phase with the input. This pin is pulled
low internally if left open. Recommend to connect this pin to ground if not used for
better noise immunity.
2
VIB
Input of driver B. The output of driver B is in phase with the input. This pin is pulled
low internally if left open. Recommend to connect this pin to ground if not used for
better noise immunity.
3
VDDI
Input power supply. A local low ESR and ESL capacitor should be connected
between VDDI and GNDI.
4
GNDI
Input power ground.
5
DIS
Device disable input. When DIS pin is high, both driver is disabled and driver output
is low. When DIS pin is low, it allows the device to perform in normal operation.
6
DT
Dead time programming input. Connect a resistor between DT and GNDI to
program the dead time. A bypassing capacitor, 2.2nF or greater, is recommended
to be put between DT and GNDI to achieve better noise immunity.
7
NC
No connection
8
VDDI
Input power supply. This pin is internally connected to pin3.
9
GNDB
Power ground of driver B.
10
VOB
Output of driver B.
11
VDDB
Power supply of driver B. A local low ESR and ESL capacitor should be connected
between VDDB and GNDB.
12
NC
No connection
13
NC
No connection
14
GNDA
Power ground of driver A.
15
VOA
Output of driver A.
16
VDDA
Power supply of driver A. A local low ESR and ESL capacitor should be connected
between VDDA and GNDA.
Table 2. SLMi8231/4 Pin Description
No.
Pin
Description
1
PWM
PWM input. The output of driver A is in phase with PWM input and the output of
driver B is out of phase with PWM input.
2
NC
No connection
3
VDDI
Input power supply. A local low ESR and ESL capacitor should be connected
between VDDI and GNDI.
4
GNDI
Input power ground.
5
DIS
6
DT
Device disable input. When DIS pin is high, both driver is disabled and driver output
is low. When DIS pin is low, it allows the device to perform in normal operation.
Dead time programming input. Connect a resistor between DT and GNDI to
program the dead time. A bypassing capacitor, 2.2nF or greater, is recommended
to be put between DT and GNDI to achieve better noise immunity.
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Rev1.3, Jul 2023
5
SLMi823x
No.
Pin
Description
7
NC
No connection
8
VDDI
Input power supply. This pin is internally connected to pin3.
9
GNDB
Power ground of driver B.
10
VOB
Output of driver B.
11
VDDB
Power supply of driver B. A local low ESR and ESL capacitor should be connected
between VDDB and GNDB.
12
NC
No connection
13
NC
No connection
14
GNDA
Power ground of driver A.
15
VOA
Output of driver A.
16
VDDA
Power supply of driver A. A local low ESR and ESL capacitor should be connected
between VDDA and GNDA.
Table 3. SLMi8232/5 Pin Description
No.
Pin
Description
1
VIA
Input of driver A. The output of driver A is in phase with the input. This pin is pulled
low internally if left open. Recommend to connect this pin to ground if not used for
better noise immunity.
2
VIB
Input of driver B. The output of driver B is in phase with the input. This pin is pulled
low internally if left open. Recommend to connect this pin to ground if not used for
better noise immunity.
3
VDDI
Input power supply. A local low ESR and ESL capacitor should be connected
between VDDI and GNDI.
4
GNDI
Input power ground.
5
DIS
Device disable input. When DIS pin is high, both driver is disabled and driver output
is low. When DIS pin is low, it allows the device to perform in normal operation.
6
NC
No connection
7
NC
No connection
8
VDDI
Input power supply. This pin is internally connected to pin3.
9
GNDB
Power ground of driver B.
10
VOB
Output of driver B.
11
VDDB
Power supply of driver B. A local low ESR and ESL capacitor should be connected
between VDDB and GNDB.
12
NC
No connection
13
NC
No connection
14
GNDA
Power ground of driver A.
15
VOA
Output of driver A.
16
VDDA
Power supply of driver A. A local low ESR and ESL capacitor should be connected
between VDDA and GNDA.
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Rev1.3, Jul 2023
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SLMi823x
FUNCTIONAL BLOCK DIAGRAM
VDDI
VDDA
ISOLATION
VIA
VIB
VOA
UVLO
GNDA
VDDI
UVLO
GNDI
DT CONTROL
&OVERLAP
PROTECTION
DIS
VDDI
VDDB
ISOLATION
DT
VOB
UVLO
GNDB
SLMi8230/3
Figure 4. SLMi8230/3 Functional Block Diagram
VDDI
VDDA
ISOLATION
PWM
VOA
UVLO
GNDA
VDDI
UVLO
GNDI
DT CONTROL
&OVERLAP
PROTECTION
DIS
VDDI
VDDB
ISOLATION
DT
VOB
UVLO
GNDB
SLMi8231/4
Figure 5. SLMi8231/4 Functional Block Diagram
VDDI
VDDA
ISOLATION
VIA
VIB
VOA
UVLO
GNDA
VDDI
UVLO
GNDI
DIS
VDDI
ISOLATION
VDDB
VOB
UVLO
SLMi8232/5
GNDB
Figure 6. SLMi8232/5 Functional Block Diagram
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Rev1.3, Jul 2023
7
SLMi823x
ORDERING INFORMATION
Order Part No.
Package
QTY
SLMi8230BDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8230DDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8231BDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8231DDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8232BDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8232DDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8233BDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8233DDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8234BDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8234DDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8235BDCG-DG
SOP16W, Pb-Free
1500/Reel
SLMi8235DDCG-DG
SOP16W, Pb-Free
1500/Reel
FAMILY OVERVIEW
Part Number
Input
Configuration
Output
Configuration
Programmable
Dead Time
Overlap
Protection
Peak
Output
Current
UVLO
SLMi8230BDCG-DG
VIA,VIB
HS/LS
Yes
Yes
1.0 A
8.5V/7.5V
SLMi8230DDCG-DG
VIA,VIB
HS/LS
Yes
Yes
1.0 A
12.5V/11.5V
SLMi8231BDCG-DG
PWM
HS/LS
Yes
Yes
1.0 A
8.5V/7.5V
SLMi8231DDCG-DG
PWM
HS/LS
Yes
Yes
1.0 A
12.5V/11.5V
SLMi8232BDCG-DG
VIA,VIB
Dual Driver
No
No
1.0 A
8.5V/7.5V
SLMi8232DDCG-DG
VIA,VIB
Dual Driver
No
No
1.0 A
12.5V/11.5V
SLMi8233BDCG-DG
VIA,VIB
HS/LS
Yes
Yes
4.0 A
8.5V/7.5V
SLMi8233DDCG-DG
VIA,VIB
HS/LS
Yes
Yes
4.0 A
12.5V/11.5V
SLMi8234BDCG-DG
PWM
HS/LS
Yes
Yes
4.0 A
8.5V/7.5V
SLMi8234DDCG-DG
PWM
HS/LS
Yes
Yes
4.0 A
12.5V/11.5V
SLMi8235BDCG-DG
VIA,VIB
Dual Driver
No
No
4.0 A
8.5V/7.5V
SLMi8235DDCG-DG
VIA,VIB
Dual Driver
No
No
4.0 A
12.5V/11.5V
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Rev1.3, Jul 2023
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SLMi823x
ABSOLUTE MAXIMUM RATINGS1
Symbol
Definition
Min
Max
Unit
VDDI
Input Power Supply Voltage
-0.3
20
V
VIA,VIB, VDIS,VPWM
Input Signal Voltage
-7
20
V
VDDA, VDDB
Driver Power Supply
-0.3
45
V
Driver Output Voltage
-0.3
VDDA+0.3,
VDDB+0.3
V
Driver Output Voltage, Transient for 200ns2
-3
VDDA+0.3,
VDDB+0.3
V
Driver Output Voltage, Transient for 50ns2
-6
VDDA+0.3,
VDDB+0.3
V
1500
V
VOUTA, VOUTB
Vch2ch
Channel to Channel Voltage
TJ
Junction Temperature
-40
150
C
TS
Storage Temperature
-65
150
C
RECOMMENDED OPERATION CONDITIONS1
Symbol
Definition
Min
Max
Unit
VDDI
Input Power Supply Voltage
3
18
V
VIA,VIB, VDIS,VPWM
Input Signal Voltage
-5
18
V
9
40
V
13.5
40
V
VDDA, VDDB
VDDA, VDDB
Driver Power Supply
(8.5V UVLO Version)
Power Supply for Driver
(12.5V UVLO Version)
TJ
Junction Temperature
-40
150
C
TA
Storage Temperature
-40
125
C
ESD RATINGS
Symbol
Definition
Value
HBM
4000
CDM
2000
VESD
Units
V
Note 1: VDDI, VIA, VIB, VDIS, VPWM are reference to GNDI; VDDA, VOUTA are referenced to GNDA; VDDB, VOUTB are
referenced to GNDB;
Note 2: Values are verified by characterization on bench
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Rev1.3, Jul 2023
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SLMi823x
THERMAL INFORMATION
Symbol
Definition
Value
Unit
RθJA
Junction to ambient thermal resistance
100
°C/W
RθJC(TOP)
Junction to case (top) thermal resistance
40
°C/W
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Rev1.3, Jul 2023
10
SLMi823x
PACKAGE SPECIFICATIONS
Symbol
Definition
Min.
Typ.
Max.
Units
RIO
Resistance (Input Side to Output Side)
1012
CIO
Capacitance (Input Side to Output Side)
1.8
pF
INSULATION SPECIFICATIONS
Symbol
Definition
Test Condition
Value
Units
CLR
External clearance
Shortest terminal to terminal
distance through air
8.0
mm
CPG
External creepage
Shortest terminal to terminal
distance across the package
surface
8.0
mm
DTI
Distance through the insulation
Minimum internal gap
>16
um
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11),
IEC 60112
>600
V
Material Group
Overvoltage category
I
Rated mains voltages 150Vrms
I-IV
Rated mains voltages 300Vrms
I-IV
Rated mains voltages 600Vrms
I-III
Rated mains voltages 1000Vrms
I-II
DIN V VDE 0884-11(1)
VIORM
Maximum repetitive peak isolation
voltage
1414
VPK
VIOWM
Maximum isolation working
voltage
1000
VRMS
VIOTM
Maximum transient isolation
voltage
60s
7000
VPK
VIOSM
Maximum surge isolation voltage
Test method per IEC62368,
1.2/50us waveform, VTEST=1.6 x
VIOSM
6250
VPK
qpd
Apparent charge
Method b2: Vpd(m)=1.875 x VIORM,
tm=1 s
5
pC
Climatic Category
40/125/21
Pollution Degree
2
UL1577
VISO
Withstand Isolation Voltage
VTEST=VISO, t=60s (qualification),
VTEST=1.2 x VISO, t=1s (100%
production)
5000
VRMS
Note 1: Certification planned
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Rev1.3, Jul 2023
11
SLMi823x
SAFETY RELATED CERTIFICATIONS
VDE
UL
CQC
TUV
DIN V VDE 088401111: 2017-01
UL 1577 component
recognition program
Certified according to
Certified according to EN
IEC 61010-1: 2010+A1 and
EN IEC 62368-1: 2018
Reinforced Insulation
Single protection, 5000
VRMS
Certification Pending
File number: E521801
Reinforced insulation,
Altitude≤ 5000m, Tropical
climate,400 VRMS maximum
working voltage
File number:
CQC21001324484
GB4943.1-2011
5000Vrms reinforced
insulation, 800Vrms
maximum working voltage
Ref.Certif.No: DE 2-038921
Ref.Certif.No: JPTUV146634
Certificate No: R 50590519
SAFETY LIMITING VALUES
Symbol
IS
Parameter
Side
Value
Unit
Driver A and
Driver B
73
mA
Condition
Safety output current
VDDA=VDDB=16V, CLOAD=1nF,
2MHz PWM, 50% duty,
RθJA=100°C/W,
TJ =150°C, TA =25°C
PS
Input
36
Driver A
584
TJ =150°C, TA =25°C
Driver B
Total
584
1204
Maximum safety
temperature
80
1600
70
1400
60
50
40
30
20
10
0
0
mW
150
Safety Limiting Power (mW)
Safety Limiting Current (mA)
TS
Safety input, output,
or total power
VDDA=VDDB=16V, CLOAD=1nF,
VDDI=12V, 2MHz PWM, 50%
duty, RθJA=100°C/W,
°C
1200
1000
800
600
400
200
25
50
75
100
125
150
Ambient Temperature (oC)
Figure 7. Thermal Derating Curve for Limiting Current
per VDE (Current in VDDA and VDDB)
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Rev1.3, Jul 2023
0
0
25
50
75
100
125
150
Ambient Temperature (oC)
Figure 8. Thermal Derating Curve for Limiting Power
per VDE
12
SLMi823x
ELECTRICAL CHARACTERISTICS (DC)
VDDI = 5 V, 0.1μF capacitor from VDDI to GNDI, VDDA = VDDB =15V, 1μF capacitor from VDDA and VDDB to GNDA
and GNDB, TA = –40°C to +125°C, unless otherwise specified.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
18
V
Input Power Supply
VDDI
Input Supply Voltage
3
VUVLO_VDDI_R
VDDI UVLO Rising
2.55
2.7
2.85
V
VUVLO_VDDI_F
VDDI UVLO Falling
2.35
2.5
2.65
V
VUVLO_HYS
VDDI UVLO Hysteresis
IVDDI
0.2
Quiescent Current
VIA = 0V, VIB = 0V
Operation Current
fsw= 100kHz, (50% Duty
Cycle), both channels
1.4
2
V
2.6
3.3
mA
mA
Logic Interface
VIH
High Level Input Threshold
Voltage at VIA, VIB, DIS and
PWM
VIL
Low Level Input Threshold
Voltage at VIA, VIB, DIS and
PWM
RPD
Pull down Resistance on
VIA,VIB,DIS and PWM
2
V
0.8
V
126
180
280
k
8.5V UVLO Version
8
8.5
9
V
12.5V UVLO Version
11.5
12.5
13.5
V
8.5V UVLO Version
7
7.5
8
V
12.5V UVLO Version
10.5
11.5
12.5
V
Driver Power Supply
VUVLO_VDDA_R,
VUVLO_VDDB_R
VDDA, VDDB UVLO Rising
VUVLO_VDDA_F,
VUVLO_VDDB_F
VDDA, VDDB UVLO Falling
VUVLO_VDDA_HYS,
VUVLO_VDDB_HYS
VDDA, VDDB UVLO
Hysteresis
IVDDA,
VDDA/B Quiescent Current,
per Channel
IVDDB
8.5V UVLO Version
1
V
12.5V UVLO Version
1
V
VIA = 0V, VIB = 0V
0.8
1.5
2.6
mA
OUTPUT (SLMi8230/1/2)
IOH
Peak Source Current
1
A
IOL
Peak Sink Current
1.5
A
VOH
High Level Output Voltage
IO=-10mA
70
120
mV
VOL
Low Level Output Voltage
IO=10mA
30
65
mV
OUTPUT (SLMi8233/4/5)
IOH
Peak Source Current
4
A
IOL
Peak Sink Current
7
A
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Rev1.3, Jul 2023
13
SLMi823x
Symbol
Parameter
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
Condition
Min
Typ
Max
Unit
IO=-10mA
12
22
mV
IO=10mA
6.2
11
mV
220
k
240
ns
10
nF
Dead Time
RDT
Resistance range on DT
tDT
Dead time
CDT
5
RDT=20k
160
200
Capacitance of CDT
SWITCHING CHARACTERISTICS (AC)
VDDI = 5 V, 0.1μF capacitor from VDDI to GNDI, VDDA = VDDB =15V, 1μF capacitor from VDDA and VDDB to GNDA
and GNDB, TA = –40°C to +125°C, unless otherwise specified.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
40
60
ns
40
60
ns
6
15
ns
4
10
ns
Switching Characteristics
tPLH
Propagation Delay, Low to High
tPHL
Propagation Delay, High to Low
tr
Turn on Rise Time
tf
Turn off Fall Time
CLOAD=1nF, fsw=1kHz,
(50% Duty Cycle)
tPWD
Pulse Width Distortion
18
ns
tDM
Propagation Delay Matching
between OUTA and OUTB
18
ns
VDDI UVLO Recovery Delay
15
μs
tUVLO_REC_VDDA(B)
VDDA, VDDB UVLO Recovery
Delay
18
μs
CMTIH
High Level Static Common
Mode Transient Immunity
VCM=1000V, TA=25°C
100
kV/μs
CMTIL
Low Level Static Common
Mode Transient Immunity
VCM=1000V, TA=25°C
100
kV/μs
tUVLO_REC_VDDI
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SLMi823x
PARAMETER MEASUREMENT INFORMATION
Propagation Delay and Pulse Width Distortion
Figure 9 shows the timing diagram of the propagation delay tPDLH and tPDHL, pulse distortion tPWD and delay matching
tDM from the input VIA and VIB. Short the DT pin to VDDI to disable the dead time function.
VIA/B
tPLHA
tPHLA
tDM
VOA
tPLHB
tPHLB
tPWDB=|tPLHB -tPHLB|
VOB
Figure 9. Propagation Delay and Pulse Width Distortion
Rise and Fall Time Testing
Figure 10 shows the criteria for measuring rise time (tr) and fall time (tf).
80%
50%
tr
20%
tf
Figure 10. Turn On Rise Time and Turn Off Fall Time
CMTI Testing
Figure 11 is the simplified diagram of the CMTI testing. Common mode voltage is set to 1000V.
VCC
VDD
VIA
1
16
2
15
VCC
VDDI
GNDI
Reinforced Isolation
VIB
3
4
DIS 5
DT
NC
VDDI
6
14
VDDA
VOA
GNDA
Functional
Isolation
11
7
10
8
9
VDDB
VOB
GNDB
Common Mode Surge
Generator
Figure 11. CMTI Test Circuit
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Rev1.3, Jul 2023
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SLMi823x
FEATURE DESCRIPTION
SLMi823x is a flexible dual channel isolated gate driver that can drive IGBTs and MOSFETs. It has 1.0A or 4.0A
peak output current capability with maxim output driver supply voltage of 40V. SLMi823x has many features that
allow it to integrate well with control circuitry and protect the gates it drives such as: resistor programmable dead
time control, an DIS pin, and under voltage lock out (UVLO) for both input and output voltages.
Under Voltage Lockout
The SLMi823x has under voltage lock out (UVLO) protection feature on each driver power supply voltage between
the VDDA (VDDB) and GNDA (GNDB) pins. When the VDDx voltage is lower than VUVLO_VDDX_R, during device start
up or lower than VUVLO_VDDX_F, after start up, the VDDA (VDDB) UVLO feature holds the driver output low, regardless
of the status of the input pins. A hysteresis on the UVLO feature prevents glitch when there is noise from the power
supply.
The SLMi823x also monitors the input power supply and there is an internal under voltage lock out protection feature
on the VDDI. The driver outputs (VOA and VOB) are hold low when the voltage on the VDDI is lower than
VUVLO_VDDI_R during start up or lower than VUVLO_VDDI_F after start up. There is a hysteresis on the VDDI UVLO feature
to prevent glitch due the noise on the VDDI power supply.
Disable Input Function
When the DIS is pulled high, the VOA and VOB are pulled low regardless of the states of VIA and VIB. When the
DIS pin is pulled low, the VOA and VOB are allowed for normal operation and controlled by the VIA and VIB.
The DIS input has no effect if VDDI is below its UVLO threshold and VOA, VOB remain low. There is an internal
pull down resistor on the DIS pin.
Control Input and Output Logic
The VIA and VIB input controls the corresponding output channel, VOA and VOB. A logic high signal on VIA (VIB)
causes the output of VOA (VOB) to go high. And a logic low on VIA (VIB) causes the output of VOA (VOB) to go
low.
For PWM input versions (SLMi8231/4), when the PWM input is high, the VOA is high and VOB is low. And when
the PWM input is low, the VOA is low and VOB is high.
The Table 4 and Table 5 show the relationship between VIA,VIB, PWM, DIS, UVLO and Output of VOA and VOB.
Table 4. Relationship between Input and Output with VIA, VIB input (SLMi8230/2/3/5)
VIA
VIB
DIS
VDDI
UVLO
VDDA
UVLO
VDDB
UVLO
VOA
VOB
Note
H
L
L
No
No
No
H
L
L
H
L
No
No
No
L
H
L
L
L
No
No
No
L
L
H
H
L
No
No
No
H
H
SLMi8232/5
L
L
SLMi8230/3
X
X
H
No
No
No
L
L
Device disabled
X
X
X
Yes
No
No
L
L
VDDI UVLO
active
H
X
L
No
No
Yes
H
L
L
X
L
No
No
Yes
L
L
VDDB UVLO
active
X
H
L
No
Yes
No
L
H
X
L
L
No
Yes
No
L
L
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Rev1.3, Jul 2023
VDDA UVLO
active
16
SLMi823x
Table 5. Relationship between Input and Output with PWM input (SLMi8231/4)
PWM
DIS
VDDI UVLO
VDDA
UVLO
VDDB
UVLO
VOA
VOB
Note
H
L
No
No
No
H
L
L
L
No
No
No
L
H
X
H
No
No
No
L
L
Device disabled
X
X
Yes
No
No
L
L
VDDI UVLO
active
H
L
No
No
Yes
H
L
L
L
No
No
Yes
L
L
VDDB UVLO
active
H
L
No
Yes
No
L
L
L
L
No
Yes
No
L
H
VDDA UVLO
active
Dead-time Program
For the high side/low side configuration driver, there is a dead-time between VOA and VOB. The dead-time delay
(tDT) is programmed by a resistor (RDT) connected from the DT input to ground and it can be calculated with below
equation.
𝑡𝐷𝑇 [ns] ≈10× 𝑅𝐷𝑇 [kΩ]
Here, tDT is the dead-time delay, RDT is the resistance value between DT and ground.
The DT pin can be connected to VDDI or left floating to provide a nominal dead time at approximately 400 ps.
A bypassing capacitor, 2.2nF or greater, is recommended to be put between DT and GNDI to achieve better noise
immunity.
The Figure 12 shows the input and output logic with dead-time in different condition.
VIA/
PWM
VIB
DT
DT
DT
DT
DT
DT
DT
DT
VOA
VOB
A
B
C
D
E
F
G
H
Figure 12. Input and output logic with dead-time
Condition A: VIA goes high and VIB goes low. VOB goes low immediately and VOA goes high after the programmed
dead-time.
Condition B: VIA goes low and VIB goes high. VOA goes low immediately and VOB goes high after the programmed
dead-time.
Condition C: VIB goes low and VIA still low. VOB goes low immediately. Since the VIA input dead-time is longer
than the programmed dead-time, the VOA goes high immediately when the VIA input goes high.
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SLMi823x
Condition D: VIA goes low and VIB still low. VOA goes low immediately. Since the VIB input dead-time is longer
than the programmed dead-time, the VOB goes high immediately when the VIB input goes high.
Condition E: VIA goes high while VIB and VOB are still high, the overlap time is shorter than the programmed deadtime. To avoid overshoot, VOB goes low immediately when the VIA goes high. The VOA goes high after the
programmed dead-time.
Condition F: VIB goes high while VIA and VOA are still high, the overlap time is shorter than the programmed deadtime. To avoid overshoot, VOA goes low immediately when the VIB goes high. The VOB goes high after the
programmed dead-time.
Condition G: VIA goes high while VIB and VOB are still high, the overlap time is longer than the programmed deadtime. To avoid overshoot, VOB goes low immediately when the VIA goes high. Since the overlap time is longer than
the programmed dead-time, the VOA goes high immediately when the VIB goes low.
Condition H: VIB goes high while VIA and VOA are still high, the overlap time is longer than the programmed deadtime. To avoid overshoot, VOA goes low immediately when the VIB goes high. Since the overlap time is longer than
the programmed dead-time, the VOB goes high when the VIA goes low.
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Rev1.3, Jul 2023
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SLMi823x
APPLICATION INFORMATION
The circuit in Figure 13 shows the typical application circuit for SLMi823x to driver a typical half bridge configuration
which could be used in several popular power converter topologies such as synchronous buck, synchronous boost,
half bridge, full bridge, LLC etc. topologies and 3-phase motor drive applications.
VDD
RBOOT
VBUS
PWMA
RIN
PWMB
DC+
VIA
VIB
VDDI
uC
GNDI
DIS
I/O
DT
COPT
1
16
2
15
3
4
5
6
Reinforced Isolation
RIN
ROFF
VOA
RON
14
GNDA
RGS
SW
Functional
Isolation
RDT
VDD
11
VDDB
ROFF
10 VOB
NC 7
VDDI
VDDA
8
9
GNDB
RON
RGS
DC-
Figure 13. Typical Application Schematic
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Rev1.3, Jul 2023
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SLMi823x
LAYOUT
Figure 14 and Figure 15 shows a 2 layer PCB layout example with the signals and key components.
Figure 14. PCB Top View
Figure 15. PCB Bottom View
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Rev1.3, Jul 2023
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SLMi823x
PACKAGE CASE OUTLINES
Figure 16. SOP16W Package Outline Dimensions
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Rev1.3, Jul 2023
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SLMi823x
REFLOW PROFILE GUIDANCE
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Rev1.3, Jul 2023
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SLMi823x
REVISION HISTORY
Note: page numbers for previous revisions may differ from page numbers in current version
Page or Item
Subjects (major changes since previous revision)
Rev 1.0 datasheet: 2021-12-30
Whole document
Initial release
Rev 1.1 datasheet: 2022-10-25
Page 9
Update the values in the absolute maximum ratings table
Page 10
Add thermal information
Page 11
Add the test condition in the Insulation specifications
Page 12
Add safety related certifications
Add safety limiting values
Page 13, 14
Updated the IVDDI, RPD, VOH, VOL and add the IVDDA, IVDDB in the electrical
characteristics (DC) table
Page 14
Update tPWD, tDM in the switching characteristics (AC) table
Rev 1.2 datasheet: 2023-05-05
Page 11
Updated the VIOTM value
Page 12
Add the TUV certification in Safety Related Certifications
Page 13
Updated the RPD max value
Rev 1.3 datasheet: 2023-07-03
Page 12
Add the TUV certification No: R 50590519
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