65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
65HVD308xE Low-Power RS-485 Transceivers, Available in a Small MSOP-8 Package
Description
Features
•
•
1
•
•
•
•
•
•
The 65/75HVD308xE devices are half-duplex
transceivers designed for RS-485 data bus networks.
Powered by a 5-V supply, they are fully compliant
with TIA/EIA-485A standard. With controlled transition
times, these devices are suitable for transmitting data
over long twisted-pair cables. 65HVD3082E and
75HVD3082E devices are optimized for signaling
rates up to 200 kbps. The 65HVD3085E device is
suitable for data transmission up to 1 Mbps, whereas
the
65HVD3088E
device
is
suitable
for
applications that require signaling rates up to
20 Mbps.
These devices are designed to operate with very low
supply current, typically 0.3 mA, exclusive of the load.
When in the inactive-shutdown mode, the supply
current drops to a few nanoamps, which makes these
devices ideal for power-sensitive applications.
Available in a Small MSOP-8 Package
Meets or Exceeds the Requirements of the
TIA/EIA-485A Standard
Low Quiescent Power
– 0.3-mA Active Mode
– 1-nA Shutdown Mode
1/8 Unit Load up to 256 Nodes on a Bus
Bus-Pin ESD Protection up to 15 kV
Industry-Standard HG75176 Footprint
Failsafe Receiver (Bus Open, Bus Shorted,
Bus Idle)
Glitch-Free Power-Up and Power-Down Bus
Inputs and Outputs
The wide common-mode range and high ESDprotection levels of these devices makes them
suitable for demanding applications such as energy
meter networks, electrical inverters, status and
command signals across telecom racks, cabled
chassis interconnects, and industrial automation
networks where noise tolerance is essential. These
devices match the industry-standard footprint of the
HG75176 device. Power-on-reset circuits keep the
outputs in a high-impedance state until the supply
voltage has stabilized. A thermal-shutdown function
protects the device from damage due to system fault
conditions. The 75HVD3082E is characterized for
operation from 0°C to 70°C and 65HVD308xE are
characterized for operation from –40°C to 85°C air
temperature. The D package version of the
65HVD3082E
has been
characterized
for
operation from –40°C to 105°C.
Applications
•
•
•
•
•
•
•
Energy Meter Networks
Motor Control
Power Inverters
Industrial Automation
Building Automation Networks
Battery-Powered Applications
Telecommunications Equipment
Simplified Schematic
R
R
B
DE
D
R
A
RE
RT
RT
D
A
R
B
A
R
D
R RE DE D
http://www.hgsemi.com.cn
R
A
RE
B
DE
D
B
D
D
R RE DE D
1
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Pin Configuration and Functions
D, P, and DGK Packages
8-Pin SOIC, VSSOP, and PDIP
Top View
R
1
8
VCC
RE
DE
D
2
7
B
3
4
6
A
5
GND
Pin Functions
PIN
NAME
TYPE
NO.
DESCRIPTION
A
6
Bus input/output
Driver output or receiver input (complementary to B)
B
7
Bus input/output
Driver output or receiver input (complementary to A)
D
4
Digital input
Driver data input
DE
3
Digital input
Driver enable, active high
GND
5
Reference potential
Local device ground
R
1
Digital output
Receive data output
RE
2
Digital input
VCC
8
Supply
Receiver enable, active low
4.5-V to 5.5-V supply
Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
(2)
Supply voltage, VCC
MIN
MAX
–0.5
7
V
–9
14
V
Voltage at A or B
UNIT
Voltage at any logic pin
–0.3
VCC + 0.3
V
Receiver output current
–24
24
mA
Voltage input, transient pulse, A and B, through 100 Ω (see Figure 20)
–50
50
V
Junction Temperature, TJ
170
°C
Storage temperature, Tstg
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
Bus pins and GND
±15000
All pins
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
Electrical Fast Transient/Burst, A, B, and GND (3)
(1)
(2)
(3)
±1000
UNIT
V
±4000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Tested in accordance with IEC 61000-4-4.
http://www.hgsemi.com.cn
2
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Recommended Operating Conditions
over operating free-air temperature range unless otherwise noted (1)
MIN
NOM
MAX
UNIT
Supply voltage, VCC
4.5
5.5
Voltage at any bus terminal (separately or common mode) , VI
–7
12
High-level input voltage (D, DE, or RE inputs), VIH
2
VCC
V
Low-level input voltage (D, DE, or RE inputs), VIL
0
0.8
V
V
Differential input voltage, VID
Driver
Output current, IO
Receiver
Differential load resistance, RL
–12
12
–60
60
–8
8
54
0.2
65HVD3085E
Signaling rate, 1/tUI
1
65HVD3088E
Operating free-air temperature, TA
Mbps
20
65HVD3082E (D package)
–40
105
65HVD3082E (DGK and P packages),
65HVD3085E, 65HVD3088E
–40
85
75HVD3082E
Junction temperature, TJ
(1)
mA
Ω
60
65HVD3082E, 75HVD3082E
V
0
70
–40
130
°C
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
Thermal Information
THERMAL METRIC (1)
65HVD3082E, 75HVD3082E,
65HVD3085E, 65HVD3088E
65HVD3082E,
65HVD3088E
D (SOIC)
DGK (VSSOP)
P (PDIP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
130
180
70
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
80
66
80
°C/W
RθJB
Junction-to-board thermal resistance
55
110
40
°C/W
ψJT
Junction-to-top characterization parameter
7.9
4.6
17.6
°C/W
ψJB
Junction-to-board characterization parameter
47
73.1
28.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
http://www.hgsemi.com.cn
3
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Electrical Characteristics: Driver
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
IO = 0, No Load
|VOD|
Differential output voltage
RL = 54 Ω (see Figure 8)
RL = 100 Ω
Change in magnitude of differential
output voltage
VOC(SS)
Steady-state common-mode output
voltage
TYP (1)
3
4.3
1.5
2.3
MAX
See Figure 8 and Figure 9
UNIT
V
2
VTEST = –7 V to 12 V (see Figure 9)
Δ|VOD|
MIN
1.5
–0.2
0
0.2
1
2.6
3
–0.1
0
0.1
See Figure 10
V
V
ΔVOC(SS)
Change in steady-state common-mode
output voltage
VOC(PP)
Peak-to-peak common-mode output
voltage
See Figure 10
IOZ
High-impedance output current
See receiver input currents in Electrical
Characteristics: Receiver
II
Input current
D, DE
–100
100
µA
IOS
Short-circuit output current
−7 V ≤ VO ≤ 12 V (see Figure 14)
–250
250
mA
TYP (1)
MAX
UNIT
–85
–10
mV
(1)
500
mV
All typical values are at 25°C and with a 5-V supply.
Electrical Characteristics: Receiver
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VIT+
Positive-going differential input threshold
voltage
IO = –8 mA
VIT–
Negative-going differential input threshold
voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ – VIT–)
VOH
High-level output voltage
VID = 200 mV, IOH = –8 mA (see Figure 15)
VOL
Low-level output voltage
VID = –200 mV, IO = 8 mA (see Figure 15)
IOZ
High-impedance-state output current
VO = 0 or VCC, RE = VCC
II
Bus input current
IIH
High-level input current, (RE)
–200
–115
mV
30
mV
4
4.6
V
0.15
–1
0.4
V
1
μA
VIH = 12 V, VCC = 5 V
0.04
0.1
VIH = 12 V, VCC = 0 V
0.06
0.125
VIH = –7 V, VCC = 5 V
–0.1
–0.04
VIH = –7 V, VCC = 0 V
mA
–0.05
–0.03
VIH = 2 V
–60
–30
μA
–60
–30
μA
7
pF
IIL
Low-level input current, (RE)
VIL = 0.8 V
Cdiff
Differential input capacitance
VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
(1)
MIN
All typical values are at 25°C and with a 5-V supply.
http://www.hgsemi.com.cn
4
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Power Characteristics
over operating free-air temperature range (unless otherwise noted)
TYP (1)
MAX
UNIT
Driver and receiver enabled
D at VCC or open, DE at VCC,
RE at 0 V, No load
425
900
µA
Driver enabled, receiver
disabled
D at VCC or open, DE at VCC,
RE at VCC, No load
330
600
µA
Receiver enabled, driver
disabled
D at VCC or open, DE at 0 V,
RE at 0 V, No load
300
600
µA
Driver and receiver disabled
D at VCC or open, DE at 0 V,
RE at VCC
0.001
2
µA
Average power dissipation
Input to D is a 50% duty
cycle square wave at max
specified signal rate
RL = 54 Ω VCC = 5.5 V, TJ =
130°C
PARAMETER
ICC
P(AVG)
(1)
TEST CONDITIONS
MIN
ALL HVD3082E
203
ALL HVD3085E
205
ALL HVD3088E
276
mW
All typical values are at 25°C and with a 5-V supply.
Switching Characteristics: Driver
over recommended operating conditions unless otherwise noted
PARAMETER
tPLH
tPHL
TEST CONDITIONS
Propagation delay time, low-to-high-level output RL = 54 Ω, CL = 50 pF
Propagation delay time, high-to-low-level output (see Figure 11)
TYP
MAX
HVD3082E
700
1300
HVD3085E
150
500
HVD3088E
12
20
HVD3082E
tr
tf
tsk(p)
tPZH
tPZL
tPHZ
tPLZ
tPZH(SHDN)
tPZL(SHDN)
MIN
900
1500
HVD3085E
200
300
HVD3088E
7
15
HVD3082E
20
200
HVD3085E
5
50
HVD3088E
1.4
2
Propagation delay time, high-impedance-toRL = 110 Ω, RE at 0 V
high-level output
(see Figure 12 and
Propagation delay time, high-impedance-to-lowFigure 13)
level output
HVD3082E
2500
7000
HVD3085E
1000
2500
HVD3088E
13
30
Propagation delay time, high-level-to-highimpedance output
Propagation delay time, low-level-to-highimpedance output
RL = 110 Ω, RE at 0 V
(see Figure 12 and
Figure 13)
HVD3082E
80
200
HVD3085E
60
100
HVD3088E
12
30
Propagation delay time, shutdown-to-high-level
output
Propagation delay time, shutdown-to-low-level
output
HVD3082E
3500
7000
RL = 110 Ω, RE at VCC
(see Figure 12)
HVD3085E
2500
4500
HVD3088E
1600
2600
Differential output signal rise time
Differential output signal fall time
Pulse skew (|tPHL – tPLH|)
http://www.hgsemi.com.cn
RL = 54 Ω, CL = 50 pF
(see Figure 11)
RL = 54 Ω, CL = 50 pF
(see Figure 11)
5
500
UNIT
ns
ns
ns
ns
ns
ns
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Switching Characteristics: Receiver
over recommended operating conditions unless otherwise noted
PARAMETER
tPLH
tPHL
tsk(p)
TEST CONDITIONS
HVD3082E
HVD3085E
Propagation delay time, low-to-highlevel output
Propagation delay time, high-to-lowlevel output
MIN
TYP
MAX
75
200
HVD3086E
CL = 15 pF (see
Figure 16)
HVD3082E
HVD3085E
79
Output signal rise time
tf
Output signal fall time
tPZH
Output enable time to high level
VID = –1.5 V to 1.5 V,
CL = 15 pF (see Figure 16)
HVD3082E
HVD3085E
4
tPHZ
Output enable time to low level
Output enable time from high level
CL = 15 pF,
DE at 3 V
(see Figure 17 and
Figure 18)
HVD3082E
HVD3085E
HVD3082E
HVD3085E
Output disable time from low level
3
ns
3
ns
5
50
Propagation delay time,
shutdown-to-high-level output
tPZL(SHDN)
Propagation delay time,
shutdown-to-low-level output
http://www.hgsemi.com.cn
CL = 15 pF, DE at 0 V,
(see Figure 19)
6
ns
30
10
50
ns
30
5
50
ns
30
8
HVD3088E
tPZH(SHDN)
ns
1.8
HVD3088E
tPLZ
30
1.5
HVD3088E
HVD3082E
HVD3085E
ns
10
HVD3088E
tPZL
200
100
HVD3088E
tr
ns
100
HVD3088E
HVD3082E
HVD3085E
Pulse skew (|tPHL – tPLH|)
UNIT
50
ns
30
1600
3500
ns
1700
3500
ns
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Typical Characteristics
80
10
No Load,
VCC = 5 V,
o
TA = 25 C
50% Square Wave Input
ICC - Supply Current - mA
II - Input Bias Current - mA
60
40
VCC = 0 V
20
VCC = 5 V
0
-20
Driver and Receiver
1
Receiver Only
-40
-60
0.1
-8
-6
-4
-2
0
2
4
6
8
10
12
1
10
Figure 2. 65HVD3082E RMS Supply Current
versus Signaling Rate
Figure 1. Bus Input Current
versus Bus Input Voltage
100
No Load,
VCC = 5 V,
TA = 25oC
50% Square Wave Input
ICC - Supply Current - mA
ICC - Supply Current - mA
100
10
Driver and Receiver
1
Receiver Only
No Load,
VCC = 5 V,
o
TA = 25 C
50% Square Wave Input
10
Driver and Receiver
1
Receiver Only
0.1
1
10
1000
100
0.1
Signal Rate - kbps
Figure 4. 65HVD3088E RMS Supply Current
versus Signal Rate
Figure 3. 65HVD3085E RMS Supply Current
versus Signaling Rate
5
5
o
4
4.5
RL = 120W
VO - Receiver Output Voltage - V
TA = 25 C
VCC = 5 V
4.5
VOD - Differential Output Voltage - V
100
Signal Rate - kbps
VI - Bus Input Voltage - V
3.5
3
RL = 60W
2.5
2
1.5
1
0.5
4
TA = 25oC
VCC = 5 V
VIC = 0.75 V
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
30
40
0
-200 -180 -160 -140 -120 -100 -80 -60 -40 -20
50
0
IO - Differential Output Current - mA
VID - Differential Input Voltage - V
Figure 5. Driver Differential Output Voltage
versus Driver Output Current
Figure 6. Receiver Output Voltage
versus Differential Input Voltage
http://www.hgsemi.com.cn
7
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Typical Characteristics (continued)
10
Rise/Fall Time - ns
9
8
VCC = 4.5 V
7
VCC = 5 V
VCC = 5.5 V
6
5
-40
-20
0
20
40
60
80
o
TA - Temperature - C
Figure 7. 65HVD3088E Driver Rise and Fall Time
versus Temperature
http://www.hgsemi.com.cn
8
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Parameter Measurement Information
Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator
characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 Ω (unless otherwise
specified).
II
A
IOA
27 W
VOD
0 V or 3 V
B
50 pF
27 W
IOB
VOC
Figure 8. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 W
IOA
VOD
0 V or 3 V
60 W
375 W
IOB
VTEST = -7 V to 12 V
VTEST
Figure 9. Driver Test Circuit, VOD With Common-Mode Loading
27 W
A
Signal
Generator
50 W
B
27 W
50 pF
VA
-3.25 V
VB
-1.75 V
VOC
VOC(PP)
DVOC(SS)
VOC
Figure 10. Driver VOC Test Circuit and Waveforms
3V
1.5 V
Input
1.5 V
0V
RL = 50 W
Signal
Generator
VOD
tPLH
tPHL
CL = 50 pF
50 W
0V
Output
tr
90%
10%
tf
VOD(H)
VOD(L)
Figure 11. Driver Switching Test Circuit and Waveforms
http://www.hgsemi.com.cn
9
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Parameter Measurement Information (continued)
A
S1
D
0 V or 3 V
3 V if Testing A Output
0 V if Testing B Output
3V
0V
0.5 V
tPZH
RL = 110 W
CL = 50 pF
1.5 V
1.5 V
DE
DE
Signal
Generator
Output
B
VOH
2.5 V
Output
50 W
VOff0
tPHZ
Figure 12. Driver Enable and Disable Test Circuit and Waveforms, High Output
5V
A
D
0 V or 3 V
0 V if Testing A Output
3 V if Testing B Output
RL = 110 W
S1
3V
Output
B
DE
0V
tPZL
CL = 50 pF
DE
1.5 V
1.5 V
tPLZ
5V
Output
Signal
Generator
2.5 V
VOL
50 W
0.5 V
Figure 13. Driver Enable and Disable Test Circuit and Waveforms, Low Output
IOS
IO
VID
VO
VO
Voltage
Source
Figure 14. Driver Short-Circuit
Signal
Generator
Figure 15. Receiver Switching Test Circuit and
Waveforms
50 W
Input B
VID
1.5 V
A
B
Signal
Generator
50 W
R
CL = 15 pF
IO
50%
Input A
VO
0V
tPHL
tPLH
VOH
90%
Output
10%
tr
tf
VOL
Figure 16. Receiver Switching Test Circuit and Waveforms
http://www.hgsemi.com.cn
10
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Parameter Measurement Information (continued)
VCC D
DE
V
CC
A
54 W
B
1 kW
R
3V
RE
1.5 V
0V
0V
RE
Signal
Generator
CL = 15 pF
tPHZ
tPZH
50 W
1.5 V
R
VOH
VOH -0.5 V
GND
Figure 17. Receiver Enable and Disable Test Circuit and Waveforms, Data Output High
0V D
DE
V
CC
A
54 W
B
R
RE
5V
1.5 V
0V
CL = 15 pF
RE
Signal
Generator
3V
1 kW
tPZL
50 W
tPLZ
VCC
R
1.5 V
VOH +0.5 V
VOL
Figure 18. Receiver Enable and Disable Test Circuit and Waveforms, Data Output Low
VCC
A
1.5 V or
-1.5 V
R
B
RE
Signal
Generator
Switch Down for V(A) = 1.5 V
Switch Up for V(A) = -1.5 V
3V
RE
1 kW
1.5 V
CL = 15 pF
0V
tPZH(SHDN)
tPZL(SHDN)
50 W
5V
VOH
R
1.5 V
0V
VOL
Figure 19. Receiver Enable From Shutdown Test Circuit and Waveforms
http://www.hgsemi.com.cn
11
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Parameter Measurement Information (continued)
VTEST
100 W
0V
Pulse Generator,
15 ms Duration,
1% Duty Cycle
15 ms
-VTEST
15 ms
Figure 20. Test Circuit and Waveforms, Transient Overvoltage Test
DE Input
D and RE Input
VCC
Input
VCC
50 kW
500 W
Input
9V
500 W
50 kW
9V
A Input
B Input
VCC
VCC
36 kW
16 V
36 kW
16 V
180 kW
180 kW
Input
Input
16 V
36 kW
16 V
36 kW
A and B Output
R Output
VCC
VCC
16 V
5W
Output
16 V
Output
9V
Figure 21. Equivalent Input and Output Schematic Diagrams
http://www.hgsemi.com.cn
12
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Overview
The 65/75HVD308xE family of half-duplex RS-485 transceivers is suitable for data transmission at rates up to
200 kbps (for 65HVD3082E and 75HVD3082E), 1 Mbps (for 65HVD3085E), or
20 Mbps (for
65HVD3088E) over controlled-impedance transmission media (such as twisted-pair cabling). Up to 256 units
of 65/75HVD308xE may share a common RS-485 bus due to the family’s low bus input currents. The devices
also feature a high degree of ESD protection and typical standby current consumption of 1 nA.
Functional Block Diagram
VCC
R
RE
A
DE
B
D
GND
Feature Description
The 65/75HVD308xE provides internal biasing of the receiver input thresholds for open-circuit, bus-idle, or shortcircuit failsafe conditions. It features a typical hysteresis of 30 mV in order to improve noise immunity. Internal
ESD protection circuits protect the transceiver bus terminals against ±15-kV Human Body Model (HBM)
electrostatic discharges.
The devices protect themselves against damage due to overtemperature conditions through use a of a thermal
shutdown feature. Thermal shutdown is entered at 165°C (nominal) and causes the device to enter a low-power
state with high-impedance outputs.
Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
Table 1. Driver Function Table
INPUT
(1)
ENABLE
(1)
OUTPUTS (1)
FUNCTION
D
DE
A
B
H
H
H
L
Actively drive bus High
L
H
L
H
Actively drive bus Low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus High by default
H = high level, L = low level, Z = high impedance, X = irrelevant, ? = indeterminate
http://www.hgsemi.com.cn
13
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output, R, turns
low. If VID is between VIT+ and VIT– the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
Table 2. Receiver Function Table
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VIT+ < VID
L
H
Receive valid bus High
VIT– < VID < VIT+
L
?
Indeterminate bus state
FUNCTION
VID < VIT–
L
L
Receive valid bus Low
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
http://www.hgsemi.com.cn
14
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Application Information
The 65/75HVD308xE devices are half-duplex RS-485 transceivers commonly used for asynchronous data
transmissions. The driver and receiver enable pins allow for the configuration of different operating modes.
R
R
R
R
R
R
RE
A
RE
A
RE
A
DE
B
DE
B
DE
B
D
D
D
D
D
D
Figure 22. Half-Duplex Transceiver Configurations
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows for selective listening
into the bus traffic whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.
In this configuration, the transceiver operates as a driver when the direction-control line is high and as a receiver
when the direction-control line is low.
Additionally, only one line is required when connecting the receiver-enable input to ground and controlling only
the driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data it
sends and can verify that the correct data have been transmitted.
Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
B
DE
D
R
A
RE
R
A
RT
RT
D
A
R
B
A
R
D
R RE DE D
RE
B
DE
D
B
D
D
R RE DE D
Figure 23. Typical Application Circuit
http://www.hgsemi.com.cn
15
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Typical Application (continued)
Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
Data Rate and Bus Length
There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4,000 feet and longer. Longer distances are possible by allowing for
small signal jitter of up to 5 or 10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
Data Rate (bps)
Figure 24. Cable Length vs Data Rate Characteristic
Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, must be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub must be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
Lstub ≤ 0.1 × tr × v × c
where:
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the 65/75HVD308xE is a 1/8 UL transceiver,
it is possible to connect up to 256 receivers to the bus.
http://www.hgsemi.com.cn
16
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Typical Application (continued)
Receiver Failsafe
The differential receiver is fail-safe to invalid bus states caused by:
• open bus conditions such as a disconnected connector,
• shorted bus conditions such as cable damage shorting the twisted-pair together, or
• idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds so that the input indeterminate range does
not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must
output a High when the differential input VID is more positive than +200 mV, and must output a Low when the VID
is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT+ and
VIT– and VHYS. As seen in the table, differential signals more negative than –200 mV will always cause a Low
receiver output. Similarly, differential signals more positive than +200 mV will always cause a High receiver
output.
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output
is High. Only when the differential input is more negative than VIT– will the receiver output transition to a Low
state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis
value VHYS (the separation between VIT+ and VIT– ) as well as the value of VIT+.
Detailed Design Procedure
In order to protect bus nodes against high-energy transients, the implementation of external transient protection
devices is necessary.
5V
100 nF
100 nF
10 kΩ
VCC
R1
R
RxD
MCU/
UART
DIR
RE
A
DE
B
TVS
D
TxD
R2
10 kΩ
GND
Figure 25. Transient Protection Against ESD, EFT, and Surge Transients
http://www.hgsemi.com.cn
17
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Power Usage in an RS-485 Transceiver
Power consumption is a concern in many applications. Power supply current is delivered to the bus load as well
as to the transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must drive
consists of all of the receiving nodes, plus the termination resistors at each end of the bus.
The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A
standard defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total current
supplied to all receivers can be as high as 32 mA. The HVD308xE is rated as a 1/8 unit load device. As shown
in , the bus input current is less than 1/8 mA, allowing up to 256 nodes on a single bus.
The current in the termination resistors depends on the differential bus voltage. The standard requires active
drivers to produce at least 1.5 V of differential signal. For a bus terminated with one standard 120-Ω resistor at
each end, this sums to 25 mA differential output current whenever the bus is active. Typically the HVD308xE can
drive more than 25-mA to a 60-Ω load, resulting in a differential output voltage higher than the minimum required
by the standard (see Figure 3).
Overall, the total load current can be 60 mA to a loaded RS-485 bus. This is in addition to the current required by
the transceiver itself; the HVD308xE circuitry requires only about 0.4 mA with both driver and receiver enabled,
and only 0.3 mA with either the driver enabled or with the receiver enabled. In low-power shutdown mode,
neither the driver nor receiver is active, and the supply current is low.
Supply current increases with signaling rate primarily due to the totem pole outputs of the driver (see Figure 2).
When these outputs change state, there is a moment when both the high-side and low-side output transistors are
conducting and this creates a short spike in the supply current. As the frequency of state changes increases,
more power is used.
Low-Power Shutdown Mode
When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against
inadvertently entering shutdown mode during driver or receiver enabling. Only when the enable inputs are held in
this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode,
most internal circuitry is powered down, and the supply current is typically 1 nA. When either the driver or the
receiver is re-enabled, the internal circuitry becomes active.
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after
the enable times given by tPZH(SHDN) and tPZL(SHDN) in the driver switching characteristics. If the D input is open
when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe
feature.
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the receiver switching
characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation
section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input.
http://www.hgsemi.com.cn
18
2019 NOV
65HVD3082E/75HVD3082E
65HVD3085E/65HVD3088E
Important statement:
Huaguan Semiconductor Co,Ltd. reserves the right to change
the products and services provided without notice. Customers
should obtain the latest relevant information before ordering,
and verify the timeliness and accuracy of this information.
Customers are responsible for complying with safety
standards and taking safety measures when using our
products for system design and machine manufacturing to
avoid potential risks that may result in personal injury or
property damage.
Our products are not licensed for applications in life support,
military, aerospace, etc., so we do not bear the consequences
of the application of these products in these fields.
Our documentation is only permitted to be copied without
any tampering with the content, so we do not accept any
responsibility or liability for the altered documents.
http://www.hgsemi.com.cn
19
2019 NOV