ES7148

ES7148 12-pin, 24-Bit Stereo D/A Converter for PCM Audio GENERAL DESCRIPTION FEATURES The ES7148 is a low cost 12-pin stereo digital to analog converter. The ES7148 can accept I²S serial audio data format up to 24-bit word length. The device uses advanced multi-bit ∆-∑ modulation technique to convert data into two channel analog outputs. The multi-bit ∆-∑ modulator makes the device with very low sensitivity to clock jitter and very low out of band noise.       100 dB SNR -85 dB THD+N Up to 100 kHz sampling frequency Support USB clocks or non standard audio clocks like 25 MHz or 26 MHz I2S audio data format, 16-24 bits Single power supply 3V to 3.6V APPLICATIONS      Digital Photo Frame Set top box Digital TV DVD player Audio player ORDERING INFORMATION ES7148 -40°C ~ +85°C QFN-12 BLOCK DIAGRAM SDATA SCLK LRCK Audio Data Interface Clock Manager/ Sample Rate Detector Interpolation Filter Interpolation Filter Multi-level Sigma-delta DAC Output Amp Low Pass Filter AOUTLN Multi-level Sigma-delta DAC Output Amp Low Pass Filter AOUTRN CLKIN Rev 6.0 September 2018 1 Latest datasheet: http://www.everest-semi.com or info@everest-semi.com Everest Semiconductor ES7148 NC AOUTRN 12 11 10 9 VDD 2 8 GND 3 7 NC SCLK 1 LRCK CLKIN ES7148 4 5 6 CAP1 CAP2 AOUTLN I/O SDATA 1. PIN DESCRIPTIONS PIN PIN DESCRIPTION 1 SCLK I Bit clock input 2 LRCK I Left and right channel clock input indicating input data sampling rate (Fs) and channel selection 3 CLKIN I System clock input 4 CAP1 O Filtering capacitor 5 CAP2 O Filtering capacitor 6 AOUTLN O Analog output of left channel 7 NC I No connect 8 GND I Ground 9 VDD I Device power supply 10 AOUTRN O Analog output of right channel 11 NC I No connect 12 SDATA I Serial audio data input 2. RECOMMENDED APPLICATION CIRCUIT AGND 0R GND(SYS) VDD * AGND 9 8 In the layout, chip is treated as an analog device 1uF PGND 12 SDATA CPU/DSP 3 SCLK NC AOUTRN LRCK AOUTLN CLKIN NC CAP2 2 ES7148 CAP1 1 AGND VDD 13 GND AGND AGND 11 2200pF 10 3.3uF 6 3.3uF AOUTRN 470R AOUTLN 470R 7 2200pF AGND * 5 4 AGND 1uF 1uF * AGND For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible Additional parallel capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help * Rev 6.0 Figure 1 Recommended Application Circuit 2 September 2018 Latest datasheet: http://www.everest-semi.com or info@everest-semi.com Everest Semiconductor ES7148 3. APPLICATION DESCRIPTIONS Sampling Rate and Input Clocks According to the sampling rate, the device can work in two speed modes, single speed and double speed. Table 1 lists the typical clock modes supported by the device. The device supports USB clocks or non standard audio clocks like 25 MHz or 26 MHz. Table 1 Speed Mode and CLKIN/LRCK Ratio MODE Sampling Rate CLKIN/LRCK Ratio Single Speed 8kHz – 50kHz 32, 64, 128, 192, 256, 384, 512, 768, 1024 Double Speed 84kHz – 100kHz 128, 192, 256, 384, 512, 768, 1024 Audio Data Input The ES7148 can accept I²S serial audio input data from 16-bit to 24-bit. The device can detect the data word length automatically. The relationship of SDATA, SCLK and LRCK for the format is illustrated through Figures 2. 1 SCLK SDATA 1 2 1 SCLK 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LRCK LEFT CHANNEL RIGHT CHANNEL Figure 2 I²S serial audio data format up to 24-bit Power Up and Power Down Upon applying VDD, the device will reset itself and enter power down state. During this state, the device clamps outputs to ground and power down the device operation except for clock management unit. Once proper CLKIN and LRCK clocks are applied, the device will leave power down state, and the device outputs ramp from ground to common mode voltage softly. Then the device enters the normal operation. Rev 6.0 September 2018 3 Latest datasheet: http://www.everest-semi.com or info@everest-semi.com Everest Semiconductor ES7148 4. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings At or beyond this condition, operating continuously may cause permanent damage to the device. The performance and functions of the device are not guaranteed at these extremes. PARAMETER MIN MAX Supply Voltage Level -0.3V +5.0V Input Voltage Range GND-0.3V VDD+0.3V Operating Temperature Range -40°C +85°C Storage Temperature -65°C +150°C Recommended Operating Conditions PARAMETER MIN TYP MAX UNIT Supply Voltage Level 3 3.3 3.6 V Analog Characteristics Test conditions: VDD=3.3V, GND=0V, ambient temperature=25°C, Fs=48KHz, CLKIN/LRCK=256, input 0dB 1KHz sinewave PARAMETER MIN TYP 90 100 MAX UNIT DAC Performance Signal to Noise Ratio (Note 1) dB THD+N -85 Channel Separation (1KHz) 100 dB Dynamic Range 105 dB Interchannel Gain Mismatch 0 dB Frequency Response -0.02 -80 dB +0.08 dB 0.454 Fs (20Hz-20KHz) Filter Frequency Response characteristics Single Speed Passband 0 Stopband 0.547 ±0.05 Passband Ripple Stopband Attenuation Fs dB -53 dB Double Speed Passband 0 Stopband 0.583 Passband Ripple Rev 6.0 0.417 Fs Fs ±0.005 dB September 2018 4 Latest datasheet: http://www.everest-semi.com or info@everest-semi.com Everest Semiconductor Stopband Attenuation ES7148 -56 dB Quad Speed Passband 0 Stopband 0.792 Fs Fs ±0.006 Passband Ripple Stopband Attenuation 0.2083 -50 dB dB Analog Output Characteristics Full Scale Output Level 0.7*VDD Vpp Output Impedance 120 Ω Minimum Load Resistance 2 KΩ Maximum Capacitance 100 pF Note 1. A-weighted filter is used in measurement. Rev 6.0 September 2018 5 Latest datasheet: http://www.everest-semi.com or info@everest-semi.com Everest Semiconductor ES7148 Serial Audio Port Switching Characteristics PARAMETER SYMBOL MIN CLKIN Frequency CLKIN Duty Cycle 40 LRCK Frequency LRCK Duty Cycle 40 SCLK Frequency MAX UNIT 51.2 MHz 60 % 200 KHz 60 % 26 MHz SCLK Pulse Width Low TSCKL 15 ns SCLK Pulse Width High TSCKH 15 ns SCLK Rising to LRCK Edge Delay TLRH 10 ns SCLK Rising to LRCK Edge Setup Time TRSU 10 ns SDATA Valid to SCLK Rising Setup Time TSDS 10 ns SCLK Rising to SDATA Hold Time TSDH 10 ns TSDS TSDH SDATA TSCKL TSCKH SCLK TSCKY LRCK TLRH TLRSU Figure 3 Serial Audio Port Timing DC Characteristics PARAMETER MIN TYP MAX UNIT Normal Operation Mode VDD Current VDD=3.3V 15 mA 5 mA Power Down Mode VDD Current VDD=3.3V Digital Voltage Level Input High-level Voltage 1.65 V Input Low-level Voltage Rev 6.0 0.8 V Output High-level Voltage VDD V Output Low-level Voltage 0 V September 2018 6 Latest datasheet: http://www.everest-semi.com or info@everest-semi.com Everest Semiconductor ES7148 5. PACKAGE INFORMATION Rev 6.0 September 2018 7 Latest datasheet: http://www.everest-semi.com or info@everest-semi.com Everest Semiconductor Rev 6.0 ES7148 September 2018 8 Latest datasheet: http://www.everest-semi.com or info@everest-semi.com Everest Semiconductor ES7148 6. Contact Information: Everest Semiconductor Co., Ltd. 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com Rev 6.0 September 2018 9 Latest datasheet: http://www.everest-semi.com or info@everest-semi.com