NSi83085x/NSi83086x
High Reliability Isolated Half and
Full-Duplex RS-485 Transceivers
Datasheet (EN) 1.4
Product Overview
NSi83085x is a high reliability isolated half duplex RS-485
transceiver based on NOVOSENSE digital isolation
technology, while NSi83086x is an isolated full duplex RS485 transceiver. Both devices are safety certified by
UL1577 support 5kVrms insulation withstand voltages,
while providing high electromagnetic immunity and low
emissions at low power consumption.
The Bus pins of NSi83085x/NSi83086x are protected from
±10kV system level ESD to GND2 on Bus side. These
devices feature fail-safe circuitry, which guarantees a
logic-high receiver output when the receiver inputs are
open or shorted. The devices have a 1/8-unit-load receiver
input impedance that allows up to 256 transceivers on the
bus.
The data rate of NSi83085x is 500kbps. The device is slew
limited to reduce EMI and reflections with improperly
terminated transmission line. The data rate of NSi83086x
is up to 16Mbps.
Key Features
Up to 5000Vrms Insulation voltage
Bus side power supply voltage: 3.0V to 5.5V
Safety Regulatory Approvals
UL recognition: up to 5000Vrms for 1 minute per UL1577
CQC certification per GB4943.1-2011
CSA component notice 5A
DIN VDE V 0884-11:2017-01
Applications
Industrial automation system
Isolated RS-485 communication
Smart electric meter and water meter
Security and protection monitoring
Device Information
Part Number
NSI8308xA-DSWR
Package
SOW16
Body Size
10.30mm × 7.50mm
NSI8308x
SOW16
10.30mm × 7.50mm
VDD1 supply voltage: 2.5V to 5.5V
High CMTI: ±150kV/us
High system level EMC performance:
Functional Block Diagrams
Bus Pins meet IEC61000-4-2 ±10kV ESD
Fail-safe protection receiver
Up to 256 transceivers on the bus
Isolation Barrier Life: >60 years
Operation temperature: -40℃~105℃
RoHS-compliant packages:
SOW16
Copyright © 2020, NOVOSENSE
VDD1 1
GND1 2
R
3
16 VDD 2
VDD1 1
16 VDD2
15 GND2
GND1 2
15 GND2
14 NC
R
3
14 A
/RE 4
13 B
/RE 4
13 B
DE 5
12 A
DE 5
12 Z
D
6
11 NC
GND1 7
GND1 8
NSi83085
D
6
10 GND2
GND1 7
9 GND2
GND 1 8
11 Y
10 GND2
NSi83086
9 GND2
Figure 1. NSi83085x & NSi83086x Block Diagrams
Page 1
NSi83085x/NSi83086x
Datasheet (EN) 1.4
INDEX
1. ABSOLUTE MAXIMUM RATINGS ...................................................................................................................................... 3
2. SPECIFICATIONS ................................................................................................................................................................... 3
2.1. DC ELECTRICAL CHARACTERISTICS ...................................................................................................................................... 3
2.2. SWITCHING ELECTRICAL CHARACTERISTICS.......................................................................................................................... 5
2.3. TYPICAL PERFORMANCE CHARACTERISTICS ................................................................................................................. 7
2.4. PARAMETER MEASUREMENT INFORMATION ......................................................................................................................... 9
3. HIGH VOLTAGE FEATURE DESCRIPTION ....................................................................................................................10
3.1. INSULATION AND SAFETY RELATED SPECIFICATIONS .............................................................................................................10
3.2. DIN VDE V 0884-11（VDE V 0884-11）:2017-01 INSULATION CHARATERISTICS ............................................................ 11
3.3. REGULATORY INFORMATION.................................................................................................................................................12
4. FUNCTION DESCRIPTION .................................................................................................................................................12
4.1. DATA RATE ...........................................................................................................................................................................12
4.2. TRUE FAIL-SAFE RECEIVER INPUTS ......................................................................................................................................12
4.3. TRUTH TABLES .....................................................................................................................................................................12
4.4. THERMAL SHUTDOWN ..........................................................................................................................................................13
5. APPLICATION NOTE ............................................................................................................................................................13
5.1. 256 TRANSCEIVERS ON THE BUS ...........................................................................................................................................13
5.2. ESD PROTECTION.................................................................................................................................................................13
5.3. LAYOUT CONSIDERATIONS ...................................................................................................................................................14
5.4. TYPICAL APPLICATION ..........................................................................................................................................................14
6. PACKAGE INFORMATION .................................................................................................................................................15
7. TAPE AND REEL INFORMATION ......................................................................................................................................17
8. ORDER INFORMATION .......................................................................................................................................................19
9. REVISION HISTORY ............................................................................................................................................................19
Copyright © 2020, NOVOSENSE
Page 2
NSi83085x/NSi83086x
Datasheet (EN) 1.4
1. Absolute Maximum Ratings
Parameters
Symbol
Min
Power Supply Voltage
VDD1, VDD2
-0.5
6
V
Maximum Input Voltage
/RE, DE, TxD
-0.4
VDD+0.4
V
VA, VB, VY, VZ
-7
12
V
Differential input voltage,A
with repect to B
VID
-18
18
V
Receiver Output Current
Io
-15
15
mA
Maximum Surge Isolation
Voltage
VIOSM
4.62
kV
Operating Temperature
Topr
-40
105
℃
Storage Temperature
Tstg
-40
150
℃
HBM (Bus
pins and
GND)
±8000
V
HBM(All pins)
±6000
V
CDM
±2000
V
Driver Output/Receiver Input
Voltage
Electrostatic discharge
Typ
Max
Unit
Comments
2. Specifications
2.1. DC Electrical characteristics
(VDD1=2.5V~5.5V, VDD2=3.0V~5.5V, Ta=-40℃ to 105℃. Unless otherwise noted, Typical values are at VDD1 = 5V, VDD2 = 5V, Ta =
25℃)
Parameters
Symbol
Min
VDD1
VDD 2
Typ
Max
Unit
Comments
2.5
5.5
V
3.0
5.5
V
Bus Side
2.97
4.98
mA
VDD1=5V, DE=high, /RE=D
=low, no load
2.94
4.89
mA
VDD1=3V, DE=high, /RE=D
=low, no load
2.83
5.02
mA
VDD2=5V, DE=high, /RE=D
=low, no load（NSi83085x）
2.15
3.23
mA
VDD2=5V, DE=high, /RE=D
=low, no load（NSi83086x）
Power supply voltage
Logic-side supply current
Bus-side supply current
Thermal-Shutdown Threshold
Copyright © 2020, NOVOSENSE
IDD1
IDD2
TTS
165
℃
Page 3
NSi83085x/NSi83086x
Thermal-Shutdown Hysteresis
Common Mode Transient
Immunity
Datasheet (EN) 1.4
TTSH
℃
15
CMTI
±100
Input High Voltage
VIH
2
Input Low Voltage
VIL
±150
kV/us
Logic Side
0.8
V
DE, D, /RE
V
DE, D, /RE
VIT
1.6
V
Input Threshold at rising
edge
VIT_HYS
0.4
V
Input Threshold Hysteresis
uA
DE,/RE
Input Threshold
Input Pull up Current
IPU
20
Input Pull down Current
IPD
-20
uA
DI
Output Voltage High
VOH
VDD10.3
V
IOH = -4mA
Output Voltage Low
VOL
0.3
V
IOL = 4mA
Output Short-Circuit Current
IOSR
150
mA
0 ≤ VR ≤VDD1
Three-State Output Current
IOZ
uA
0 ≤ VR ≤ VDD1 , /RE = high
Input Capacitance
CIN
pF
DE, D, /RE
VDD2
V
No Load
2.7
VDD2
V
See Figure 2.4.1, RL=100Ω
(RS-422),VDD2=5V
1.5
VDD2
V
See Figure 2.4.1, RL=100Ω
(RS-422),VDD2=3.3V
2.1
VDD2
V
See Figure 2.4.1, RL=54Ω
(RS-485),VDD2=5V
1.3
VDD2
V
See Figure 2.4.1, RL=54Ω
(RS-485),VDD2=3.3V
0.2
V
See Figure 2.4.1, RL=100Ω or
RL=54Ω
V
See Figure 2.4.1, RL=100Ω or
RL=54Ω
0.2
V
See Figure 2.4.1, RL=100Ω or
RL=54Ω
250
mA
0 ≤ VOUT ≤ +12 V
mA
−7V ≤ VOUT ≤ VDD2
-15
2
Driver
Differential Output Voltage
Change in magnitude of the
| VOD |
Δ|VOD |
differential output voltage
Common-Mode Output
Voltage
| VOC |
Change in Magnitude of
Δ|VOC |
VDD2/2
Common-Mode Voltage
Driver Short-Circuit Output
Current
Copyright © 2020, NOVOSENSE
IOSD
-250
Page 4
NSi83085x/NSi83086x
Output Leakage Current (Y and
Z) Full-Duplex
Datasheet (EN) 1.4
200
uA
DE=GND, VIN=12V
uA
DE=GND, VIN=-7V
uA
DE=GND, VDD2=GND,
VIN=12V
uA
DE=GND, VDD2=GND, VIN=7V
mV
−7V ≤ VCM ≤ 12V
mV
VA+VB=0
kΩ
−7V ≤ VCM ≤ 12V, DE=low
IO
-150
Receiver
IA , I B
200
Input Current (A and B)
-150
Receiver Differential Threshold
Voltage
VTH
-200
Receiver Input Hysteresis
ΔVTH
Receiver Input Resistance
RIN
-125
-10
15
96
2.2. switching Electrical characteristics
(VDD1=2.5V~5.5V, VDD2=3.0V~5.5V, Ta=-40℃ to 105℃. Unless otherwise noted, Typical values are at VDD1 = 5V, VDD2 = 5V, Ta =
25℃)
Parameters
Symbol
Min
Typ
Max
Unit
Comments
Maximum Data Rate
fMAX
0.5
Driver Propagation Delay
t PLH
24.4
60
ns
See Figure 2.4.2，
RL=54Ω，CL=50pF
t PHL
24.2
60
ns
See Figure 2.4.2，
RL=54Ω，CL=50pF
PWD
0.2
ns
See Figure 2.4.2，
RL=54Ω，CL=50pF
tF
14.4
ns
See Figure 2.4.2，
RL=54Ω，CL=50pF
tR
14.4
ns
See Figure 2.4.2，
RL=54Ω，CL=50pF
Driver Enable to Output High
tZH
20.4
60
ns
See Figure 2.4.3，
RL=110Ω，CL=50pF
Driver Enable to Output Low
tZL
24.4
60
ns
See Figure 2.4.3，
RL=110Ω，CL=50pF
Driver Output High to Disable
tHZ
32.8
60
ns
See Figure 2.4.3，
RL=110Ω，CL=50pF
Driver Output Low to Disable
tLZ
28.6
60
ns
See Figure 2.4.3，
RL=110Ω，CL=50pF
Driver (NSi83085x)
Driver Pulse Width Distortion,|t
PHL – t PLH |
Driver Output Falling Time or
Rising time
Mbps
Receiver (NSi83085x)
Copyright © 2020, NOVOSENSE
Page 5
NSi83085x/NSi83086x
Datasheet (EN) 1.4
Maximum Data Rate
fMAX
0.5
Mbps
Receiver Propagation Delay
t PLH
75
153
ns
See Figure 2.4.4， CL=15pF
t PHL
74
138
ns
See Figure 2.4.4， CL=15pF
Receiver Pulse Width Distortion
PWD
1
ns
|t PHL – t PLH |,See Figure
2.4.4， CL=15pF
Receiver Output Falling Time or
Rising time
tF
2.5
5
ns
See Figure 2.4.4， CL=15pF
tR
2.5
5
ns
See Figure 2.4.4， CL=15pF
Receiver Enable to Output High
tZH
22
60
ns
See Figure 2.4.5，
RL=1kΩ，CL=15pF
Receiver Enable to Output Low
tZL
22
60
ns
See Figure 2.4.5，
RL=1kΩ，CL=15pF
Receiver Disable to Output High
tHZ
23
60
ns
See Figure 2.4.5，
RL=1kΩ，CL=15pF
Receiver Disable to Output Low
tLZ
23
60
ns
See Figure 2.4.5，
RL=1kΩ，CL=15pF
Driver (NSi83086x)
Maximum Data Rate
fMAX
Driver Propagation Delay
t PLH
15.2
25
ns
See Figure 2.4.2，
RL=54Ω，CL=50pF
t PHL
16.4
20.25
ns
See Figure 2.4.2，
RL=54Ω，CL=50pF
PWD
1.2
ns
See Figure 2.4.2，
RL=54Ω，CL=50pF
tF
7.4
15
ns
See Figure 2.4.2，
RL=54Ω，CL=50pF
tR
8.4
15
ns
See Figure 2.4.2，
RL=54Ω，CL=50pF
Driver Enable to Output High
tZH
15.4
30
ns
See Figure 2.4.3，
RL=110Ω，CL=50pF
Driver Enable to Output Low
tZL
15.4
30
ns
See Figure 2.4.3，
RL=110Ω，CL=50pF
Driver Disable to Output High
tHZ
28.2
50
ns
See Figure 2.4.3，
RL=110Ω，CL=50pF
Driver Disable to Output Low
tLZ
28.2
50
ns
See Figure 2.4.3，
RL=110Ω，CL=50pF
Driver Pulse Width Distortion,|t
PHL – t PLH |
Driver Output Falling Time or
Rising time
16
Mbps
Receiver (NSi83086x)
Maximum Data Rate
Copyright © 2020, NOVOSENSE
fMAX
16
Mbps
Page 6
NSi83085x/NSi83086x
Receiver Propagation Delay
Datasheet (EN) 1.4
t PLH
65
100
ns
See Figure 2.4.4， CL=15pF
t PHL
98
150
ns
See Figure 2.4.4， CL=15pF
Receiver Pulse Width Distortion,
|t PHL – t PLH |
PWD
33
ns
See Figure 2.4.4， CL=15pF
Receiver Output Falling Time or
Rising time
tF
2.3
5
ns
See Figure 2.4.4， CL=15pF
tR
2.1
5
ns
See Figure 2.4.4， CL=15pF
Receiver Enable to Output High
tZH
12
20.7
ns
See Figure 2.4.5，
RL=1kΩ，CL=15pF
Receiver Enable to Output Low
tZL
13
18.9
ns
See Figure 2.4.5，
RL=1kΩ，CL=15pF
Receiver Disable to Output High
tHZ
13.6
21
ns
See Figure 2.4.5，
RL=1kΩ，CL=15pF
Receiver Disable to Output Low
tLZ
14
20.1
ns
See Figure 2.4.5，
RL=1kΩ，CL=15pF
2.3. TYPICAL PERFORMANCE characteristics
Figure 2.1 NSi83085x VDD1 supply current vs Temperature
Copyright © 2020, NOVOSENSE
Figure 2.2 NSi83085x VDD2 supply current vs Temperature
Page 7
NSi83085x/NSi83086x
Figure 2.3 NSi83086x VDD1 supply current vs Temperature
Figure 2.5 Receiver output current vs Output low voltage
Figure 2.7 NSi83085x Transmitter Propagation Delay vs Temperature
Temperature
Figure 2.9 NSi83086x Transmitter Propagation Delay vs Temperature
Copyright © 2020, NOVOSENSE
Datasheet (EN) 1.4
Figure 2.4 NSi83086x VDD2 supply current vs Temperature
Figure 2.6 Receiver output current vs Output High voltage
Figure 2.8 NSi83085x Receiver Propagation Delay vs
Figure 2.10 NSi83086x Receiver Propagation Delay vs Temperature
Page 8
NSi83085x/NSi83086x
Datasheet (EN) 1.4
2.4. Parameter Measurement Information
Y
RL/2
VOD
RL/2 VOC
Z
Figure 2.4.1 Driver DC Test Load
Y
D
VOD
RL
CL
Z
Figure 2.4.2 Driver Timing Test Circuit and waveform
GND or
VDD1
Y
D
OUT
DE
Z
CL
VDD2
50ohm
Figure 2.4.3 Driver Enable Disable Timing Test Circuit and waveform
A
R
OUT
B
RE
15pF
Figure 2.4.4 Receiver Propagation Delay Test Circuit and waveform
Copyright © 2020, NOVOSENSE
Page 9
NSi83085x/NSi83086x
+1.5V
A
-1.5V
B
Datasheet (EN) 1.4
R
OUT
RE
15pF
VDD1
50ohm
Figure 2.4.5 Receiver Enable Disable Timing Test Circuit and waveform
GND1
VDD1 VDD2
R
VOUT
15pF
/RE
B
D
VDD1
0.8V
or 2V
A
DE
GND1
GND2
Figure 2.4.6 Common-Mode Transient Immunity Test Circuit
3. High Voltage Feature Description
3.1. insulation and safety related specifications
Parameters
Symbol
Value
Unit
Comments
Minimum External Air Gap
(Clearance)
L(I01)
8.0
mm
Shortest terminal-to-terminal
distance through air
Minimum External Tracking
(Creepage)
L(I02)
8.0
mm
Shortest terminal-to-terminal
distance across the package
surface
Minimum internal gap
DTI
20
um
Distance through insulation
Tracking Resistance(Comparative
Tracking Index)
CTI
>600
V
DIN EN 60112 (VDE 0303-11);
IEC 60112
Material Group
Copyright © 2020, NOVOSENSE
Ⅰ
Page 10
NSi83085x/NSi83086x
Datasheet (EN) 1.4
3.2. DIN VDE V 0884-11（VDE V 0884-11）:2017-01 insulation charateristics
Description
Test Condition
Symbol
Value
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150Vrms
Ⅰto Ⅳ
For Rated Mains Voltage ≤ 300Vrms
Ⅰto Ⅳ
For Rated Mains Voltage ≤ 400Vrms
Ⅰto Ⅳ
Climatic Classification
40/125/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum repetitive isolation voltage
Input to Output Test Voltage, Method B1
AC Voltage(Bipolar)
VIORM
1131
Vpeak
AC Voltage(TDDB)
VIORM
800
Vrms
DC Voltage
VIORM
1131
Vdc
V IORM × 1.5 = V pd (m) , 100%
production test,
V pd (m)
1749
Vpeak
t ini = t m = 1 sec, partial
discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
V IORM × 1.3 = V pd (m) , t ini = 60
sec, t m = 10 sec, partial
discharge < 5 pC
V pd (m)
1399
Vpeak
After Input and /or Safety Test Subgroup 2 and
Subgroup 3
V IORM × 1.2= V pd (m) , t ini = 60
sec, t m = 10 sec, partial
discharge < 5 pC
V pd (m)
1399
Vpeak
t = 60 sec
VIOTM
7000
Vpeak
Test method per
IEC60065,1.2/50us waveform,
VTEST=1.3×VIOSM
VIOSM
5384
Vpeak
Isolation resistance
VIO =500V
RIO
>109
Ω
Isolation capacitance
f = 1MHz
CIO
0.6
pF
Input capacitance
CI
2
pF
Total Power Dissipation at 25℃
Ps
1499
mW
237
mA
150
℃
Maximum transient isolation voltage
Maximum Surge Isolation Voltage
θJA = 84 °C/W, V I = 5.5 V, T J =
150 °C, T A = 25 °C
Case Temperature
Copyright © 2020, NOVOSENSE
Ts
Page 11
Saftey Limiting Current (mA)
NSi83085x/NSi83086x
Datasheet (EN) 1.4
250
200
150
100
50
0
0
50
100
150
200
Ambient Temperature (℃)
Figure 3.1 NSi83085x/NSi83086x Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE V 0884-11
3.3. Regulatory information
The NSi83085x/NSi83086x are approved or pending approval by the organizations listed in table.
CUL
VDE
UL 1577 Component
Recognition Program1
Single Protection, 5000Vrms
Isolation voltage
Approved under CSA
Component Acceptance
Notice 5A
DIN VDE V 0884-11(VDE V
0884-11):2017-012
Single Protection, 5000Vrms
Isolation voltage
Basic Insulation 1131Vpeak,
VIOSM=4615Vpeak
File (E500602)
File (5024579-4880-0001)
File (E500602)
1
CQC
Certified by CQC11471543-2012
GB4943.1-2011
Basic insulation
File (pending)
In accordance with UL 1577, each NSi83085x/NSi83086x is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec.
2
In accordance with DIN VDE V 0884-11, each NSi8100W/NSi8101W is proof tested by applying an insulation test voltage ≥ 1273 V peak for 1 sec (partial
discharge detection limit = 5 pC). The * marking branded on the component designates DIN VDE V 0884-11 approval.
4. Function Description
NSi83085x is a high reliability isolated half duplex RS-485 transceiver , while NSi83086x is an isolated full duplex RS-485 transceiver.
Data isolation is achieved using Novosense integrated capacitive isolation that allows data transmission between the logic side and
the Bus side. Both devices are safety certified by UL1577 support 5kVRMS insulation withstand voltages.
4.1. Data rate
The data rate of NSi83085x is 500kbps. The device is slew limited to reduce EMI and reflections with improperly terminated
transmission line. The data rate of NSi83086x is up to 16Mbps.
4.2. True Fail-safe receiver inputs
The devices feature fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted. The
receiver threshold is fixed between -50mV and -200mV, which meets EIA/TIA-485 standard. If the differential input voltage (VA-VB) is
greater than or equal to -50mV, receiver output R is logic high. In the case of a terminated bus with all transmitters disabled, the
differential input voltage is pulled to zero by the termination resistors. Due to the receiver threshold, the receiver output R is logic high.
4.3. Truth tables
Table 4.1 Driver Function Table
VDD1 status
VDD2 status
Copyright © 2020, NOVOSENSE
Input
Enable Input
Outputs1
Page 12
NSi83085x/NSi83086x
Datasheet (EN) 1.4
(D)
(DE)
A/Y
B/Z
PU
PU
H
H
H
L
PU
PU
L
H
L
H
PU
PU
X
L
Z
Z
PU
PU
X
OPEN
Z
Z
PU
PU
OPEN
H
H
L
PD
PU
X
X
Z
Z
PU
PD
X
X
Z
Z
PD
PD
X
X
Z
Z
1 PD=
Powered down; PU= Powered up; H= Logic High; L= Logic Low; X= Irrelevant; Z= High Impedance; Driver output pins are Y and Z for NSi83086x, A
and B for NSi83085x;
Table 4.2 Reciever Function Table1
VDD1 status
VDD2 status
Differential Input
Enable Input
Output
(VA-VB)
(/RE)
(R)
PU
PU
≥-50mV
L/Open
H
PU
PU
≤-200mV
L/Open
L
PU
PU
Open/Short
L/Open
H
PU
PU
X
H
Z
PU
PU
Idle
L
H
PD
PU
X
X
Z
PU
PD
X
X
H
PD
PD
X
X
Z
1 PD=
Powered down; PU= Powered up; H= Logic High; L= Logic Low; X= Irrelevant; Z= High Impedance.
4.4. Thermal shutdown
The device is protected from over temperature damage by integrated thermal shutdown circuitry. When the junction temperature
(TJ) exceeds +165°C (typ), the driver outputs go high-impedance. The device resumes normal operation when TJ falls below +145°C
(typ).
5. Application Note
5.1. 256 transceivers on the bus
The devices have a 1/8-unit-load receiver input impedance (96kΩ) that allows up to 256 transceivers on the bus. Connect any
combination of these devices, and/or other RS-485 devices, for a maximum of 32 unit-loads to the line.
5.2. ESD protection
ESD protection structures are enhanced on all pins to protect against electrostatic discharge encountered during handing and assembly.
The Bus pins have extra protection against static electricity to both the logic side (VDD1 side) and bus side (VDD2 side).
ESD protection can be tested in various ways. Below is the ESD spec of the devices.
Copyright © 2020, NOVOSENSE
Page 13
NSi83085x/NSi83086x
Datasheet (EN) 1.4
Bus pins:
± 8kV HBM.
±10kV using the Contact Discharge method specified in IEC 61000-4-2
Other pins except bus pins:
±6kV HBM.
±7kV using the Contact Discharge method specified in IEC 61000-4-2
5.3. Layout considerations
The NSi83085x/NSi83086x requires a 0.1 µF bypass capacitor between VDD and GND. The capacitor should be placed as close as
possible to the package. To eliminate line reflections, each cable end is terminated with a resistor, whose value matches the
characteristic impedance of the cable. It’s good practice to have the bus connectors and termination resistor as close as possible to
the A and B, Y and Z pins.
5.4. Typical application
GND1
VDD1 VDD2
GND2
R
MICROPROCESSOR
AND UART
/RE
B
DE
A
D
Figure 5.1 NSi83085x typical application circuit
R
R
/RE
B
B
/RE
DE
A
A
DE
D
D
B
R /RE
A
DE
D
Figure 5.2 Typical isolated Half-Duplex RS-485 application
GND1
MICROPROCESSOR
AND UART
VDD1 VDD2
GND2
R
A
/RE
B
DE
Z
D
Y
Figure 5.3 NSi83086x typical application circuit
Copyright © 2020, NOVOSENSE
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NSi83085x/NSi83086x
Datasheet (EN) 1.4
R
A
Y
D
/RE
B
Z
DE
Z
B
/RE
Y
A
R
Master
Z
Y
A
B
Slave
Slave
R
/RE DE
D
Figure 5.4 Typical isolated Full-Duplex RS-485 application
6. Package Information
VDD1 1
16 VDD2
GND1 2
15 GND2
R
3
14 NC
/RE 4
13 B
DE 5
12 A
D
6
11 NC
GND1 7
GND1 8
10 GND2
NSi83085
9 GND2
Figure 6.1 NSi83085x Package
VDD1 1
16 VDD2
GND1 2
15 GND2
3
14 A
/RE 4
13 B
DE 5
12 Z
6
11 Y
R
D
GND1 7
GND1 8
10 GND2
NSi83086
9 GND2
Figure 6.2 NSi83086x Package
Copyright © 2020, NOVOSENSE
Page 15
NSi83085x/NSi83086x
Datasheet (EN) 1.4
Figure 6.3 SOIC16 Package Shape and Dimension in millimeters and (inches)
Table6.1 NSi83085x Pin Configuration and Description
NSi83085x
PIN NO.
SYMBOL
FUNCTION
1
VDD1
Power Supply for Isolator Side 1
2
GND1
Ground 1, the ground reference for Isolator Side 1
3
R
Receive output
4
/RE
Receive enable input. This is an active low input.
5
DE
Driver enable input. This is an active high input
6
D
Driver transmit data input.
7
GND1
Ground 1, the ground reference for Isolator Side 1
8
GND1
Ground 1, the ground reference for Isolator Side 1
9
GND2
Ground 2, the ground reference for Isolator Side 2
10
GND2
Ground 2, the ground reference for Isolator Side 2
11
NC
No Connection.
12
A
Noninverting Driver Output/Receiver Input. When the driver is disabled, or when
VDD1 or VDD2 is powered down, Pin A is put into a high impedance state to avoid
overloading the bus.
13
B
Inverting Driver Output/Receiver Input. When the driver is disabled, or when VDD 1 or
VDD2 is powered down, Pin B is put into a high impedance state to avoid overloading
the bus.
Copyright © 2020, NOVOSENSE
Page 16
NSi83085x/NSi83086x
Datasheet (EN) 1.4
14
NC
No Connection.
15
GND2
Ground 2, the ground reference for Isolator Side 2
16
VDD2
Power Supply for Isolator Side 2
Table6.2 NSi83086x Pin Configuration and Description
NSi83086x
PIN NO.
SYMBOL
FUNCTION
1
VDD1
Power Supply for Isolator Side 1
2
GND1
Ground 1, the ground reference for Isolator Side 1
3
R
Receive output
4
/RE
Receive enable input. This is an active low input.
5
DE
Driver enable input. This is an active high input
6
D
Driver transmit data input.
7
GND1
Ground 1, the ground reference for Isolator Side 1
8
GND1
Ground 1, the ground reference for Isolator Side 1
9
GND2
Ground 2, the ground reference for Isolator Side 2
10
GND2
Ground 2, the ground reference for Isolator Side 2
11
Y
Noninverting Driver Output. When the driver is disabled, or when VDD 1 or VDD2 is
powered down, Pin Y is put into a high impedance state to avoid overloading the bus.
12
Z
Inverting Driver Output. When the driver is disabled, or when VDD 1 or VDD2 is
powered down, Pin Z is put into a high impedance state to avoid overloading the bus.
13
B
Inverting Receiver Input.
14
A
Noninverting Receiver Input.
15
GND2
Ground 2, the ground reference for Isolator Side 2
16
VDD2
Power Supply for Isolator Side 2
7. Tape and Reel Information
Copyright © 2020, NOVOSENSE
Page 17
NSi83085x/NSi83086x
Copyright © 2020, NOVOSENSE
Datasheet (EN) 1.4
Page 18
NSi83085x/NSi83086x
Datasheet (EN) 1.4
Figure 7.1 Tape and Reel Information of SOW16
8. Order Information
Part No.
NSi83085A
-DSWR
NSi83086A
-DSWR
NSi83085
NSi83086
Isolation
Rating(kVRMS)
5
Duplex
MSL
Temperature
No. of Nodes
Package
SPQ
Half
Max Data Rate
(Mbps)
0.5
3
-40 to 105℃
256
SOW16
1000
5
Full
16
3
-40 to 105℃
256
SOW16
1000
5
Half
0.5
3
-40 to 105℃
256
SOW16
1000
5
Full
16
3
256
SOW16
1000
-40 to 105℃
NOTE: All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
9. Revision History
Copyright © 2020, NOVOSENSE
Page 19
NSi83085x/NSi83086x
Revision
1.0
1.1
1.2
1.3
1.4
Description
Initial version
Update format
Added MSL information
Added NSi83085 and NSi83086 information
Correction MSL level
Copyright © 2020, NOVOSENSE
Datasheet (EN) 1.4
Date
2020/12/5
2021/2/25
2021/3/2
2021/4/8
2021/6/8
Page 20
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