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BMR4613001/001

BMR4613001/001

  • 厂商:

    FLEX(伟创力)

  • 封装:

    BLGA32 模块

  • 描述:

    非隔离 PoL 模块,数字 直流转换器 1 输出 0.6 ~ 5V 12A 4.5V - 14V 输入

  • 数据手册
  • 价格&库存
BMR4613001/001 数据手册
Internal Use Only PRODUCT TABLE OF CONTENTS SPECIFICATION Prepared (also subject responsible if other) 1/1301-BMR 461 Uen 00152-BMR461 Technical jidgezou George Jidgezou GeorgeZou Zou Approved BMR461 series jiddaxie David Xie 1 (2) (4) No. Checked PoL Regulators Input 4.5-14 V, Output up to 18 A / 60 W Specification Date Rev Reference 10/30/2019 1/28701-BMR 461 Rev. K E J November 2019 © Flex Key Features • Small package 12.2 x 12.2 x 8.0 mm (0.48 x 0.48 x 0.315 in) • Architects of Modern PowerTM picoAMPTM Compliant • 0.6 V - 5.0 V output voltage range • High efficiency, typ. 96 % at 12Vin, 5Vout and 80% load • Configuration Control and Monitoring via PMBus • Adaptive compensation of PWM control loop & fast loop transient response • Synchonization input & phase spreading/interleaving • Voltage Tracking & Voltage margining • MTBF 24 Mh General Characteristics • • • • • • • • • For narrow board pitch applications (15 mm/0.6 in) Pre-bias start-up and shut down Monotonic & Soft start Power up Input under voltage shutdown OTP, output OVP, OCP Remote control & Power Good Differential sense pins Voltage setting via pin-strap or PMBus Advanced Configurable via Graphical User Interface • ISO 9001/14001 certified supplier • Highly automated manufacturing ensures quality Safety Approvals Design for Environment Meets requirements in hightemperature lead-free soldering processes. Contents Ordering Information General Information Safety Specification Absolute Maximum Ratings ............................................................. 2 ............................................................. 2 ............................................................. 3 ............................................................. 4 Electrical Specification 6 A / 0.6 – 5.0 V 12 A / 0.6 – 5.0 V 18 A / 0.6 – 1.8 V 15 A / 0.6 – 3.3 V BMR 461 2001 BMR 461 3001 BMR 461 4001 BMR 461 5001 ..................................... 5 ................................... 15 ................................... 25 ................................... 33 EMC Specification Operating Information Thermal Consideration Typical Application Circuit PCB Layout Consideration Mechanical Information Soldering Information Delivery Package Information Product Qualification Specification ........................................................... 42 ........................................................... 43 ........................................................... 52 ........................................................... 54 ........................................................... 54 ........................................................... 60 ........................................................... 62 ........................................................... 63 ........................................................... 64 2 Internal Use Only PRODUCT SPECIFICATION Prepared (also subject responsible if other) 1/1301-BMR 461 Uen Technical jidgezou George Zou Approved Checked BMR461 series jiddaxie David Xie PoL Regulators Input 4.5-14 V, Output up to 18 A / 60 W Product program BMR 461 2001 BMR 461 3001 BMR 461 4001 BMR 461 5001 Rev 10/30/2019 1/28701-BMR 461 Rev. K E November 2019 © Flex The products are compatible with the relevant clauses and requirements of the RoHS directive 2002/95/EC and have a maximum concentration value of 0.1% by weight in homogeneous materials for lead, mercury, hexavalent chromium, PBB and PBDE and of 0.01% by weight in homogeneous materials for cadmium. Output 0.6-5.0 V, 6 A/ 30 W 0.6-5.0 V, 12 A/ 60 W 0.6-1.8 V, 18 A/ 32W 0.6-3.3 V, 15 A/ 50 W Product number and Packaging BMR 461 n1n2n3n4/n5n6n7n8 Options n1 n2 n3 n4 / n5 Output Current / ο ο Exemptions in the RoHS directive utilized in Flex products are found in the Statement of Compliance document. n6 n7 n8 / ο Variants info Specification Date Compatibility with RoHS requirements Ordering Information Mechanical 2 (4) No. ο / / / Configuration file Packaging ο ο ο ο Flex fulfills and will continuously fulfill all its obligations under regulation (EC) No 1907/2006 concerning the registration, evaluation, authorization and restriction of chemicals (REACH) as they enter into force and is through product materials declarations preparing for the obligations to communicate information on substances in the products. Quality Statement Options Description n1 2 3 4 5 6A 12A 18A 15A n2 0 1 2 3 LGA (Land Grid Array) BGA (Solder Bump Grid Array) Inductor-glued LGA Inductor-glued BGA n3 n4 01 Standard variants Warranty n5 n6 n7 001 Standard configuration Warranty period and conditions are defined in Flex General Terms and Conditions of Sale. n8 C Antistatic tape & reel of 280 pcs of modules (1 full reel/box =280 pcs of modules. Sample delivery avalable in lower quantities) The products are designed and manufactured in an industrial environment where quality systems and methods like ISO 9000, Six Sigma, and SPC are intensively in use to boost the continuous improvements strategy. Infant mortality or early failures in the products are screened out and they are subjected to an ATE-based final test. Conservative design rules, design reviews and product qualifications, plus the high competence of an engaged work force, contribute to the high quality of the products. Limitation of Liability General Information Flex does not make any other warranties, expressed or implied including any warranty of merchantability or fitness for a particular purpose (including, but not limited to, use in life support applications, where malfunctions of product can cause injury to a person’s health or life). Reliability © Flex 2019 Example: Product number BMR 461 3001/001C equals a 12A, LGA, PMBus and analog pin strap, standard configuration variant. The failure rate (λ) and mean time between failures (MTBF= 1/λ) is calculated at max output power and an operating ambient temperature (TA) of +40°C. Flex uses Telcordia SR-332 Issue 2 Method 1 to calculate the mean steady-state failure rate and standard deviation (σ). Telcordia SR-332 Issue 2 also provides techniques to estimate the upper confidence levels of failure rates based on the mean and standard deviation. Mean steady-state failure rate, λ 40 nFailures/h Std. deviation, σ 8.2 nFailures/h MTBF (mean value) for the BMR 461 series = 24.98 Mh. MTBF at 90% confidence level = 19.77 Mh (calculation based on BMR461 3001) The information and specifications in this technical specification is believed to be correct at the time of publication. However, no liability is accepted for inaccuracies, printing errors or for any consequences thereof. Flex reserves the right to change the contents of this technical specification at any time without prior notice. 3 Internal Use Only PRODUCT SPECIFICATION Prepared (also subject responsible if other) 1/1301-BMR 461 Uen Technical jidgezou George Zou Approved BMR461 series jiddaxie David Xie Checked PoL Regulators Input 4.5-14 V, Output up to 18 A / 60 W Safety Specification General information Flex DC/DC converters and DC/DC regulators are designed in accordance with safety standards IEC/EN/UL 60950-1 Safety of Information Technology Equipment. IEC/EN/UL 60950-1 contains requirements to prevent injury or damage due to the following hazards: • • • • • • 3 (4) No. Electrical shock Energy hazards Fire Mechanical and heat hazards Radiation hazards Chemical hazards On-board DC/DC converters and DC/DC regulators are defined as component power supplies. As components they cannot fully comply with the provisions of any safety requirements without “Conditions of Acceptability”. Clearance between conductors and between conductive parts of the component power supply and conductors on the board in the final product must meet the applicable safety requirements. Certain conditions of acceptability apply for component power supplies with limited stand-off (see Mechanical Information for further information). It is the responsibility of the installer to ensure that the final product housing these components complies with the requirements of all applicable safety standards and regulations for the final product. Component power supplies for general use should comply with the requirements in IEC 60950-1, EN 60950-1 and UL 60950-1 Safety of Information Technology Equipment. There are other more product related standards, e.g. IEEE 802.3 CSMA/CD (Ethernet) Access Method, and ETS-300132-2 Power supply interface at the input to telecommunications equipment, operated by direct current (dc), but all of these standards are based on IEC/EN/UL 60950-1 with regards to safety. Flex DC/DC converters and DC/DC regulators are UL 60950-1 recognized and certified in accordance with EN 60950-1. The flammability rating for all construction parts of the products meet requirements for V-0 class material according to IEC 60695-11-10, Fire hazard testing, test flames – 50 W horizontal and vertical flame test methods. The products should be installed in the end-use equipment, in accordance with the requirements of the ultimate application. Normally the output of the DC/DC converter is considered as SELV (Safety Extra Low Voltage) and the input source must be isolated by minimum Double or Reinforced Insulation from the primary circuit (AC mains) in accordance with IEC/EN/UL 60950-1. Specification Date Rev 10/30/2019 1/28701-BMR 461 Rev. K E November 2019 © Flex Isolated DC/DC converters It is recommended that a slow blow fuse is to be used at the input of each DC/DC converter. If an input filter is used in the circuit the fuse should be placed in front of the input filter. In the rare event of a component problem that imposes a short circuit on the input source, this fuse will provide the following functions: • • Isolate the fault from the input power source so as not to affect the operation of other parts of the system. Protect the distribution wiring from excessive current and power loss thus preventing hazardous overheating. The galvanic isolation is verified in an electric strength test. The test voltage (Viso) between input and output is 1500 Vdc or 2250 Vdc (refer to product specification). 24 V DC systems The input voltage to the DC/DC converter is SELV (Safety Extra Low Voltage) and the output remains SELV under normal and abnormal operating conditions. 48 and 60 V DC systems If the input voltage to the DC/DC converter is 75 Vdc or less, then the output remains SELV (Safety Extra Low Voltage) under normal and abnormal operating conditions. Single fault testing in the input power supply circuit should be performed with the DC/DC converter connected to demonstrate that the input voltage does not exceed 75 Vdc. If the input power source circuit is a DC power system, the source may be treated as a TNV-2 circuit and testing has demonstrated compliance with SELV limits in accordance with IEC/EN/UL60950-1. Non-isolated DC/DC regulators The input voltage to the DC/DC regulator is SELV (Safety Extra Low Voltage) and the output remains SELV under normal and abnormal operating conditions. 4 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 1 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date 8/30/2019 Rev 1/28701-BMR 461 Rev. K L November 2019 © Flex Absolute Maximum Ratings Characteristics min max Unit TP1 Operating temperature (see Thermal Consideration section) -40 typ 120 °C TS Storage temperature -40 125 °C VI Input voltage (See Operating Information Section for input and output voltage relations) -0.3 18 V Logic I/O voltage Ground voltage differential CTRL, SA0, SA1, SALERT, SCL, SDA, VSET, SYNC, PG, CS_VTRK -0.3 4 V -S, PREF, GND -0.3 0.3 V Analog pin voltage VO, +S -0.3 5.5 V Stress in excess of Absolute Maximum Ratings may cause permanent damage. Absolute Maximum Ratings, sometimes referred to as no destruction limits, are normally tested with one parameter at a time exceeding the limits in the Electrical Specification. If exposed to stress above these limits, function and performance may degrade in an unspecified manner. See technical paper TP023 for details on how data retention time of the Non-Volatile Memory (NVM) of the product is affected by high temperature. Configuration File This product is designed with a digital control circuit. The control circuit uses a configuration file which determines the functionality and performance of the product. The Electrical Specification table shows parameter values of functionality and performance with the default configuration file, unless otherwise specified. The default configuration file is designed to fit most application needs with focus on high efficiency. If different characteristics are required it is possible to change the configuration file to optimize certain performance characteristics. In this Technical specification examples are included to show the possibilities with digital control. See Operating Information section for information about trade offs when optimizing certain key performance characteristics. Fundamental Circuit Diagram 5 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 2 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Electrical Specification BMR 461 2001 TP1 = -30 to +95°C, VI = 4.5 to 14 V, VI > VO + 1.0 V Typical values given at: TP1 = +25°C, VI = 12.0 V, max IO, unless otherwise specified under Conditions. Default configuration file, 190 10-CDA 102 0518/001. VO defined by pin strap. External CIN = 47 µF ceramic + 270 µF/10 mΩ electrolytic, COUT = 3x100 µF + 0.1 µF ceramic. See Operating Information section for selection of capacitor types. Sense pins are connected to the output pins. Characteristics VI Conditions Input voltage Output voltage without pin strap Output voltage adjustment range Output voltage adjustment including PMBus margining Output voltage set-point resolution Output voltage accuracy Internal resistance +S/-S to VOUT/GND +S bias current -S bias current VO Line regulation IO = max IO Load regulation IO = 0 - 100% VOac Output ripple & noise (up to 20 MHz) IO Output current Static input current at max IO Ilim Current limit threshold Short circuit current Efficiency IO = max IO Pd Power dissipation at max IO max Unit 14 V V V 0 0.60 5.0 0.50 5.25 1.2 Including line, load, temp -1 1 47 50 -35 1 2 3 4 7 1 1 1 2 2 10 10 11 19 25 VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V RMS, hiccup mode, VO = 3.3 V, 4 mΩ short 50% of max IO η typ 4.5 0 IS Isc min mV mV mVp-p 6 0.38 0.70 1.00 1.75 2.63 10 3 VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VO = 0.6 V VO = 1.2 V VO = 1.8 V 70.1 81.8 86.4 91.0 93.3 78.5 87.3 90.7 94.0 95.6 0.99 1.01 1.12 VO = 3.3 V 1.28 VO = 5.0 V 1.40 V mV % VO Ω µA µA A A 11.5 A A % % W 6 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 3 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex BMR 461 2001 Characteristics Conditions W 47 47 24 15 μF Input standby power Turned off with CTRL-pin CI Internal input capacitance VI = 0 V VO = 0 V VO = 3.3 V VO = 5.0 V Effective capacitance Note 1 COUT Total output capacitance Vtr1 Load transient peak voltage deviation ttr1 Load transient recovery time Switching frequency range Switching frequency set-point accuracy External Sync Duty Cycle SYNC-in clock PLL lock range Input Under Voltage Lockout (hardware controlled) Input Over Voltage Lockout (hardware controlled) Input Turn-On Voltage Input Turn-Off Voltage Threshold, VUVLO Load step 25-75-25% of max IO, di/dt = 1.5 A/μs CO=3x100 μF + 270 μF VO = 3.3 V IOVP threshold IOVP threshold range UVP threshold Output voltage Over/Under Voltage Protection, OVP/UVP UVP threshold range OVP threshold OVP threshold range Fault response µs 600 kHz 300-1000 kHz Locked operation frequency Rising edge 3.8 4.1 4.4 V 0.24 Set point accuracy Fault response 13 % % % NOTE8 PMBus configurable VIN_ON NOTE8 PMBus configurable VIN_OFF NOTE8 PMBus configurable VIN_UV_FAULT_LIMIT NOTE8 PMBus configurable VIN_OV_FAULT_LIMIT IUVP threshold range mV 10 60 10 Threshold Threshold range 25 ±5 Input rising Threshold μF -10 40 -10 Threshold, VOVLO IUVP threshold Input Under/Over Voltage Protection, IUVP/ IOVP PMBus configurable FREQUENCY_SWITCH Note 2 Hysteresis Threshold range μF 55 Switching frequency Fsw Unit 0.25 PCTRL Internal output capacitance max W Input idling power CO typ 0.70 0.70 0.71 0.80 0.92 Pli IO = 0 min VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VIN_UV_FAULT_RESPONSE VIN_OV_FAULT_RESPONSE NOTE8 PMBus configurable VOUT_UV_FAULT_LIMIT NOTE8 PMBus configurable VOUT_OV_FAULT_LIMIT VOUT_UV_FAULT_RESPONSE VOUT_OV_FAULT_RESPONSE 14.3 15.2 V 16 V 4.35 V 0-14.7 V 3.8 V 0-14.7 V 4.1 V 0-14.7 V 14.4 V 0-14.7 V -150 150 Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3. 88 mV % VO 0-100 % VO 112 % VO 100-115 % VO Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3. 7 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 4 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex BMR 461 2001 Characteristics OCP threshold Over Current Protection, OCP Over Temperature Protection, OTP Over Temperature Shutdown (hardware controlled) OCP threshold range min Set value PMBus configurable IOUT_OC_FAULT_LIMIT 10 Fault response IOUT_OC_FAULT_RESPONSE OTP threshold OTP hysteresis Note 4 PMBus configurable OT_FAULT_LIMIT PMBus configurable Fault response OT_FAULT_RESPONSE Threshold Hysteresis Accuracy Note 4 OTP threshold range VOL Logic output low signal level VOH Logic output high signal level IOL IOH VIL VIH IIL_CTRL Logic output low sink current Logic output high source current Logic input low threshold Logic input high threshold Logic input low sink current II_LEAK Logic leakage current fSMB SMBus Operating frequency TBUF SMBus Bus free time tset thold SMBus SDA setup time from SCL SMBus SDA hold time from SCL SMBus START/STOP condition setup/hold time from SCL SCL low period SCL high period Tlow Thigh Conditions SCL, SDA, SYNC, SALERT, PG Sink/source current = 4 mA SCL, SDA, CTRL, SYNC Note 5 Delay duration range Delay accuracy Soft-start Rise Time (0-100% of VO) Note 5 Ramp set resolution Ramp set accuracy Ramp time accuracy V 2.8 Signal level 0.5 mA mA V V mA 10 uA 2 400 kHz 1.3 µs 100 300 ns ns 600 ns 1.3 0.6 µs µs TON_DELAY value sent versus read-back Actual delay duration versus TON_DELAY read-back VO = 0.6 V VO = 1.2 – 3.3 V VO = 5.0 V °C °C °C V 4 4 0.8 PMBus configurable TON_DELAY Signal duration Compensation Calibration °C 0.4 10 PMBus configurable TON_RISE Varies with VO TON_RISE value sent versus read-back Actual ramp duration versus TON_RISE read-back °C °C 23 ms 10 ms 1-145 ms 0.6 ms ±0.5 x Delay set resolution Ramp duration Ramp duration range A 15 Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3. 150 20 ±20 Delay set resolution Delay set accuracy A -40…+120 Delay duration Soft-start On Delay Time Unit Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3. 120 CTRL SCL, SDA, SYNC, SALERT, PG STOP bit to START bit See section SMBus – Timing max 11.5 0-11.5 From VI > VUVLO to ready to be enabled Initialization time typ ms ±0.8 ms 10 ms 1 - (255 x Ramp set resolution) 0.4 ms 1 ±0.5 x Ramp set resolution ms ms ±10 µs 5 3.5 2.5 2 ms % VO 8 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 5 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex BMR 461 2001 Characteristics Conditions PG threshold Power Good , PG min Rising Falling Tracking mode See section Voltage Tracking Unit % VO % VO 450 mV PMBus configurable POWER_GOOD_ON POWER_GOOD_OFF PG delay From VO reaching target to PG assertion 11 ms Enabled compensation calibration (default) Tracking mode See section Voltage Tracking 20 ms PG delay From VO reaching PG rising threshold to PG assertion 0 ms Disabled compensation calibration Tracking mode See section Voltage Tracking 20 Ms CS_VTRK pin Note 6 Tracking Accuracy 0 100 % VO 0 1.2 V -100 100 mV Input voltage READ_VIN Output voltage READ_VOUT ±3 % VI ±1 % VO ±8.5 % IO ±0.4 A Output current READ_IOUT Note 7 TP1 = 0-95°C, VI = 4.5-14 V, IO > 5 A TP1 = 0-95°C, VI = 4.5-14 V, IO < 5 A Temperature READ_ TEMPERATURE_1 Note 4 -5 5 °C Duty cycle < 10% -3 3 % Duty cycle > 10% -1 1 % Duty cycle READ_DUTY_CYCLE RPU max 90 85 PG thresholds range (Non-tracking only) Tracking Input Voltage Range Monitoring accuracy typ Logic pin internal pull-up resistance SCL, SDA, SALERT CTRL to 3.3 V ±0.5 No internal pull-up 6.8 KΩ Note 1. Value refers to total (internal + external) effective output capacitance. Capacitance derating with VO typical for ceramic capacitors (bias characteristics) and temperature variations must be considered for the external capacitor(s). See section External Output Capacitors. Note 2. A switching frequency close to 475 kHz should not be used since this frequency represents a boundary of two operational modes of the product. There are configuration changes to consider when changing the switching frequency, see section Switching Frequency. Note 3.The restart interval is configurable between 100ms and 700ms in 100ms steps. Severe overcurrent faults occurring with VO > 2.5V may result in a restart interval of 1200 ms instead of the configured value. See operating conditions for other fault response alternatives. Note 4. Temperature measured internally at temperature position P3. See section Over Temperature Protection. Note 5. Same specification applies for soft-stop and TOFF_DELAY/TOFF_FALL if enabled. The internal ramp and delay generators can only achieve certain discrete timing values. A written TON/OFF_DELAY or TON/OFF_RISE value will be rounded to the closest achievable value, thus a command read-back provides the actual set value. See section Soft-Start and Soft-Stop. Note 6.Larger tracking input range is provided by external resistor divider, see section Voltage Tracking. Note 7. At VO > 3.5V and VO / VI in the approximate range 55-70% there may be an additional current monitoring inaccuracy on the negative side up to -1 A. Note 8. Factory default settings by PMBUS 9 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 6 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Typical Characteristics, VO = 0.6 V BMR 461 2001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 90 1.5 85 1.2 80 VI VI 75 4.5 V 70 5V 65 4.5 V 0.9 5V 0.6 12 V 12 V 60 14 V 14 V 0.3 55 0.0 50 0 1 2 3 4 5 0 6 [A] 1 2 3 4 5 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics [A] 6 [A] [V] 6 0.8 5 3.0 m/s 4 2.0 m/s 3 1.0 m/s VI 0.6 4.5 V 0.4 5V 0.5 m/s 2 Nat. Conv. 12 V 0.2 14 V 1 0.0 0 100 102 104 106 108 110 [°C] 6 7 8 9 10 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 6 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (1.5–4.5–1.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 20 mV/div, 5 A/div, 100 µs/div. 10 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 7 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Typical Characteristics, VO = 1.2 V BMR 461 2001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 95 1.5 90 1.2 85 VI VI 80 4.5 V 75 4.5 V 0.9 5V 5V 70 12 V 65 14 V 0.6 12 V 14 V 0.3 60 55 0.0 0 1 2 3 4 5 6 [A] 0 1 2 3 4 5 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics 6 [A] [V] [A] 6 1.6 5 3.0 m/s VI 1.2 4 2.0 m/s 3 1.0 m/s 4.5 V 0.8 5V 0.5 m/s 2 12 V Nat. Conv. 1 0 94 96 98 100 102 104 0.4 14 V 0.0 [°C] 6 7 8 9 10 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 6A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (1.5–4.5–1.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 20 mV/div, 5 A/div, 100 µs/div. 11 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 8 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Typical Characteristics, VO = 1.8 V BMR 461 2001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 100 1.5 95 1.2 90 VI VI 85 4.5 V 80 4.5 V 0.9 5V 5V 75 12 V 70 14 V 0.6 12 V 14 V 0.3 65 0.0 60 0 1 2 3 4 5 0 6 [A] 1 2 3 4 5 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics [A] 6 [A] [V] 6 2.0 5 3.0 m/s 4 2.0 m/s 3 1.0 m/s 0.5 m/s 2 1.6 VI 1.2 4.5 V 5V 0.8 12 V Nat. Conv. 14 V 0.4 1 0 94 96 98 100 102 104 0.0 [°C] 6 7 8 9 10 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 6 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (1.5–4.5–1.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 20 mV/div, 5 A/div, 100 µs/div. 12 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 9 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Typical Characteristics, VO = 3.3 V BMR 461 2001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 100 1.5 95 1.2 VI VI 90 4.5 V 85 5V 80 12 V 14 V 75 70 4.5 V 0.9 5V 0.6 12 V 14 V 0.3 0.0 0 1 2 3 4 5 0 6 [A] 1 2 3 4 5 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics [A] 6 [A] [V] 6 3.6 5 3.0 m/s 3.0 VI 4 2.0 m/s 2.4 3 1.0 m/s 1.8 5V 1.2 12 V 0.5 m/s 2 4.5 V Nat. Conv. 14 V 0.6 1 0.0 0 92 94 96 98 100 102 [°C] 6 7 8 9 10 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 6 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (1.5–4.5–1.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 20 mV/div, 5 A/div, 100 µs/div. 13 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 10 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Typical Characteristics, VO = 5.0 V BMR 461 2001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 100 2.1 1.8 95 90 85 VI 1.5 6V 1.2 9.6 V 12 V 80 VI 6V 9.6 V 0.9 12 V 0.6 14 V 14 V 75 0.3 0.0 70 0 1 2 3 4 5 0 6 [A] 1 2 3 4 5 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics [A] 6 [A] [V] 6 6.0 5 3.0 m/s 5.0 VI 4 2.0 m/s 4.0 3 1.0 m/s 3.0 9.6 V 2.0 12 V 0.5 m/s 2 6V Nat. Conv. 14 V 1.0 1 0.0 0 92 94 96 98 100 102 [°C] 6 7 8 9 10 11 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 6A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (1.5–4.5–1.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 100 µs/div. 14 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) 11 (40) No. Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date 8/30/2019 Rev 1/28701-BMR 461 Rev. K L © Flex Typical Characteristics BMR 461 2001 Default Configuration, TP1 = +25°C, VO = 3.3 V Start-up by input source Shut-down by input source VI VI VO VO PG PG Start-up enabled by applying VI. TON_DELAY = TON_RISE = 10 ms (default). VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 10 or 2 V/div, 10 ms/div. Shut-down by removing VI. VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 10 or 2 V/div, 1 ms/div. Start-up by CTRL signal Shutdown by CTRL signal CTRL CTRL VO VO PG PG Start-up enabled by CTRL signal. TON_DELAY = TON_RISE = 10 ms (default). VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 2 V/div, 10 ms/div. November 2019 Shut-down by CTRL signal. VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 2 V/div, 1 ms/div. 15 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 12 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Electrical Specification BMR 461 3001 TP1 = -30 to +95°C, VI = 4.5 to 14 V, VI > VO + 1.0 V Typical values given at: TP1 = +25°C, VI = 12.0 V, max IO, unless otherwise specified under Conditions. Default configuration file, 190 10-CDA 102 0370/001. VO defined by pin strap. External CIN = 47 µF ceramic + 270 µF/10 mΩ electrolytic, COUT = 3x100 µF + 0.1 µF ceramic. See Operating Information section for selection of capacitor types. Sense pins are connected to the output pins. Characteristics VI Conditions Input voltage Output voltage without pin strap Output voltage adjustment range Output voltage adjustment including PMBus margining Output voltage set-point resolution Output voltage accuracy Internal resistance +S/-S to VOUT/GND +S bias current -S bias current VO Line regulation IO = max IO Load regulation IO = 0 - 100% VOac Output ripple & noise (up to 20 MHz) IO Output current Static input current at max IO Ilim Current limit threshold Short circuit current Efficiency IO = max IO Pd Power dissipation at max IO max Unit 14 V V V 0 0.60 5.0 0.50 5.25 1.2 Including line, load, temp -1 1 47 50 -35 1 2 3 4 7 1 1 1 2 2 10 10 11 19 25 VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V RMS, hiccup mode, VO = 3.3 V, 4 mΩ short 50% of max IO η typ 4.5 0 IS Isc min VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V mV mV mVp-p 12 0.7 1.3 2.0 3.5 5.2 16 3 78.8 87.5 90.8 94.1 95.4 81.3 89.0 91.8 94.6 95.8 1.66 1.78 1.93 2.24 2.63 V mV % VO Ω µA µA A A 17.5 A A % % W 16 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 13 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex BMR 461 3001 Characteristics Conditions W 47 47 24 15 μF Input standby power Turned off with CTRL-pin CI Internal input capacitance VI = 0 V VO = 0 V VO = 3.3 V VO = 5.0 V Effective capacitance Note 1 COUT Total output capacitance Vtr1 Load transient peak voltage deviation ttr1 Load transient recovery time Switching frequency range Switching frequency set-point accuracy External Sync Duty Cycle SYNC-in clock PLL lock range Input Under Voltage Lockout (hardware controlled) Input Over Voltage Lockout (hardware controlled) Input Turn-On Voltage Input Turn-Off Voltage Threshold, VUVLO Load step 25-75-25% of max IO, di/dt = 1.5 A/μs CO=3x100 μF + 270 μF VO = 3.3 V IOVP threshold IOVP threshold range UVP threshold Output voltage Over/Under Voltage Protection, OVP/UVP UVP threshold range OVP threshold OVP threshold range Fault response µs 600 kHz 300-1000 kHz Locked operation frequency Rising edge 3.8 4.1 4.4 V 0.24 Set point accuracy Fault response 25 % % % NOTE8 PMBus configurable VIN_ON NOTE8 PMBus configurable VIN_OFF NOTE8 PMBus configurable VIN_UV_FAULT_LIMIT NOTE8 PMBus configurable VIN_OV_FAULT_LIMIT IUVP threshold range mV 10 60 10 Threshold Threshold range 60 ±5 Input rising Threshold μF -10 40 -10 Threshold, VOVLO IUVP threshold Input Under/Over Voltage Protection, IUVP/ IOVP PMBus configurable FREQUENCY_SWITCH Note 2 Hysteresis Threshold range μF 55 Switching frequency Fsw Unit 0.25 PCTRL Internal output capacitance max W Input idling power CO typ 0.70 0.70 0.71 0.80 0.92 Pli IO = 0 min VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 5.0 V VIN_UV_FAULT_RESPONSE VIN_OV_FAULT_RESPONSE NOTE8 PMBus configurable VOUT_UV_FAULT_LIMIT NOTE8 PMBus configurable VOUT_OV_FAULT_LIMIT VOUT_UV_FAULT_RESPONSE VOUT_OV_FAULT_RESPONSE 14.3 15.2 V 16 V 4.3 V 0-14.7 V 3.8 V 0-14.7 V 4. V 0-14.7 V 1 V 0-14.7 V -150 150 Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3 88 mV % VO 0-100 % VO 112 % VO 100-115 % VO Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3 17 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 14 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex BMR 461 3001 Characteristics OCP threshold Over Current Protection, OCP Over Temperature Protection, OTP Over Temperature Shutdown (hardware controlled) OCP threshold range min Set value PMBus configurable IOUT_OC_FAULT_LIMIT 16 Fault response IOUT_OC_FAULT_RESPONSE OTP threshold OTP hysteresis Note 4 PMBus configurable OT_FAULT_LIMIT PMBus configurable Fault response OT_FAULT_RESPONSE Threshold Hysteresis Accuracy Note 4 OTP threshold range VOL Logic output low signal level VOH Logic output high signal level IOL IOH VIL VIH IIL_CTRL Logic output low sink current Logic output high source current Logic input low threshold Logic input high threshold Logic input low sink current II_LEAK Logic leakage current fSMB SMBus Operating frequency TBUF SMBus Bus free time tset thold SMBus SDA setup time from SCL SMBus SDA hold time from SCL SMBus START/STOP condition setup/hold time from SCL SCL low period SCL high period Tlow Thigh Conditions SCL, SDA, SYNC, SALERT, PG Sink/source current = 4 mA SCL, SDA, CTRL, SYNC Note 5 Delay duration range Delay accuracy Soft-start Rise Time (0-100% of VO) Note 5 Ramp set resolution Ramp set accuracy Ramp time accuracy V 2.8 Signal level 0.5 mA mA V V mA 10 uA 2 400 kHz 1.3 µs 100 300 ns ns 600 ns 1.3 0.6 µs µs TON_DELAY value sent versus read-back Actual delay duration versus TON_DELAY read-back VO = 0.6 V VO = 1.2 – 3.3 V VO = 5.0 V °C °C °C V 4 4 0.8 PMBus configurable TON_DELAY Signal duration Compensation Calibration °C 0.4 10 PMBus configurable TON_RISE Varies with VO TON_RISE value sent versus read-back Actual ramp duration versus TON_RISE read-back °C °C 23 ms 10 ms 1-145 ms 0.6 ms ±0.5 x Delay set resolution Ramp duration Ramp duration range A 15 Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3 150 20 ±20 Delay set resolution Delay set accuracy A -40…+120 Delay duration Soft-start On Delay Time Unit Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3. 120 CTRL SCL, SDA, SYNC, SALERT, PG STOP bit to START bit See section SMBus – Timing max 17.5 0-17.5 From VI > VUVLO to ready to be enabled Initialization time typ ms ±0.8 ms 10 ms 1 - (255 x Ramp set resolution) 0.4 ms 1 ±0.5 x Ramp set resolution ms ms ±10 µs 5 3.5 2.5 2 ms % VO 18 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 15 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex BMR 461 3001 Characteristics Conditions PG threshold Power Good , PG min Rising Falling Tracking mode See section Voltage Tracking Unit % VO % VO 450 mV PMBus configurable POWER_GOOD_ON POWER_GOOD_OFF PG delay From VO reaching target to PG assertion 11 ms Enabled compensation calibration (default) Tracking mode See section Voltage Tracking 20 ms PG delay From VO reaching PG rising threshold to PG assertion 0 ms Disabled compensation calibration Tracking mode See section Voltage Tracking 20 ms CS_VTRK pin Note 6 Tracking Accuracy 0 100 % VO 0 1.2 V -100 100 mV Input voltage READ_VIN Output voltage READ_VOUT ±3 % VI ±1 % VO ±8.5 % IO ±0.4 A Output current READ_IOUT Note 7 TP1 = 0-95°C, VI = 4.5-14 V, IO > 5 A TP1 = 0-95°C, VI = 4.5-14 V, IO < 5 A Temperature READ_ TEMPERATURE_1 Note 4 -5 5 °C Duty cycle < 10% -3 3 % Duty cycle > 10% -1 1 % Duty cycle READ_DUTY_CYCLE RPU max 90 85 PG thresholds range (Non-tracking only) Tracking Input Voltage Range Monitoring accuracy typ Logic pin internal pull-up resistance SCL, SDA, SALERT CTRL to 3.3 V ±0.5 No internal pull-up 6.8 KΩ Note 1. Value refers to total (internal + external) effective output capacitance. Capacitance derating with VO typical for ceramic capacitors (bias characteristics) and temperature variations must be considered for the external capacitor(s). See section External Output Capacitors. Note 2. A switching frequency close to 475 kHz should not be used since this frequency represents a boundary of two operational modes of the product. There are configuration changes to consider when changing the switching frequency, see section Switching Frequency. Note 3.The restart interval is configurable between 100ms and 700ms in 100ms steps. Severe overcurrent faults occurring with VO > 2.5V may result in a restart interval of 1200 ms instead of the configured value. See operating conditions for other fault response alternatives. Note 4. Temperature measured internally at temperature position P3. See section Over Temperature Protection. Note 5. Same specification applies for soft-stop and TOFF_DELAY/TOFF_FALL if enabled. The internal ramp and delay generators can only achieve certain discrete timing values. A written TON/OFF_DELAY or TON/OFF_RISE value will be rounded to the closest achievable value, thus a command read-back provides the actual set value. See section Soft-Start and Soft-Stop. Note 6.Larger tracking input range is provided by external resistor divider, see section Voltage Tracking. Note 7. At VO > 3.5V and VO / VI in the approximate range 55-70% there may be an additional current monitoring inaccuracy on the negative side up to -1 A. Note 8. Factory default settings by PMBUS 19 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 16 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex Typical Characteristics, VO = 0.6 V BMR 461 3001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [W] [%] 90 2.5 85 2.0 80 VI VI 75 4.5 V 4.5 V 1.5 70 5V 5V 1.0 65 12 V 12 V 60 14 V 14 V 0.5 55 50 0 2 4 6 8 10 12 0.0 0 [A] 2 4 6 8 10 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics [A] 12 [A] [V] 12 0.75 10 3.0 m/s 8 2.0 m/s 6 1.0 m/s 0.5 m/s 0.60 VI 0.45 4.5 V 5V 0.30 12 V 4 Nat. Conv. 2 14 V 0.15 0.00 0 85 90 95 100 105 [°C] 12 13 14 15 16 17 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 12 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (3–9–3 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 50 µs/div. 20 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 17 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex Typical Characteristics, VO = 1.2 V BMR 461 3001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 95 2.5 90 2.0 85 VI VI 80 4.5 V 1.5 4.5 V 75 5V 5V 1.0 70 12 V 12 V 65 14 V 14 V 0.5 60 55 0.0 0 2 4 6 8 10 12 0 [A] 2 4 6 8 10 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics 12 [A] [V] [A] 12 1.50 10 3.0 m/s 8 2.0 m/s 6 1.0 m/s VI 1.20 4.5 V 0.90 0.5 m/s 5V 0.60 12 V 4 Nat. Conv. 14 V 0.30 2 0 0.00 85 90 95 100 105 [°C] 12 13 14 15 16 17 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 12 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (3–9–3 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 50 µs/div. 21 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 18 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex Typical Characteristics, VO = 1.8 V BMR 461 3001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [W] [%] 100 2.5 95 2.0 90 VI VI 85 4.5 V 1.5 4.5 V 80 5V 5V 1.0 75 12 V 12 V 70 14 V 14 V 0.5 65 60 0.0 0 2 4 6 8 10 12 0 [A] 2 4 6 8 10 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics 12 [A] [V] [A] 12 2.0 10 3.0 m/s 8 2.0 m/s 6 1.0 m/s VI 1.6 4.5 V 1.2 0.5 m/s 5V 0.8 12 V 4 Nat. Conv. 14 V 0.4 2 0.0 0 85 90 95 100 105 12 13 14 15 16 [°C] 17 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 12 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (3–9–3 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 50 µs/div. 22 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 19 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex Typical Characteristics, VO = 3.3 V BMR 461 3001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 100 2.5 95 2.0 VI VI 90 4.5 V 85 4.5 V 1.5 5V 5V 1.0 12 V 12 V 80 14 V 75 14 V 0.5 0.0 70 0 2 4 6 8 10 12 0 [A] 2 4 6 8 10 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics [A] 12 [A] [V] 12 3.6 10 3.0 m/s 3.0 8 2.0 m/s 2.4 6 1.0 m/s 1.8 VI 4.5 V 5V 0.5 m/s 12 V 1.2 4 Nat. Conv. 14 V 0.6 2 0.0 0 85 90 95 100 105 [°C] 12 13 14 15 16 17 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 12 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (3–9–3 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 50 µs/div. 23 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 20 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex Typical Characteristics, VO = 5.0 V BMR 461 3001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [W] [%] 100 3.5 3.0 95 VI 90 6V 85 9.6 V 80 12 V 14 V VI 2.5 6V 2.0 9.6 V 1.5 12 V 1.0 14 V 75 0.5 70 0 2 4 6 8 10 0.0 12 [A] 0 2 4 6 8 10 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics 12 [A] [V] [A] 12 6.0 10 3.0 m/s 8 2.0 m/s 6 1.0 m/s 5.0 VI 4.0 6V 3.0 9.6 V 0.5 m/s 4 12 V 2.0 Nat. Conv. 14 V 2 1.0 0 80 85 90 95 100 0.0 [°C] 12 13 14 15 16 17 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 12 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (3–9–3 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 50 µs/div. 24 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) 21 (40) No. Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date 8/30/2019 Rev 1/28701-BMR 461 Rev. K L © Flex Typical Characteristics BMR 461 3001 Default Configuration, TP1 = +25°C, VO = 3.3 V Start-up by input source Shut-down by input source VI VI VO VO PG PG Start-up enabled by applying VI. TON_DELAY = TON_RISE = 10 ms (default). VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 10 or 2 V/div, 10 ms/div. Shut-down by removing VI. VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 10 or 2 V/div, 1 ms/div. Start-up by CTRL signal Shutdown by CTRL signal CTRL CTRL VO VO PG PG Start-up enabled by CTRL signal. TON_DELAY = TON_RISE = 10 ms (default). VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 2 V/div, 10 ms/div. November 2019 Shut-down by CTRL signal. VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 2 V/div, 1 ms/div. 25 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 22 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Electrical Specification BMR 461 4001 TP1 = -30 to +95°C, VI = 4.5 to 14 V, VI > VO + 1.0 V Typical values given at: TP1 = +25°C, VI = 12.0 V, max IO, unless otherwise specified under Conditions. Default configuration file, 190 10-CDA 102 0519/001. VO defined by pin strap. External CIN = 47 µF ceramic + 270 µF/10 mΩ electrolytic, COUT = 3x100 µF + 0.1 µF ceramic. See Operating Information section for selection of capacitor types. Sense pins are connected to the output pins. Characteristics VI VO Conditions Input voltage Output voltage without pin strap Output voltage adjustment range Output voltage adjustment including PMBus margining Output voltage set-point resolution Output voltage accuracy Internal resistance +S/-S to VOUT/GND +S bias current -S bias current Line regulation IO = max IO Load regulation IO = 0 - 100% VOac Output ripple & noise (up to 20 MHz) IO Output current Static input current at max IO Ilim Current limit threshold Short circuit current Efficiency IO = max IO Pd Power dissipation at max IO max Unit 14 V V V 0 0.60 1.8 0.50 2.0 1.2 Including line, load, temp -1 1 47 50 -35 3 3 5 2 2 1 10 10 11 VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 0.6 V VO = 1.2 V VO = 1.8 V RMS, hiccup mode, VO = 3.3 V, 4 mΩ short 50% of max IO η typ 4.5 0 IS Isc min VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 0.6 V VO = 1.2 V VO = 1.8 V VO = 0.6 V VO = 1.2 V VO = 1.8 V mV mV mVp-p 18 0.38 0.70 1.00 24 3 81.0 88.7 91.6 79.3 87.5 90.5 2.80 3.10 3.40 V mV % VO Ω µA µA A A 26.25 A A % % W 26 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 23 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex BMR 461 4001 Characteristics Conditions W 47 47 39 35 μF Input standby power Turned off with CTRL-pin CI Internal input capacitance VI = 0 V VO = 0 V VO =1.2 V VO = 1.8 V Effective capacitance Note 1 COUT Total output capacitance Vtr1 Load transient peak voltage deviation ttr1 Load transient recovery time Switching frequency range Switching frequency set-point accuracy External Sync Duty Cycle SYNC-in clock PLL lock range Input Under Voltage Lockout (hardware controlled) Input Over Voltage Lockout (hardware controlled) Input Turn-On Voltage Input Turn-Off Voltage Threshold, VUVLO Load step 25-75-25% of max IO, di/dt = 1.5 A/μs CO=3x100 μF + 270 μF VO = 1.8 V IOVP threshold IOVP threshold range UVP threshold Output voltage Over/Under Voltage Protection, OVP/UVP UVP threshold range OVP threshold OVP threshold range Fault response µs 600 kHz 300-1000 kHz Locked operation frequency Rising edge 3.8 4.1 4.4 V 0.24 Set point accuracy Fault response 22 % % % NOTE8 PMBus configurable VIN_ON NOTE8 PMBus configurable VIN_OFF NOTE8 PMBus configurable VIN_UV_FAULT_LIMIT NOTE8 PMBus configurable VIN_OV_FAULT_LIMIT IUVP threshold range mV 10 60 10 Threshold Threshold range 70 ±5 Input rising Threshold μF -10 40 -10 Threshold, VOVLO IUVP threshold Input Under/Over Voltage Protection, IUVP/ IOVP PMBus configurable FREQUENCY_SWITCH Note 2 Hysteresis Threshold range μF 55 Switching frequency Fsw Unit 0.25 PCTRL Internal output capacitance max W Input idling power CO typ 0.70 0.70 0.71 Pli IO = 0 min VO = 0.6 V VO = 1.2 V VO = 1.8 V VIN_UV_FAULT_RESPONSE VIN_OV_FAULT_RESPONSE NOTE8 PMBus configurable VOUT_UV_FAULT_LIMIT NOTE8 PMBus configurable VOUT_OV_FAULT_LIMIT VOUT_UV_FAULT_RESPONSE VOUT_OV_FAULT_RESPONSE 14.3 15.2 V 16 V 4.35 V 0-14.7 V 3.8 V 0-14.7 V 4.1 V 0-14.7 V 14.4 V 0-14.7 -150 150 Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3 88 V mV % VO 0-100 % VO 112 % VO 100-115 % VO Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3 27 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 24 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex BMR 461 4001 Characteristics OCP threshold Over Current Protection, OCP Over Temperature Protection, OTP Over Temperature Shutdown (hardware controlled) OCP threshold range min Set value PMBus configurable IOUT_OC_FAULT_LIMIT 24 Fault response IOUT_OC_FAULT_RESPONSE OTP threshold OTP hysteresis Note 4 PMBus configurable OT_FAULT_LIMIT PMBus configurable Fault response OT_FAULT_RESPONSE Threshold Hysteresis Accuracy Note 4 OTP threshold range VOL Logic output low signal level VOH Logic output high signal level IOL IOH VIL VIH IIL_CTRL Logic output low sink current Logic output high source current Logic input low threshold Logic input high threshold Logic input low sink current II_LEAK Logic leakage current fSMB SMBus Operating frequency TBUF SMBus Bus free time tset thold SMBus SDA setup time from SCL SMBus SDA hold time from SCL SMBus START/STOP condition setup/hold time from SCL SCL low period SCL high period Tlow Thigh Conditions SCL, SDA, SYNC, SALERT, PG Sink/source current = 4 mA SCL, SDA, CTRL, SYNC Note 5 Delay duration range Delay accuracy Soft-start Rise Time (0-100% of VO) Note 5 Ramp set resolution Ramp set accuracy Ramp time accuracy Compensation Calibration V 2.8 Signal level 0.5 mA mA V V mA 10 uA 2 400 kHz 1.3 µs 100 300 ns ns 600 ns 1.3 0.6 µs µs TON_DELAY value sent versus read-back Actual delay duration versus TON_DELAY read-back VO = 0.6 V VO = 1.2 – 1.8 V °C °C °C V 4 4 0.8 PMBus configurable TON_DELAY Signal duration °C 0.4 10 PMBus configurable TON_RISE Varies with VO TON_RISE value sent versus read-back Actual ramp duration versus TON_RISE read-back °C °C CTRL SCL, SDA, SYNC, SALERT, PG STOP bit to START bit See section SMBus – Timing A 15 Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3 150 20 ±20 23 ms 10 ms 1-145 ms 0.6 ms ±0.5 x Delay set resolution Ramp duration Ramp duration range A -40…+120 Delay set resolution Delay set accuracy Unit Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3. 120 Delay duration Soft-start On Delay Time max 26.25 0-26.25 From VI > VUVLO to ready to be enabled Initialization time typ ms ±0.8 ms 10 ms 1 - (255 x Ramp set resolution) 0.4 ms 1 ±0.5 x Ramp set resolution ms ms ±10 µs 5 3.5 2.5 ms % VO 28 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 25 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex BMR 461 4001 Characteristics Conditions PG threshold Power Good , PG min Rising Falling Tracking mode See section Voltage Tracking Unit % VO % VO 450 mV PMBus configurable POWER_GOOD_ON POWER_GOOD_OFF PG delay From VO reaching target to PG assertion 11 ms Enabled compensation calibration (default) Tracking mode See section Voltage Tracking 20 ms PG delay From VO reaching PG rising threshold to PG assertion 0 ms Disabled compensation calibration Tracking mode See section Voltage Tracking 20 ms CS_VTRK pin Note 6 Tracking Accuracy 0 100 % VO 0 1.2 V -100 100 mV Input voltage READ_VIN Output voltage READ_VOUT ±3 % VI ±1 % VO ±8.5 % IO ±0.4 A Output current READ_IOUT Note 7 TP1 = 0-95°C, VI = 4.5-14 V, IO > 5 A TP1 = 0-95°C, VI = 4.5-14 V, IO < 5 A Temperature READ_ TEMPERATURE_1 Note 4 -5 5 °C Duty cycle < 10% -3 3 % Duty cycle > 10% -1 1 % Duty cycle READ_DUTY_CYCLE RPU max 90 85 PG thresholds range (Non-tracking only) Tracking Input Voltage Range Monitoring accuracy typ Logic pin internal pull-up resistance SCL, SDA, SALERT CTRL to 3.3 V ±0.5 No internal pull-up 6.8 KΩ Note 1. Value refers to total (internal + external) effective output capacitance. Capacitance derating with VO typical for ceramic capacitors (bias characteristics) and temperature variations must be considered for the external capacitor(s). See section External Output Capacitors. Note 2. A switching frequency close to 475 kHz should not be used since this frequency represents a boundary of two operational modes of the product. There are configuration changes to consider when changing the switching frequency, see section Switching Frequency. Note 3.The restart interval is configurable between 100ms and 700ms in 100ms steps. Severe overcurrent faults occurring with VO > 2.5V may result in a restart interval of 1200 ms instead of the configured value. See operating conditions for other fault response alternatives. Note 4. Temperature measured internally at temperature position P3. See section Over Temperature Protection. Note 5. Same specification applies for soft-stop and TOFF_DELAY/TOFF_FALL if enabled. The internal ramp and delay generators can only achieve certain discrete timing values. A written TON/OFF_DELAY or TON/OFF_RISE value will be rounded to the closest achievable value, thus a command read-back provides the actual set value. See section Soft-Start and Soft-Stop. Note 6.Larger tracking input range is provided by external resistor divider, see section Voltage Tracking. Note 7. At VO > 3.5V and VO / VI in the approximate range 55-70% there may be an additional current monitoring inaccuracy on the negative side up to -1 A. Note 8. Factory default settings by PMBUS 29 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 26 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Typical Characteristics, VO = 0.6 V BMR 461 4001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 90 4.0 85 80 VI 75 3.0 VI 4.5 V 4.5 V 2.0 70 5V 5V 12 V 65 12 V 60 1.0 14 V 14 V 55 0.0 50 0 2 4 6 8 10 12 14 16 0 18 [A] 3 6 9 12 15 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics [A] 18 [A] [V] 18 0.75 16 14 3.0 m/s 12 2.0 m/s 10 0.60 VI 0.45 4.5 V 5V 1.0 m/s 8 0.5 m/s 0.30 12 V 6 Nat. Conv. 4 14 V 0.15 2 0.00 0 75 80 85 90 95 100 105 [°C] 19 20 21 22 23 24 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 18 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (4.5–13.5–4.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 100 µs/div. 30 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 27 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex Typical Characteristics, VO = 1.2 V BMR 461 4001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 95 3.5 90 3.0 85 80 VI 2.5 4.5 V 2.0 75 5V 70 12 V 65 14 V VI 4.5 V 5V 1.5 12 V 1.0 14 V 0.5 60 55 0.0 0 2 4 6 8 10 12 14 16 18 [A] 0 3 6 9 12 15 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics [A] 18 [A] [V] 18 1.20 16 14 3.0 m/s 12 2.0 m/s 10 1.0 m/s 8 VI 1.00 0.80 4.5 V 0.60 5V 12 V 0.5 m/s 6 0.40 14 V Nat. Conv. 4 0.20 2 [A] 0.00 0 75 80 85 90 95 100 105 [°C] 18 19 20 21 22 23 Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 18A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (4.5–13.5–4.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 100 µs/div. 31 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 28 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Typical Characteristics, VO = 1.8 V BMR 461 4001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 100 4.0 95 VI 90 3.0 VI 4.5 V 4.5 V 85 5V 2.0 5V 12 V 12 V 80 14 V 1.0 14 V 75 0.0 70 0 2 4 6 8 10 12 14 16 0 18 [A] 3 6 9 12 15 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics 18 [A] [A] [V] 18 2.0 16 14 3.0 m/s 12 2.0 m/s 10 1.6 VI 1.2 4.5 V 5V 1.0 m/s 8 0.8 12 V 0.5 m/s 6 Nat. Conv. 4 2 14 V 0.4 0.0 19 0 75 80 85 90 95 100 20 21 22 23 [A] [°C] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO =18 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (4.5–13.5–4.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 100 µs/div. 32 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) 29 (40) No. Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date 8/30/2019 Rev 1/28701-BMR 461 Rev. K L © Flex Typical Characteristics BMR 461 4001 Default Configuration, TP1 = +25°C, VO = 1.8 V Start-up by input source Shut-down by input source VI VI VO VO PG PG Start-up enabled by applying VI. TON_DELAY = TON_RISE = 10 ms (default). VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 10 or 1 V/div, 10 ms/div. Shut-down by removing VI. VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 10 or 1 V/div, 1 ms/div. Start-up by CTRL signal Shutdown by CTRL signal CTRL CTRL VO VO PG PG Start-up enabled by CTRL signal. TON_DELAY = TON_RISE = 10 ms (default). VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 2 or 1 V/div, 10 ms/div. November 2019 Shut-down by CTRL signal. VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 2 or 1 V/div, 1 ms/div. 33 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 30 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Electrical Specification BMR 461 5001 TP1 = -30 to +95°C, VI = 4.5 to 14 V, VO ≤3.3V Typical values given at: TP1 = +25°C, VI = 12.0 V, max IO=15A unless otherwise specified under Conditions. Default configuration file, 190 10-CDA 102 0519/001. VO defined by pin strap. External CIN = 47 µF ceramic + 270 µF/10 mΩ electrolytic, COUT = 3x100 µF + 0.1 µF ceramic. See Operating Information section for selection of capacitor types. Sense pins are connected to the output pins. Characteristics VI VO Conditions Input voltage Output voltage without pin strap Output voltage adjustment range Output voltage adjustment including PMBus margining Output voltage set-point resolution Output voltage accuracy Internal resistance +S/-S to VOUT/GND +S bias current -S bias current Line regulation IO = max IO Load regulation IO = 0 - 100% VOac Output ripple & noise (up to 20 MHz) IO Output current Static input current at max IO Ilim Current limit threshold Short circuit current Efficiency IO = max IO Pd Power dissipation at max IO max Unit 14 V V V 0 0.60 3.3 0.50 3.3 1.2 Including line, load, temp -1 1 47 50 -35 3 3 5 9 2 2 3 4 10 10 11 16 VO = 1.0 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 1.0 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 1.0V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 1.0 V VO = 1.2 V VO = 1.8 V VO = 3.3 V RMS, hiccup mode, VO = 3.3 V, CV=0.5V 50% of max IO η typ 4.5 0 IS Isc min VO = 1.0 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 1.0V VO = 1.2 V VO = 1.8 V VO = 3.3 V VO = 1.0 V VO = 1.2 V VO = 1.8 V VO = 3.3 V mV mV mVp-p 15 1.45 1.70 2.47 4.41 24 5 86.5 88.2 91.4 94.1 86.5 88.1 91.3 93.6 2.4 2.4 2.6 3.4 V mV % VO Ω µA µA A A 26.25 A A % % W 34 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 31 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex BMR 461 5001 Characteristics Conditions W 47 47 39 35 24 μF Input standby power Turned off with CTRL-pin CI Internal input capacitance VI = 0 V VO = 0 V VO = 1.2 V VO = 1.8 V VO = 3.3 V Effective capacitance Note 1 COUT Total output capacitance Vtr1 Load transient peak voltage deviation ttr1 Load transient recovery time Switching frequency range Switching frequency set-point accuracy External Sync Duty Cycle SYNC-in clock PLL lock range Input Under Voltage Lockout (hardware controlled) Input Over Voltage Lockout (hardware controlled) Input Turn-On Voltage Input Turn-Off Voltage Threshold, VUVLO Load step 25-75-25% of max IO, di/dt = 1.5 A/μs CO=3x100 μF + 270 μF VO = 1.8 V IOVP threshold IOVP threshold range UVP threshold Output voltage Over/Under Voltage Protection, OVP/UVP UVP threshold range OVP threshold OVP threshold range Fault response µs 600 kHz 300-1000 kHz Locked operation frequency Rising edge 3.8 4.1 4.4 V 0.24 Set point accuracy Fault response 22 % % % NOTE8 PMBus configurable VIN_ON NOTE8 PMBus configurable VIN_OFF NOTE8 PMBus configurable VIN_UV_FAULT_LIMIT NOTE8 PMBus configurable VIN_OV_FAULT_LIMIT IUVP threshold range mV 10 60 10 Threshold Threshold range 70 ±5 Input rising Threshold μF -10 40 -10 Threshold, VOVLO IUVP threshold Input Under/Over Voltage Protection, IUVP/ IOVP PMBus configurable FREQUENCY_SWITCH Note 2 Hysteresis Threshold range μF 55 Switching frequency Fsw Unit 0.25 PCTRL Internal output capacitance max W Input idling power CO typ 0.7 0.7 0.7 0.8 Pli IO = 0 min VO = 1.0 V VO = 1.2 V VO = 1.8 V VO = 3.3 V VIN_UV_FAULT_RESPONSE VIN_OV_FAULT_RESPONSE NOTE8 PMBus configurable VOUT_UV_FAULT_LIMIT NOTE8 PMBus configurable VOUT_OV_FAULT_LIMIT VOUT_UV_FAULT_RESPONSE VOUT_OV_FAULT_RESPONSE 14.3 15.2 V 16 V 4.35 V 0-14.7 V 3.8 V 0-14.7 V 4.1 V 0-14.7 V 14.4 V 0-14.7 V -150 150 Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3 88 mV % VO 0-100 % VO 112 % VO 100-115 % VO Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3 35 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 32 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex BMR 461 5001 Characteristics OCP threshold Over Current Protection, OCP Over Temperature Protection, OTP Over Temperature Shutdown (hardware controlled) OCP threshold range min Set value PMBus configurable IOUT_OC_FAULT_LIMIT 24 Fault response IOUT_OC_FAULT_RESPONSE OTP threshold OTP hysteresis Note 4 PMBus configurable OT_FAULT_LIMIT PMBus configurable Fault response OT_FAULT_RESPONSE Threshold Hysteresis Accuracy Note 4 OTP threshold range VOL Logic output low signal level VOH Logic output high signal level IOL IOH VIL VIH IIL_CTRL Logic output low sink current Logic output high source current Logic input low threshold Logic input high threshold Logic input low sink current II_LEAK Logic leakage current fSMB SMBus Operating frequency TBUF SMBus Bus free time tset thold SMBus SDA setup time from SCL SMBus SDA hold time from SCL SMBus START/STOP condition setup/hold time from SCL SCL low period SCL high period Tlow Thigh Conditions SCL, SDA, SYNC, SALERT, PG Sink/source current = 4 mA SCL, SDA, CTRL, SYNC Note 5 Delay duration range Delay accuracy Soft-start Rise Time (0-100% of VO) Note 5 Ramp set resolution Ramp set accuracy Ramp time accuracy Compensation Calibration V 2.8 0.5 mA mA V V mA 10 uA 2 400 kHz 1.3 µs 100 300 ns ns 600 ns 1.3 0.6 µs µs TON_DELAY value sent versus read-back Actual delay duration versus TON_DELAY read-back 23 ms 10 ms 1-145 ms 0.6 ms ±0.5 x Delay set resolution ms ±0.8 ms 10 VO = 0.6 V VO = 1.2 – 3.3 V °C °C °C V 4 4 0.8 PMBus configurable TON_DELAY Signal duration Signal level °C 0.4 10 PMBus configurable TON_RISE Varies with VO TON_RISE value sent versus read-back Actual ramp duration versus TON_RISE read-back °C °C CTRL SCL, SDA, SYNC, SALERT, PG STOP bit to START bit See section SMBus – Timing A 15 Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3 150 20 ±20 Ramp duration Ramp duration range A -40…+120 Delay set resolution Delay set accuracy Unit Shutdown, make continuous restarts at 700 ms interval (hiccup). Note 3. 120 Delay duration Soft-start On Delay Time max 26.25 0-26.25 From VI > VUVLO to ready to be enabled Initialization time typ ms 1 - (255 x Ramp set resolution) 0.4 ms 1 ±0.5 x Ramp set resolution ms ms ±10 µs 5 3.5 2.5 ms % VO 36 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 33 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex BMR 461 5001 Characteristics Conditions PG threshold Power Good , PG min Rising Falling Tracking mode See section Voltage Tracking Unit % VO % VO 450 mV PMBus configurable POWER_GOOD_ON POWER_GOOD_OFF PG delay From VO reaching target to PG assertion 11 ms Enabled compensation calibration (default) Tracking mode See section Voltage Tracking 20 ms PG delay From VO reaching PG rising threshold to PG assertion 0 ms Disabled compensation calibration Tracking mode See section Voltage Tracking 20 ms CS_VTRK pin Note 6 Tracking Accuracy 0 100 % VO 0 1.2 V -100 100 mV Input voltage READ_VIN Output voltage READ_VOUT ±3 % VI ±1 % VO ±8.5 % IO ±0.4 A Output current READ_IOUT Note 7 TP1 = 0-95°C, VI = 4.5-14 V, IO > 5 A TP1 = 0-95°C, VI = 4.5-14 V, IO < 5 A Temperature READ_ TEMPERATURE_1 Note 4 -5 5 °C Duty cycle < 10% -3 3 % Duty cycle > 10% -1 1 % Duty cycle READ_DUTY_CYCLE RPU max 90 85 PG thresholds range (Non-tracking only) Tracking Input Voltage Range Monitoring accuracy typ Logic pin internal pull-up resistance SCL, SDA, SALERT CTRL to 3.3 V ±0.5 No internal pull-up 6.8 KΩ Note 1. Value refers to total (internal + external) effective output capacitance. Capacitance derating with VO typical for ceramic capacitors (bias characteristics) and temperature variations must be considered for the external capacitor(s). See section External Output Capacitors. Note 2. A switching frequency close to 475 kHz should not be used since this frequency represents a boundary of two operational modes of the product. There are configuration changes to consider when changing the switching frequency, see section Switching Frequency. Note 3. The restart interval is configurable between 100ms and 700ms in 100ms steps. Severe overcurrent faults occurring with VO > 2.5V may result in a restart interval of 1200 ms instead of the configured value. See operating conditions for other fault response alternatives. Note 4. Temperature measured internally at temperature position P3. See section Over Temperature Protection. Note 5. Same specification applies for soft-stop and TOFF_DELAY/TOFF_FALL if enabled. The internal ramp and delay generators can only achieve certain discrete timing values. A written TON/OFF_DELAY or TON/OFF_RISE value will be rounded to the closest achievable value, thus a command read-back provides the actual set value. See section Soft-Start and Soft-Stop. Note 6. Larger tracking input range is provided by external resistor divider, see section Voltage Tracking. Note 7. At high duty cycles, VO / VI in the approximate range 55-70% there may be an additional current monitoring inaccuracy on the negative side up to -1 A. Note 8. Factory default settings by PMBUS 37 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 34 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Typical Characteristics, VO = 1.0 V BMR 461 5001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 95 4.0 90 85 VI 80 4.5 V 75 5V 3.0 VI 4.5 V 2.0 5V 12 V 12 V 70 1.0 14 V 14 V 65 0.0 60 0 3 6 9 12 0 15 [A] 3 6 9 12 15 [A] Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics [A] [V] 15 1.00 12 VI 3.0 m/s 0.80 2.0 m/s 9 1.0 m/s 6 0.5 m/s Nat. Conv. 3 4.5 V 0.60 5V 0.40 12 V 14 V 0.20 0.00 0 75 80 85 90 95 100 105 [°C] 18 19 20 21 22 23 24 25 26 [A] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 15 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (4.5–13.5–4.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 100 µs/div. 38 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 35 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev November 2019 1/28701-BMR 461 Rev. K L 8/30/2019 © Flex Typical Characteristics, VO = 1.2 V BMR 461 5001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 95 3.5 90 3.0 85 80 VI 2.5 4.5 V 2.0 75 5V 70 12 V 65 14 V VI 4.5 V 5V 1.5 12 V 1.0 14 V 0.5 60 55 0.0 0 3 6 9 12 15 [A] 0 3 6 9 12 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics [A] 15 [A] [V] 15 1.20 12 3.0 m/s 2.0 m/s 9 1.0 m/s 6 VI 1.00 0.80 4.5 V 0.60 5V 12 V 0.5 m/s 0.40 14 V Nat. Conv. 3 0.20 [A] 0.00 0 75 80 85 90 95 100 105 [°C] 18 19 20 21 22 23 Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO = 15A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (4.5–13.5–4.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 100 µs/div. 39 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 36 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Typical Characteristics, VO = 1.8 V BMR 461 5001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 100 4.0 95 VI 90 3.0 VI 4.5 V 4.5 V 85 5V 2.0 5V 12 V 12 V 80 14 V 1.0 14 V 75 0.0 70 0 3 6 9 12 0 15 [A] 3 6 9 12 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics 15 [A] [A] [V] 15 2.0 12 3.0 m/s 2.0 m/s 9 1.6 VI 1.2 4.5 V 5V 1.0 m/s 0.8 6 12 V 0.5 m/s Nat. Conv. 14 V 0.4 3 0.0 19 0 75 80 85 90 95 100 20 21 22 23 [A] [°C] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO =15 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (4.5–13.5–4.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 100 µs/div. 40 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 37 (40) No. 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) Checked Date BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Rev 1/28701-BMR 461 Rev. K L 8/30/2019 November 2019 © Flex Typical Characteristics, VO = 3.3 V BMR 461 5001 Default Configuration, TP1 = +25°C Efficiency Power Dissipation [%] [W] 100 4.0 95 VI 90 3.0 VI 5V 5V 2.0 85 12 V 12 V 80 14 V 14 V 1.0 75 0.0 70 0 3 6 9 12 0 15 [A] 3 6 9 12 Efficiency vs. load current and input voltage. Dissipated power vs. load current and input voltage. Output Current Derating Current Limit Characteristics 15 [A] [A] [V] 15 3.5 3.0 12 VI 3.0 m/s 2.5 2.0 m/s 9 2.0 5V 1.5 12 V 1.0 14 V 1.0 m/s 6 0.5 m/s Nat. Conv. 3 0.5 0.0 19 0 75 80 85 90 95 100 20 21 22 23 24 25 [A] [°C] Available load current vs. ambient air temperature and airflow at VI = 12 V. See section Thermal Consideration. Output voltage vs. load current and input voltage. Output Ripple and Noise Transient Response Fundamental output voltage ripple at VI = 12 V, CO = 3x100 µF, IO =15 A. Scale: 5 mV/div, 1 µs/div, 20 MHz bandwidth. See section Output Ripple and Noise. Output voltage response to load current step change (4.5–13.5–4.5 A) at VI = 12 V, CO = 3x100 µF + 270 µF/10mΩ. Default compensation settings. Scale: 50 mV/div, 5 A/div, 100 µs/div. 41 INTERNAL USE ONLY PRODUCT SPECIFICATION Prepared (Subject resp) 2/1301-BMR 461 Uen Technical Specification JIDDASUN Dan Sun Approved (Document resp) 38 (40) No. Checked BMR461 series PoL Regulators jidlliaa Lisa Li Input 4.5-14 V, Output up to 18 A / 60 W Date Rev 8/30/2019 1/28701-BMR 461 Rev. K L © Flex Typical Characteristics, start up sequence BMR 461 5001 Default Configuration, TP1 = +25°C Start-up by input source Shut-down by input source VI VI VO VO PG PG Start-up enabled by applying VI. TON_DELAY = TON_RISE = 10 ms (default). VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 10 or 1 V/div, 10 ms/div. Vout=1.8V Shut-down by removing VI. VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 10 or 1 V/div, 1 ms/div. Vout=1.8V Start-up by CTRL signal Shutdown by CTRL signal CTRL CTRL VO VO PG PG Start-up enabled by CTRL signal. TON_DELAY = TON_RISE = 10 ms (default). VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 2 or 1 V/div, 10 ms/div. Vout=1.8V Start-up by input source with PG pull up to external source Shut-down by CTRL signal. VI = 12 V, IO = max IO, PG pulled up to VO. Scale: 2 or 1 V/div, 1 ms/div. Vout=1.8V Shutdown by CTRL signal VIN VIN VO VO PG PG Start-up enabled by applying Vin. TON_DELAY = TON_RISE = 10 ms (default). VI = 12 V, IO = max IO, PG pulled up to external 3.3V. Scale: 10 or 5 V/div, 10 ms/div. Vout=3.3V November 2019 Shut-down by removing Vin. VI = 12 V, IO = max IO, PG pulled up to external 3.3V. Scale: 10 or 5 V/div, 1 ms/div. Vout=3.3V 42 Ericsson Internal PRODUCT SPECIFICATION 1 (16) No. 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W EMC Specification Conducted EMI is measured according to the test set-up below. The fundamental switching frequency is 600 kHz. VI = 12 V, VO = 1.8 V, IO = 18 A. Conducted EMI Input terminal value (typical for default configuration). Date Rev Specification Reference November 2019 461 Rev. K 2015-12-2429 1/28701-BMR E © Flex Output Ripple and Noise Output ripple and noise is measured according to figure below. A 50 mm conductor works as a small inductor forming together with the two capacitances a damped filter. 50 mm conductor Vout +S co Tantalum Capacitor 10 µF Ceramic Capacitor 0.1 µF −S GND Load Prepared (also subject responsible if other) 50 mm conductor BNC-contact to oscilloscope Output ripple and noise test set-up. EMI without filter. To spectrum analyzer RF Current probe 1kHz – 50MHz Battery supply The digital compensation of the product is designed to automatically provide stability, accurate line and load regulation and good transient performance for a wide range of operating conditions (switching frequency, input voltage, output voltage, output capacitance). Inherent from the implementation and normal to the product there will be some low-frequency noise or wander at the output, in addition to the fundamental switching frequency output ripple. The total output ripple and noise is maintained at a low level. Resistive load DUT C1 50mm C1 = 10uF / 600VDC Feed- Thru RF capacitor 800mm 200mm VI=12 V, VO=3.3 V, IO=12 A, CO=3x100 µF,10 mV/div, 50 µs/div Example of low frequency noise at the output. Test set-up conducted emission, power lead Layout Recommendations The radiated EMI performance of the product will depend on the PWB layout and ground layer design. It is also important to consider the stand-off of the product. If a ground layer is used, it should be connected to the output of the product and the equipment ground or chassis. A ground layer will increase the stray capacitance in the PWB and improve the high frequency EMC performance. 43 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Operating Information Power Management Overview This product is equipped with a PMBus interface. The product incorporates a wide range of readable and configurable power management features that are simple to implement with a minimum of external components. Additionally, the product includes protection features that continuously safeguard the load from damage due to unexpected system faults. A fault is also shown as an alert on the SALERT pin. The product is delivered with a default configuration suitable for a wide range of operation in terms of input voltage, output voltage, and load. The configuration is stored in an internal Non-Volatile Memory (NVM). All power management functions can be reconfigured using the PMBus interface. Please contact your local Flex representative for design support of custom configurations or appropriate SW tools for design and download of your own configurations. Input Under Voltage Lockout, UVLO The product provides a non-configurable under voltage lockout (UVLO) circuit that monitors the internal supply of the converter. Below a certain input voltage level the internal supply will be too low for proper operation and the product will be in under voltage lockout, not switching or responding to the CTRL pin or to PMBus commands. Input Over Voltage Lockout, OVLO The product provides a non-configurable over voltage lockout (OVLO) circuit that will shut down the product when the input voltage rises above a certain level. The product will not switch, respond to the CTRL pin or to PMBus commands when being in over voltage lockout. Input Turn-On and Turn-Off Voltage The product monitors the input voltage and will turn-on and turn-off the output at configured levels (assuming the product is enabled by CTRL pin or PMBus). The default turn-on input voltage level is 4.35 V whereas the corresponding turn-off input voltage level is 3.8 V. The turn-on and turn-off levels may be reconfigured using the PMBus commands VIN_ON and VIN_OFF. Input Under Voltage Protection (IUVP) The product monitors the input voltage continously and will respond as configured when the input voltage falls below the configured threshold level. The product can respond in a number of ways as follows: 1. 2. 3. 2 (16) No. Continue operating without interruption. Continue operating for a given delay period, followed by an output voltage shutdown if the fault still exists. Immediate and definite shutdown of output voltage until the fault is cleared by PMBus or the output voltage is reenabled. Date Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex 4. Immediate shutdown of output voltage while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. The default response is 4. The IUVP function can be reconfigured using the PMBus commands VIN_UV_FAULT_LIMIT and VIN_UV_FAULT_RESPONSE. Input Over Voltage Protection (IOVP) The product monitors the input voltage continously and will respond as configured when the input voltage rises above the configured threshold level. Refer to section “Input Under Voltage Protection” for response configuration options and default setting. Input and Output Impedance The impedance of both the input source and the load will interact with the impedance of the product. It is important that the input source has low characteristic impedance. If the input voltage source contains significant inductance, the addition of a capacitor with low ESR at the input of the product will ensure stable operation. External Input Capacitors The input ripple RMS current in a buck converter can be estimated to Eq. 1. I inputRMS = I load D(1 − D ) , where I load is the output load current and D is the duty cycle. The maximum load ripple current becomes I load 2 . The ripple current is divided into three parts, i.e., currents in the input source, external input capacitor, and internal input capacitor. How the current is divided depends on the impedance of the input source, ESR and capacitance values in the capacitors. For most applications non-tantalum capacitors are preferred due to the robustness of such capacitors to accommodate high inrush currents of systems being powered from very low impedance sources. It is recommended to use a combination of ceramic capacitors and low-ESR electrolytic/polymer bulk capacitors. The low ESR of ceramic capacitors effectively limits the input ripple voltage level, while the bulk capacitance minimizes deviations in the input voltage at large load transients. It is recommended to use at least 47 uF of ceramic input capacitance. At duty cycles between 25% and 75% where the input ripple current increases (see Eq. 1), additional ceramic capacitance will help to keep the input ripple voltage low. The required bulk capacitance depends on the impedance of the input source and the load transient levels at the output. In general a low-ESR bulk capacitor of at least 100 uF is recommended. The larger the duty cycle is, the larger impact an output load step will have on the input side, thus the larger bulk capacitance is required to limit the input voltage deviation. If several products are connected in a phase spreading setup the amount of input capacitance per product can be reduced. 44 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 30/1301-BMR 461Technical Uen EYIZJIA Approved 3 (16) No. Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Input Capacitors must be placed closely and with low impedance connections to the VIN and GND pins in order to be effective. External Output Capacitors The output capacitor requirement depends on two considerations; output ripple voltage and load transient response. To achieve low ripple voltage, the output capacitor bank must have a low ESR value, which is achieved with ceramic output capacitors. A small output voltage deviation during load transients is achieved by using a larger amount of capacitance. Designs with smaller load transients can use fewer capacitors and designs with more dynamic load content will require more load capacitors to achieve a small output deviation. Improved transient response can also be achieved by adjusting the settings of the control loop of the product (see section Compensation Implementation). It is recommended to locate low ESR ceramic and low ESR electrolytic/polymer capacitors as close to the load as possible, using several capacitors in parallel to lower the effective ESR. It is important to use low resistance and low inductance PCB layouts and cabling in order for capacitance to be effective. The control loop of the product is optimized to operate with low-ESR output capacitors and can achieve a fast loop transient response with a reduced amount of capacitance. However, it should be noted that the power stage resonance frequency FLC (FLC/Fsw) is limited to the range of 1/66 to 1/25. Using too high or low capacitive load will get FLC is saturated with value 1/25 or 1/66 and the loop performance will be impacted. Please contact your Flex sales representative for further support. Using different Vout and Iout values could impact the Cout_DCbias and L_saturation values, and the FLC can be greatly affected. It’s therefore recommended to read the ratio_flc to verify that only the LSB varies, and that the MSB is somewhere in the middle of [25,66]. Dynamic Loop Compensation (DLC) The typical design of regulated power converters includes a control function with a feedback loop that can be closed using either analog or digital circuits. The feedback loop is required to provide a stable output voltage, but should be optimized for the output filter to maintain output voltage regulation during transient conditions such as sudden changes in output current and/or input voltage. Digitally controlled converters allow one to optimize loop parameters without the need to change components on the board, however, optimization can still be challenging because the key parameters of the output filter include parasitic impedances in the PCB and the often distributed filter components themselves. Date Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex Dynamic Loop Compensation has been developed to solve the problem of compensation for a converter with a difficult to define output filter. This task is achieved by utilization of algorithms that can characterize an arbitrary output filter based on behavior of the output voltage in response to a disturbance initiated by the algorithm, or occurring due to the changes in operating conditions, and automatically adjust feedback loop parameters to match the output filter. Details of the algorithm that is used to characterize an output filter and the different operational modes can be found in the following sections. Compensation Implementation Unlike PID-based digital power regulators the product uses a state-space model based algorithm that is valid for both the small- and large-signal response and accounts for duty-cycle saturation effects. This eliminates the need for users to determine and set thresholds for transitioning from linear to nonlinear modes. These capabilities result in fast loop transient response and the possibility of reducing the number of output capacitors. Compensation calibration is when the resonance frequency FLC of the output stage is measured. The FLC value is used to automatically control the compensation. During ramp-up of the output voltage, robust and low bandwidth default compensation settings are used based on the default FLC value assigned by bits 15:0 in PMBus command COMP_MODEL. If the switching frequency is changed the default FLC should be adjusted according to Eq. 4 to maintain robust settings. Eq. 4. FLC _ DEFAULT = FSW 32 It is possible for the user to write any FLC value in COMP_MODEL to be used during ramp-up. This is useful in cases where improved dynamic performance is needed during ramp-up. User assignment of FLC in COMP_MODEL is also needed when calibration is disabled, since in such case the FLC value used during ramp-up will continue to be used when ramp-up has finished. When calibration is enabled (default), an AC low amplitude measurement signal is applied on the output immediately after ramp-up has finished. See Electrical Characteristics table for a specification of this measurement signal. During calibration the resonant frequency FLC of the power stage is measured. From the result an internal non-linear model is constructed to optimize the bandwidth and transient response of the product. Pole locations of the closed system are automatically selected based on switching frequency, measured FLC and the output voltage level. After each performed calibration, bits 15:0 in COMP_MODEL are updated with measured FLC, thus this value can be read out by the user. Note however, as soon as the output voltage is disabled, the FLC value in COMP_MODEL will revert back to 45 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W the corresponding value stored in User NVM. Therefore, user values of COMP_MODEL should be written to NVM, or, if written to RAM only, be written before each time the output voltage is enabled. COMP_MODEL should only be changed in RAM while the output voltage is disabled. By setting bit 2 in ADAPTIVE_MODE a STORE_USER_ALL command will automatically be performed after the next calibration, effectively storing the measured FLC value in COMP_MODEL 15:0 in NVM as the FLC value for subsequent ramp-ups. Output Voltage 4 (16) No. Compensation calibration Date Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex 5. Calibration is performed continuously in response to a PMBus command. Controlled by setting/clearing bit 8 in ADAPTIVE_MODE during operation. Compensation may be set more or less aggressive by adjusting the feedback gain factor, controlled by the PMBus command FEEDBACK_EFFORT. This parameter is proportional to the open loop gain of the system. Increasing the gain, i.e the control effort, will reduce the voltage deviation at load transients, at the expense of somewhat increased jitter and noise on the output. Users also have access to the PMBus command ZETAP, which corresponds to the damping ratio of the closed loop system. By default the product uses 0.5 as the feedback gain factor and 1.5 for damping ratio, to target a system bandwidth of 10% of the switching frequency. In some operating conditions at low output voltages, it is possible to enhance the recovery time at load release by enabling Negative Duty Cycle by PMBus command LOOP_CONFIG. Time Below table shows an example of improvement in transient response due to the compensation calibration, compared to using the FLC_DEFAULT value. Below graphs exemplify the impact on load transient performance when adjusting the feedback gain factor, the damping ratio and the Negative Duty Cycle feature. [mV] 70 60 Non-calibrated compensation Calibrated compensation 50 Voltage deviation 53 mV 34 mV 40 Recovery time 50 µs 30 µs 30 Load transient performance non-calibrated compensation with FLC_DEFAULT vs. calibrated compensation. VI=12 V, VO=1.2 V, CO = 3x100 µF + 270µF/10mΩ, load step 3-9-3 A, 1 A/us. 20 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FEEDBACK_EFFORT CO=3x100µF+270µF/10mΩ CO=3x100µF VI=12 V, VO=1.2 V, load step 3-9-3 A,1 A/us. Voltage deviation vs. FEEDBACK_EFFORT setting. The PMBus command ADAPTIVE_MODE provides the user different options for compensation calibration: 1. Calibration is performed once after each ramp-up (default). (ADAPTIVE_MODE = 0x024B). 2. Calibration is performed once after first ramp-up after input voltage is applied (ADAPTIVE_MODE = 0x124B). 3. Calibration is performed continuously after ramp-up at ~800 ms interval (ADAPTIVE_MODE = 0x034B). 4. Calibration is disabled (ADAPTIVE_MODE = 0x004B). The FLC value stored in bits 15:0 in COMP_MODEL will be applied. 1.0 46 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 5 (16) No. 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W [us] Date Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex 21.0 Output Voltage Control To control the output voltage the product features both a remote control input through the CTRL pin and a PMBus enable function by the command OPERATION. It is also possible to configure the output to be always on. By default the output is controlled by the CTRL pin only. The output voltage control can be reconfigured using the PMBus command ON_OFF_CONFIG. 18.0 Remote Control 30.0 27.0 24.0 15.0 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 Vext ZETAP VI=12 V, VO=1.2 V, CO = 3x100 µF + 270µF/10mΩ, load step 3-9-3 A,1 A/us. CTRL Recovery time to within 1% of VO vs. ZETAP setting. GND Disabled Enabled VI=12 V, VO=0.6 V, CO = 3x100 µF + 270µF/10mΩ, load step 3-9-3 A,1 A/us. FEEDBACK_EFFORT = 0.8, ZETAP = 1.5. Scale: 20 mV/div, 5 A/div, 10 µs/div. Load release response at enabled/disabled Negative Duty Cycle at low output voltage. The product is equipped with a remote control function, i.e., the CTRL pin. The remote control can be connected to either the primary negative input connection (GND) or an external voltage (Vext). See Absolute Maximum Rating for maximum voltage level allowed at the CTRL pin. The CTRL function allows the product to be turned on/off by an external device like a semiconductor or mechanical switch. The CTRL pin has an internal 6.8 kΩ pull-up resistor to 3.3 V. The external device must provide a minimum required sink current to guarantee a voltage not higher than the logic low threshold level (see Electrical Characteristics). When the CTRL pin is left open, the voltage generated on the CTRL pin is 3.3 V. By default the product provides “positive logic” RC and will turn on when the CTRL pin is left open and turn off when the CTRL pin is applied to GND. It is possible to configure “negative logic” instead by using the PMBus command ON_OFF_CONFIG. If the device is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the CTRL pin. Output Voltage Adjust using Pin-strap Resistor Remote Sense Using an external Pin-strap The product has remote sense that can be used to resistor, RSET, the output voltage compensate for voltage drops between the output and the point can be set in the range 0.6 V to VSET of load. The sense traces should be located close to the PWB 5.0 V at 16 different levels ground layer to reduce noise susceptibility. Due to derating of RSET shown in the table below. The internal output capacitance the voltage drop should be kept PREF resistor should be applied below VDROPMAX = (5.25 – VOUT) / 2. A large voltage drop will between the VSET pin and the impact the electrical performance of the regulator. If the remote PREF pin. sense is not needed +S must be connected to VOUT and −S must be connected to GND. RSET also sets the maximum output voltage; see section “Output Voltage Range Limitation”. The resistor is sensed only at the application of input voltage. Changing the resistor value during normal operation will not change the output voltage. The input voltage must be at least 1 V larger than the output voltage in order to deliver the correct output voltage. See Ordering Information for output voltage range. 47 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W The following table shows recommended resistor values for RSET. Maximum 1% tolerance resistors are required. RSET[kΩ] VOUT [V] 0.60 5.11 1.05 17.8 0.70 6.19 1.10 21.5 0.75 7.15 1.20 26.1 0.80 8.25 1.50 31.6 0.85 9.53 1.80 38.3 0.90 11.0 2.50 44.2 0.95 12.7 3.30 51.1 1.00 14.7 5.00 59.0 VOUT [V] 6 (16) No. RSET[kΩ] Leaving VSET open will produce an output voltage of 0 V. Using an RSET ≤ 4.22 kΩ will put the product in track mode, see section Voltage Tracking. Output Voltage Adjust using PMBus The output voltage set by pin-strap can be overridden using the PMBus command VOUT_COMMAND. See Electrical Specification for adjustment range. Voltage Margining Up/Down Using the PMBus interface it is possible to adjust the output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. This provides a convenient method for dynamically testing the operation of the load circuit over its supply margin or range. It can also be used to verify the function of supply voltage supervisors. Margin limits of the nominal output voltage ±5% are default, but the margin limits can be reconfigured using the PMBus commands VOUT_MARGIN_LOW, VOUT_MARGIN_HIGH. Margining is activated by the command OPERATION. Output Voltage Trim The actual output voltage can be trimmed to optimize performance of a specific load by setting a non-zero value for PMBus command VOUT_TRIM. The value of VOUT_TRIM is summed with VOUT_COMMAND, allowing for multiple products to be commanded to a common nominal value, but with slight adjustments per load. Output Voltage Range Limitation The output voltage is by default limited to the least of 5.5 V or 110% of the nominal output voltage, where the nominal output voltage is defined by pin-strap or by VOUT_COMMAND in Non-Volatile Memory (see section Initialization Procedure). This protects the load from an over voltage due to an accidentally written wrong VOUT_COMMAND. The limitation applies to the regulated output voltage, rather than the internal value of VOUT_COMMAND. The output voltage limit can be reconfigured using the PMBus command VOUT_MAX. Date Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex Output Over Voltage Protection (OVP) The product includes over voltage limiting circuitry for protection of the load. The default OVP limit is 15% above the nominal output voltage. The product can be configured to respond in different ways to the output voltage exceeding the OVP limit: 1. 2. 3. 4. Continue operating without interruption. Continue operating for a given delay period, followed by an output voltage shutdown if the fault still exists. Immediate and definite shutdown of output voltage until the fault is cleared by PMBus or the output voltage is reenabled. Immediate shutdown of output voltage while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. The default response is 4. The OVP limit and fault response can be reconfigured using the PMBus commands VOUT_OV_FAULT_LIMIT and VOUT_OV_FAULT_RESPONSE. Output Under Voltage Protection (UVP) The product includes output under voltage limiting circuitry for protection of the load. The default UVP limit is 15% below the nominal output voltage. Refer to section “Output Over Voltage Protection” for response configuration options and default setting. Power Good PG (Power Good) is an active high open drain output used to indicate when the product is ready to provide regulated output voltage to the load. During startup and during a fault condition, PG is held low. By default, PG is asserted high after the output has ramped to a voltage above 90% of the nominal voltage and a successful compensation calibration has completed. By default, PG is deasserted if the output voltage falls below 85% of the nominal voltage. These limits may be changed using the PMBus commands POWER_GOOD_ON and POWER_GOOD_OFF. The PG output is not defined during ramp up of the input voltage due to the initialization of the product. Over Current Protection (OCP) The product includes robust current limiting circuitry for protection at continuous overload. After ramp-up is complete the product can detect an output overload/short condition. The following OCP response options are available: 1. 2. 3. Continue operating without interruption (this could result in permanent damage to the product). Immediate and definite shutdown of output voltage until the fault is cleared by PMBus or the output voltage is reenabled. Immediate shutdown of output voltage followed by continous restart attempts of the output voltage with a preset interval (“hiccup” mode). 48 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W The default response from an over current fault is 3. Note that delayed shutdown is not supported. The load distribution should be designed for the maximum output short circuit current specified. The OCP limit and response can be reconfigured using the PMBus commands IOUT_OC_FAULT_LIMIT and IOUT_OC_FAULT_RESPONSE. If option 2 above is to be used, the TON_MAX_FAULT_RESPONSE setting should match the setting of IOUT_OC_FAULT_RESPONSE in order to make sure that no restart attempts occur. Switching Frequency The default switching frequency yields optimal performance. The switching frequency can be re-configured in a certain range using the PMBus command FREQUENCY_SWITCH. Refer to Electrical Specification for default switching frequency and range. If changing the switching frequency more than +/-10% from the default value, the following should be considered to maintain reliable operation: • • 7 (16) No. The default FLC value in COMP_MODEL should be adjusted, see section Compensation Implementation. Adjustment of the fixedDTR and fixedDTF values in DEADTIME_GCTRL may be required, for higher switching frequencies in particular. Changing the switching frequency will affect efficiency/power dissipation, load transient response and output ripple. Synchronization The product may be synchronized with an external clock to eliminate beat noise on the input and output voltage lines by connecting the clock source to the SYNC pin. Synchronization can also be utilized for phase spreading, described in section Phase Spreading. The clock frequency of the external clock source must be stable prior to enabling the output voltage. Further, the PMBus command FREQUENCY_SWITCH must be set to a value close to the frequency of the external clock prior to enabling the output voltage, in order to set the internal controller in proper operational mode. The product automatically checks for a clock signal on the SYNC pin when input power is applied and when the output is enabled. If no incoming clock signal is present, the product will use the internal oscillator at the configued switching frequency. In the event of a loss of the external clock signal during normal operation, the product will automatically switch to the internal oscillator and switch at a frequency close to the original SYNC input frequency. Phase Spreading When multiple products share a common DC input supply, spreading of the switching clock phase between the products Date Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex can be utilized. This dramatically reduces input capacitance requirements and efficiency losses, since the peak current drawn from the input supply is effectively spread out over the whole switch period. This requires that the products are synchronized. The phase offset is measured from the rising edge of the applied external clock to the center of the PWM pulse as illustrated below. SYNC clock Phase offset = 120° PWM pulse (VO/VI = 0.33) Illustration of phase offset. By default the phase offset is controlled by the defined PMBus address (see section PMBus Interface) according to the table below. This provides a way to configure phase spreading with up to eight different phase positions without using a PMBus command. Set PMBus address Phase offset xxxx000b 0° xxxx001b 60° xxxx010b 120° xxxx011b 180° xxxx100b 240° xxxx101b 300° xxxx110b 90° xxxx111b 270° The default phase offset can be overridden by using the standard PMBus command INTERLEAVE. The phase offset can then be defined as Phase _ offset (°) = 360° × Interleave _ order Number _ in _ group Interleave_order is in the range 0-15. Number_in_group is in the range 0-15 where a value of 0 means 16. The set resolution for the phase offset is 360° / 128 ≈ 2.8°. Giving the PMBus command INTERLEAVE a value of 0x0000 will revert back to the default address controlled phase offset. 49 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 8 (16) No. 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Date Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex Flex provides software tools for convenient configuration of optimized phase spreading, allowing the amount of input capacitance to be significantly reduced. Vout related PMBus command Loaded value unless explicitly written + stored to User NVM. POWER_GOOD_ON 0.90 x loaded Vout level Initialization Procedure The product follows an internal initialization procedure after power is applied to the VIN pin (refer to figure below): POWER_GOOD_OFF 0.85 x loaded Vout level VOUT_MAX 1.10 x loaded Vout level VOUT_MARGIN_HIGH 1.05 x loaded Vout level 1. Self test and memory check. 2. The address pin-strap resistors are measured and the associated PMBus address is defined. 3. The output voltage pin-strap resistor is measured. The associated output voltage level will be loaded into operational RAM memory, unless an overriding PMBus command VOUT_COMMAND has been explicitly written and stored in the User Non-Volatile Memory (indicated by bit 0 in command STRAP_DISABLE). 4. Values stored in the User Non-Volatile Memory (NVM) are loaded into operational RAM memory. For PMBus commands listed in the table below, loaded values will be based on the output voltage level loaded in step 3 above, unless the commands have been explicitly written and stored in the User NVM. 5. Check for external clock signal at the SYNC pin and wait for lock if used. VOUT_MARGIN_LOW 0.95 x loaded Vout level VOUT_OV_FAULT_LIMIT 1.15 x loaded Vout level VOUT_UV_FAULT_LIMIT 0.85 x loaded Vout level Soft-start and Soft-stop The soft-start and soft-stop control functionality allows the output voltage to ramp-up and ramp-down with defined timing with respect to the control of the output. This can be used to control inrush current and manage supply sequencing of multiple controllers. The rise time is the time taken for the output to ramp to its target voltage while the fall time is the time taken for the output to ramp down from its regulation voltage to less than 10% of that value. The on delay time sets a delay from when the output is enabled until the output voltage starts to ramp up. The off delay time sets a delay from when the output is disabled Once this procedure is completed and the initialization time has until the output voltage starts to ramp down. passed (see Electrical Specification), the output voltage is ready to be enabled and the PMBus interface can be used. Output control Pin-strap VOUTRSET NO STRAP_DISABLE[0]=1? On delay time RAM VOUT_COMMAND Rise time Off delay time Fall time YES User NVM VOUT_COMMAND VOUT READ Illustration of Soft-Start and Soft-Stop WRITE PMBus Interface VOUT_COMMAND STRAP_DISABLE[0]=1 Loading of nominal output voltage level. Note the following implications of the initialization procedure: • If the RSET pin-strap resistance is changed, input voltage will have to be cycled before the output voltage level is affected. • If VOUT_COMMAND is changed and stored to User NVM, input voltage will have to be cycled before the output voltage related commands in the table below are re-scaled according to the new output voltage level. See section PMBus Interface for more information about the Non-Volatile Memories (NVM) of the product. Soft-stop is disabled by default but may be enabled through the PMBus command ON_OFF_CONFIG. The delay and ramp times can be reconfigured using the PMBus commands TON_DELAY, TON_RISE, TOFF_DELAY and TOFF_FALL. The internal delay generator can only achieve certain discrete timing values. A written TON_DELAY/TOFF_DELAY value will be rounded to the closest achievable value, thus a TON_DELAY/OFF_DELAY read will provide the actual set value. The internal ramp generator can only achieve certain discrete timing values for a given combination of switch frequency, output voltage level, set ramp time and trim data. These values are close, but not exactly the same, when any of the relevant parameters are altered. A written TON_RISE/TOFF_FALL value will be rounded to the closest achievable value, thus a TON_RISE/TOFF_FALL read will provide the actual set value. 50 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 9 (16) No. 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Refer to Electrical Specification for default on delay time and rise time and the configurability ranges and resolutions. The specification provided for soft-start applies also for soft-stop, if enabled. Output Voltage Sequencing A group of products may be configured to power up in a predetermined sequence. This feature is especially useful when powering advanced processors, FPGAs, and ASICs that require one supply to reach its operating voltage prior to another. Multi-product sequencing can be achieved by configuring the start delay and rise time of each device through the PMBus interface and by connecting the CTRL pin of each product to a common enable signal. Date Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex Voltage Tracking The product supports tracking of the output from a master voltage applied to the CS_VTRK pin. To select the tracking mode, a resistance ≤ 4.22 kΩ must be connected between the VSET and PREF pins. The tracking ratio used is controlled by an internal feedback divider RDIV and an external resistive voltage divider (R1, R2) which is placed from the supply being tracked to GND pins. VTRACK (MASTER) BMR 461 R2 max 1.2V Voltage CS_VTRK RDIV VOUT (SLAVE) VSET R1 VOUT RSET VOUT1 PREF VOUT2 GND RSET ≤ 4.22 kΩ Tracking Mode Configuration Time In tracking mode the output voltage is regulated to the lower of: Illustration of Output Voltage Sequencing. VOUT = Pre-Bias Startup Capability Pre-bias startup often occurs in complex digital systems when current from another power source is fed back through a dualsupply logic component, such as FPGAs or ASICs. The product incorporates synchronous rectifiers, but will not sink current during startup, or turn off, or whenever a fault shuts down the product in a pre-bias condition. When the output is enabled the product checks the output for the presence of pre-bias voltage. If the pre-bias voltage is above the output overvoltage threshold the product will not attempt soft-start. If the pre-bias voltage is less than 200 mV the soft-start is performed assuming no pre-bias. If the pre-bias voltage is above 200 mV but below target output voltage, the product ramps up the output voltage from the pre-bias voltage to the target regulation as shown in the figure below. Voltage Soft-start ramp time Eq. 5 VTRACK R1 × RDIV R1 + R 2 or the output voltage defined by the PMBus command VOUT_COMMAND. RDIV is automatically selected based on the value of VOUT_COMMAND as shown in the table below. If VOUT_COMMAND is not defined by the user, it will default to 5.25 V with RDIV= 0.20272. VOUT_COMMAND [V] < 0.99 0.99547 0.99 to < 1.12 0.88222 1.12 to < 1.28 0.76897 1.28 to < 1.50 0.65572 1.50 to < 1.82 0.54247 1.82 to < 2.29 0.42922 2.29 to < 3.12 0.31597 3.12 to < 5.25 0.20272 VOUT_COMMAND not user defined => 5.25 Time Illustration of Pre-Bias Startup RDIV 0.20272 For best tracking accuracy it is recommended that once the product is powered up, the VOUT_COMMAND should not be changed so as to cause a change to the operational RDIV. If such a change in VOUT_COMMAND is required, the user 51 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W should save the new value to User Non-Volatile Memory (using STORE_USER_ALL command) and recycle the input voltage to set a new RDIV operational value. To simplify resistor selection it is recommended to fix R1 at 10 kΩ and use the following equation to determine R2:   VTRACK R 2(kΩ) = R1 ×  − 1   RDIV × VOUT Eq. 6 R2 must be chosen so that the CS_VTRK input does not exceed 1.2 V. As seen in Eq. 5, if the resistor-divider ratio from R1//R2 is chosen such that it is equal to the operational RDIV, the output voltage follows the tracking voltage coincidentally. For all other cases, the output voltage follows a ratiometric tracking. These two modes of tracking are further described below. 1. Coincident tracking. Output voltage is ramped at the same rate as the VTRACK voltage. To achieve coincident tracking the desired output voltage should be set by the PMBus command VOUT_COMMAND. R2 should be set so that R2 = R1 / RDIV – R1. The output will stop ramping when the VOUT_COMMAND level is reached. Since the voltage at the CS_VTRK pin must be below 1.2 V, coincident tracking will not be possible in all cases. A higher R2 value may be required, giving a ratiometric tracking instead. Voltage R1 / (R1 + R2) = RDIV VTRACK VOUT_ COMMAND 10 (16) No. Date Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex 2. Ratiometric tracking. Output voltage is ramped at a rate that is a percentage of the VTRACK voltage. To achieve ratiometric tracking, R2 should be set according to Eq. 6 with VOUT being the desired output voltage. The PMBus command VOUT_COMMAND should be set equal to or higher than the output voltage given by Eq. 5, or not being set at all giving the default VOUT_COMMAND value 5.25 V. Since the target voltage level is decided by the R1//R2 divider there will be a small regulation inaccuracy due to the tolerance of the resistors. Note also that VOUT will be higher than VTRACK if R1 / (R1 + R2) > RDIV. Voltage R1 / (R1 + R2) < RDIV VT RACK VTRACK R1 × RDIV R1 + R 2 V OUT Time Ratiometric Voltage Tracking Example: External VTRACK = 3.3 V Target VOUT = 1.3 V VOUT_COMMAND not set => RDIV = 0.20272 R1 = 10 kΩ   3.3 R 2 = 10 ×  − 1 = 115kΩ  0.20272 × 1.3    Eq. 6 => VOUT Time Coincident Voltage Tracking Example: External VTRACK = 3.3 V Target VOUT = 2.5 V R1 = 10 kΩ VOUT_COMMAND = 2.5 V => RDIV = 0.31597 R2 = 10 / 0.31597– 10 = 21.6 kΩ During voltage tracking compensation calibration is triggered when the output voltage is above 450 mV and stable within a 100 mV window for two consecutive measurements at 10 ms intervals. When calibration is complete, the power good (PG) output is asserted. The PG output remains asserted until the output voltage falls below 450 mV, as verified at 10 ms intervals. For this reason, the PG output may remain high for as much as 10 ms after the output voltage has fallen below 450 mV. When voltage tracking is enabled the output over voltage protection limit is set 12% above VOUT_COMMAND as default. This limit may be reconfigured using the PMBus command VOUT_OV_FAULT_LIMIT. Output under voltage protection is not functional in tracking mode. Soft-start parameters TON_DELAY and TON_RISE are not functional in tracking mode and will be set to their minimum values to prevent interference with tracking. TOFF_DELAY and TOFF_FALL can be used if soft-stop is enabled. In such case the output voltage will follow the least of the output levels given by the soft-stop parameters and the tracking equations. 52 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 12 (16) No. 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Date Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex Thermal Consideration General The product is designed to operate in different thermal environments and sufficient cooling must be provided to ensure reliable operation. Cooling is achieved mainly by conduction, from the pins to the host board, and convection, which is dependent on the airflow across the product. Increased airflow enhances the cooling of the product. The Output Current Derating graph found in the Output section for each model provides the available output current vs. ambient air temperature and air velocity at specified VI. The product is tested on a 254 x 254 mm, 35 µm (1 oz), test board mounted vertically in a wind tunnel with a cross-section of 608 x 203 mm. The test board has 8 layers. Proper cooling of the product can be verified by measuring the temperature at positions P1, P2 and P3. The temperature at these positions should not exceed the max values provided in the table below. Note that the max value is the absolute maximum rating (non destruction) and that the electrical Output data is guaranteed up to TP1 +95°C. See Design Note 019 for further information. Definition of Product Operating Temperature The product operating temperature is used to monitor the temperature of the product. Proper thermal conditions can be verified by measuring the temperature at positions P1, P2 and P3. The temperature at these position (TP1,TP2, TP3) should not exceed the maximum temperatures in the table below. The number of measurement points may vary with different thermal design and topology. Position Description Max Temperature P1 FET Reference point 125°C * P2 L1, Inductor 125°C * (115°C **) P3 N1, Control circuit 115°C * * A guard band of 5 °C is applied to the maximum recorded component temperatures when calculating output current derating curves. ** See section Alternative thermal verification. AIR FLOW P2 P1 P3 Temperature positions and air flow direction. Top view. Definition of Reference Temperature TP1 The reference temperature is used to monitor the temperature limits of the product. Temperature above maximum TP1, measured at the reference point P1 is not allowed and may cause degradation or permanent damage to the product. TP1 is also used to define the temperature range for normal operating conditions. TP1 is defined by the design and used to guarantee safety margins, proper operation and high reliability of the product. Alternative Thermal Verification Since it is difficult to access positions P1 and P3 of the product, measuring the temperature at only position P2 is an alternative method to verify proper thermal conditions. If measuring only TP2 the maximum temperature of P2 must be lowered since in some operating conditions TP1 will be higher than TP2. Using a temperature limit of 115°C for TP2 will make sure that the temperatures at all points P1, P2 and P3 stay below their maximum limits. Over Temperature Protection (OTP) The internal temperature of the product is continously monitored at position P3. When the internal temperature rises above the configured threshold level the product will respond as configured. The product can respond in a number of ways as follows: 1. 2. 3. 4. Continue operating without interruption (this could result in permanent damage to the product). Continue operating for a given delay period, followed by an output voltage shutdown if the fault still exists. Immediate and definite shutdown of output voltage until the fault is cleared by PMBus or the output voltage is reenabled. Immediate shutdown of output voltage while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists. Default response is 4. The OTP protection uses hysteresis so that the fault exists until the temperature has fallen to a certain level (OT_WARN_LIMIT) below the fault threshold. The default OTP threshold and hysteresis are specified in Electrical Characteristics. The OTP limit, hysteresis and response can be reconfigured using the PMBus commands OT_FAULT_LIMIT, OT_WARN_LIMIT and OT_FAULT_RESPONSE. The product also incorporates a non-configurable hard-coded thermal shutdown associated with the temperature monitored at position P3 to ensure long-term flash-memory integrity. See Electrical Characteristics. 53 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Date Rev Pin Designation Function 1A, 1B 2A, 2B, 2C, 2D VOUT Output Voltage 3A, 3B, 4A, 4B, 5A, 5B GND Power Ground 5C, 6A, 6B, 6C VIN Input Voltage 1C +S Positive sense. Connect to output voltage close to the load -S 1E PG 1F SA0 3E SA1 Negative sense. Connect to power ground close to the load. Power Good output. Asserted high when the product is ready to provide regulated output voltage to the load. Open drain. See section Power Good. PMBus address pin strap. Used with external resistors to assign a unique PMBus address to the product. See section PMBus Interface. November 2019 © Flex 2F VSET 3F PREF 6D CTRL 2E SYNC Pin layout, bottom view. Below table gives a brief description of the functionality of each pin. A more detailed description can be found in the different sub sections of the Operating Information section. Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E Connections 1D 13 (16) No. 5F SALERT 6E SDA 6F SCL 4F CS_VTRK 4E RSVD 5D, 5E NC Output voltage pin strap. Used with external resistor to set the nominal output voltage or to select tracking mode. See section Output Voltage Adjust using Pinstrap Resistor. Pin-strap reference. Ground reference for pin-strap resistors. Remote Control. Can be used to enable/disable the output voltage of the product. See section Remote Control. External switching frequency synchronization input. See section Synchronization. PMBus Alert. Asserted low when any of the configured protection mechanisms indicate a fault. PMBus Data. Data signal for PMBus communication. See section PMBus Interface. PMBus Clock. Clock for PMBus communication. See section PMBus Interface. Voltage Tracking input. Allows for tracking of output voltage to an external voltage. See section Voltage Tracking. In normal operation when tracking is not used, this pin must be connected to PREF. Reserved. Connect to PREF. No connection 54 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 14 (16) No. 30/1301-BMR 461Technical Uen EYIZJIA Approved Checked Date BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Rev Specification Reference 461 Rev. K 2015-12-2429 1/28701-BMR E November 2019 © Flex the equipment ground or chassis. A ground layer will increase the stray capacitance in the PCB and improve the high frequency EMC performance. Unused Pins Unused pins should be connected according to the table below. Note that connection of CS_VTRK to PREF is required for normal standalone operation. VSET should always have a pin strap resistor. Further layout recommendations are listed below. • The pin strap resistors, RSET, and RSA0/RSA1 should be placed as close to the product as possible to minimize loops that may pick up noise. • Avoid current carrying planes under the pin strap resistors and the PMBus signals. • The capacitors CI should be placed as close to the input pins as possible. Unused Pin Connection CS_VTRK PREF. Required for normal operation CTRL Open (pin has internal pull-up) RSVD PREF or pulled down to PREF • The capacitors CO should be placed close to the load. SYNC PREF or pulled down to PREF • SA0 PREF or Open The point of output voltage sense should be “downstream” of CO according to figure below. SA1 PREF or Open • SDA Pull-up resistor to voltage 2.7V - 3.6 V SCL Pull-up resistor to voltage 2.7V - 3.6 V PG Open SALERT Open Care should be taken in the routing of the connections from the sensed output voltage to the S+ and S– terminals. These sensing connections should be routed as a differential pair, preferably between ground planes which are not carrying high currents. The routing should avoid areas of high electric or magnetic fields. • If possible use planes on several layers to carry VI, VO and GND. There should be a large number of vias close to the VIN, VOUT and GND pads in order to lower input and output impedances and improve heat spreading between the product and the host board. Typical Application Circuit VIN VIN CI VOUT VOUT +S BMR461 -S CO CTRL L O A D VO SA0 SA1 VSET CO 2.7-3.6 V PREF RSA0 RSA1 SALERT SCL CS_VTRK SDA 3 x RPU = 2.2 kΩ SYNC RSVD GND GND -S +S PG RSET LOAD CI SALERT SCL SDA DGND VI BMR 461 Typical standalone operation with PMBus communication. GND PCB Layout Consideration The radiated EMI performance of the product will depend on the PCB layout and ground layer design. If a ground layer is used, it should be connected to the output of the product and RSA0, RSET, RSA1 Layout guidelines. SCL SDA SYNC 55 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 31/1301-BMR 461Technical EYIZJIA Approved 1 (6) No. Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Date Rev Specification Reference 461 Rev. K 2015-12-2408 1/28701-BMR F November 2019 © Flex PMBus Interface This product provides a PMBus digital interface that enables the user to configure many aspects of the device operation as well as to monitor the input and output voltages, output current and device temperature. The product can be used with any standard two-wire I2C or SMBus host device. In addition, the product is compatible with PMBus version 1.1 and includes an SALERT line to help mitigate bandwidth limitations related to continuous fault monitoring. The PMBus signals, SCL, SDA and SALERT require passive pull-up resistors as stated in the SMBus Specification. Pull-up resistors are required to guarantee the rise time as follows: τ = RP C p ≤ 1µs where Rp is the pull-up resistor value and Cp is the bus loading. The maximum allowed bus load is 400 pF. The pull-up resistor should be tied to an external supply voltage in range from 2.7 to 3.6 V, which should be present prior to or during power-up. If the proper power supply is not available, voltage dividers may be applied. Note that in this case, the resistance in the equation above corresponds to parallel connection of the resistors forming the voltage divider. See application note AN304 for details on interfacing the product with a microcontroller. Monitoring via PMBus It is possible to monitor a wide variety of parameters through the PMBus interface. Fault conditions can be monitored using the SALERT pin, which will be asserted when any number of pre-configured fault or warning conditions occur. It is also possible to continuously monitor one or more of the power conversion parameters including but not limited to the following: • • • • • • Input voltage (READ_VIN) Output voltage (READ_VOUT) Output current (READ_IOUT) Internal junction temperature (READ_TEMPERATURE_1) Switching frequency (READ_FREQUENCY) Duty cycle (READ_DUTY_CYCLE) Reading Set Parameters To clearly display the true performance of the product, PMBus command reads of set levels, limits and timing parameters will return the internally used values. For this reason, due to rounding or internal representation in the controller of the product, there may be a difference between written and read value of a PMBus command. This applies to PMBus commands of type Linear or VoutLinear. When verifying write transactions, tolerances according to the table below can be used. PMBus Command COMP_MODEL Read back accuracy ±0 VIN_ON VIN_OFF VIN_UV_FAULT_LIMIT ±0.1 V VIN_OV_FAULT_LIMIT IOUT_OC_FAULT_LIMIT TON_DELAY TOFF_DELAY TON_RISE TOFF_FALL ±0.1 A ±0.3 ms ±0.4 ms VOUT_COMMAND VOUT_MAX VOUT_MARGIN_HIGH ±0.001 V VOUT_MARGIN_LOW VOUT_TRANSITION_RATE ±0.5 V VOUT_OV_FAULT_LIMIT VOUT_UV_FAULT_LIMIT POWER_GOOD_ON ±0.01 V POWER_GOOD_OFF Non-Volatile Memory (NVM) The product incorporates two Non-Volatile Memory areas for storage of the supported PMBus commands; the Default NVM and the User NVM. The Default NVM is pre-loaded with Flex factory default values. The Default NVM is write-protected and can be used to restore the Flex factory default values through the command RESTORE_DEFAULT_ALL. The RESTORE_DEFAULT_ALL command will load a nominal output level of 0 V. Therefore, after a RESTORE_DEFAULT_ALL command is sent, the input voltage must be cycled in order to load correct output voltage level according to VSET pin-strap resistor (see section Startup procedure). The User NVM is pre-loaded with Flex factory default values. The User NVM is writable and open for customization. The values in the User NVM are loaded during initialization whereafter commands can be changed through the PMBus Interface. The STORE_USER_ALL command will store the changed parameters to the User NVM. 56 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 31/1301-BMR 461Technical EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Date Rev RSA1 [kΩ] RESTORE_USER_ALL INITIALIZATION Default NVM RESTORE_DEFAULT_ALL RAM WRITE PMBus interface READ Protecting Commands The user may write-protect specific PMBus commands in the User NVM by following the steps below. 1. 2. 3. 4. 5. November 2019 © Flex STORE_USER_ALL Flex factory default Write-protected Specification Reference 461 Rev. K 2015-12-2408 1/28701-BMR F User NVM Flex factory default Customizable 2 (6) No. Enter the default password 0x0000 through the command USER_PASSWD. After the correct password is entered, SECURITY_LEVEL will read back 0x01 instead of default 0x00. If desired, define a new password by writing it to the USER_LOCK command. Define which commands should be locked by using the 256 bit command USER_CONF. Setting bit X will writeprotect the PMBus command with code X. Send command STORE_USER_ALL. Cycle the input voltage. Software Tools for Design and Production Flex provides software tools for configuration and monitoring of this product via the PMBus interface. For more information please contact your local Flex sales representative. ≤ 4.22 5.11 6.19 7.15 8.25 9.53 11.0 12.7 14.7 17.8 21.5 26.1 31.6 38.3 44.2 51.1 59.0 68.1 86.6 115 RSA0 [kΩ] 140 169 205 237 ≥ 274 ≤ 4.22 0x0A 0x22 0x3A 0x52 0x6A 5.11 0x0B 0x23 0x3B 0x53 0x6B 6.19 0x0C 0x24 0x3C 0x54 0x6C 7.15 0x0D 0x25 0x3D 0x55 0x6D 8.25 0x0E 0x26 0x3E 0x56 0x6E 9.53 0x0F 0x27 0x3F 0x57 0x6F 11.0 0x10 0x28 0x40 0x58 0x70 12.7 0x11 0x29 0x41 0x59 0x71 14.7 0x12 0x2A 0x42 0x5A 0x72 17.8 0x13 0x2B 0x43 0x5B 0x73 21.5 0x14 0x2C 0x44 0x5C 0x74 26.1 0x15 0x2D 0x45 0x5D 0x75 31.6 0x16 0x2E 0x46 0x5E 0x76 38.3 0x17 0x2F 0x47 0x5F 0x77 44.2 0x18 0x30 0x48 0x60 0x78 51.1 0x19 0x31 0x49 0x61 0x79 59.0 0x1A 0x32 0x4A 0x62 0x7A 68.1 0x1B 0x33 0x4B 0x63 0x7B 86.6 0x1C 0x34 0x4C 0x64 0x7C 115 0x1D 0x35 0x4D 0x65 0x7D 140 0x1E 0x36 0x4E 0x66 0x7E 169 0x1F 0x37 0x4F 0x67 0x7F 205 0x20 0x38 0x50 0x68 0x7F ≥ 237 0x21 0x39 0x51 0x69 0x7F PMBus Addressing The PMBus address should be configured with resistors connected between the SA0/SA1 pins and the PREF pin, as shown in the table and figure below. Note that five different values of RSA1 produce the same address. Recommended resistor values for hard-wiring PMBus addresses are shown in the table. 1% tolerance resistors are required. The configurable PMBus addresses range from 0x0A to 0x7F. In total 118 device address combinations are provided. SA0 SA1 RSA1 RSA0 PREF Schematic of connection of address resistor. 57 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 31/1301-BMR 461Technical EYIZJIA Approved Checked Date BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Optional PMBus Addressing The user may leave SA0/SA1 open or shorted to PREF. Shorting SA0/SA1 to PREF corresponds to RSA0/RSA1 ≤ 4.22 kΩ in the address table above. Leaving SA0/SA1 open corresponds to RSA0/RSA1 ≥ 274 kΩ in the address table above. Reserved Addresses Addresses listed in the table below are reserved or assigned according to the SMBus specification and may not be usable. Refer to the SMBus specification for further information. Address Comment 0x00 General Call Address / START byte 0x01 CBUS address 0x02 Address reserved for different bus format 0x03 - 0x07 Reserved for future use 0x08 SMBus Host 0x09 - 0x0B Assigned for Smart Battery 0x0C SMBus Alert Response Address 0x28 Reserved for ACCESS.bus host 0x2C - 0x2D Reserved by previous versions of the SMBus specification 0x37 0x48 - 0x4B Reserved for ACCESS.bus default address Reserved by previous versions of the SMBus specification Unrestricted addresses 0x61 SMBus Device Default Address 0x78 - 0x7B 10-bit slave addressing 0x7C - 0x7F Reserved for future use 0x40 - 0x44 3 (6) No. Rev Specification Reference 461 Rev. K 2015-12-2408 1/28701-BMR F © Flex followed, including clock stretching. Refer to the SMBus specification, for SMBus electrical and timing requirements. The bus-free time (time between STOP and START packet) according to Electrical Specification must be followed. The product supports PEC (Packet Error Checking) according to the SMBus specification. In operation cases according to the list below the product’s controller will be executing processor-intensive tasks and may not respond to PMBus commands. • During the presence of an overcurrent fault. • Just after the output voltage has been enabled. It is recommended to wait until PG is asserted (or the equivalent time) before sending commands. • When sending subsequent commands to the same unit it is recommended to insert additional delays after write transactions according to the table below. PMBus Command Delay after write before additional command STORE_USER_ALL STORE_DEFAULT_ALL 500 ms, and Vin must be cycled DEADTIME_GCTRL USER_CONF 350 ms MANUF_CONF RESTORE_USER_ALL RESTORE_DEFAULT_ALL 10 ms FREQUENCY_SWITCH VOUT_DROOP IOUT_CAL_GAIN I2C/SMBus – Timing ADAPTIVE_MODE FEEDBACK_EFFORT LOOP_CONFIG COMP_MODEL ZETAP Setup and hold times timing diagram The setup time, tset, is the time data, SDA, must be stable before the rising edge of the clock signal, SCL. The hold time thold, is the time data, SDA, must be stable after the falling edge of the clock signal, SCL. If these times are violated incorrect data may be captured or meta-stability may occur and the bus communication may fail. All standard SMBus protocols must be November 2019 0.5 ms 58 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 31/1301-BMR 461Technical EYIZJIA Approved 4 (6) No. Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W Date Rev Specification Reference 461 Rev. K 2015-12-2408 1/28701-BMR F November 2019 © Flex IOUT_OC_WARN_LIMIT Designation 4Ah Code IOUT_UC_FAULT_LIMIT 4Bh No OT_FAULT_LIMIT 4Fh Yes OT_WARN_LIMIT 51h Yes UT_WARN_LIMIT 52h No UT_FAULT_LIMIT 53h No VIN_OV_FAULT_LIMIT 55h Yes Standard PMBus Commands VIN_OV_WARN_LIMIT 57h No Control Commands VIN_UV_WARN_LIMIT 58h No 59h Yes PMBus Commands The product is PMBus compliant. The following table lists all the implemented PMBus read commands. For more detailed information see PMBus Power System Management Protocol Specification; Part I – General Requirements, Transport and Electrical Interface and PMBus Power System Management Protocol; Part II – Command Language. Designation Code Impl No Impl PAGE 00h No VIN_UV_FAULT_LIMIT OPERATION 01h Yes Fault Response Commands ON_OFF_CONFIG 02h Yes VOUT_OV_FAULT_RESPONSE 41h Yes WRITE_PROTECT 10h Yes VOUT_UV_FAULT_RESPONSE 45h Yes OT_FAULT_RESPONSE 50h Yes Yes UT_FAULT_RESPONSE 54h No 56h Yes Output Commands CAPABILITY (read only) 19h VOUT_MODE (read Only) 20h Yes VIN_OV_FAULT_RESPONSE VOUT_COMMAND 21h Yes VIN_UV_FAULT_RESPONSE 5Ah Yes 47h Yes VOUT_TRIM 22h Yes IOUT_OC_FAULT_RESPONSE VOUT_CAL_OFFSET 23h Yes IOUT_OC_LV_FAULT_RESPONSE 49h No 4Ch No 63h Yes VOUT_MAX 24h Yes IOUT_UC_FAULT_RESPONSE VOUT_MARGIN_HIGH 25h Yes TON_MAX_FAULT_RESPONSE VOUT_MARGIN_LOW 26h Yes Time setting Commands VOUT_TRANSITION_RATE 27h Yes TON_DELAY 60h Yes VOUT_DROOP 28h Yes TON_RISE 61h Yes 64h Yes MAX_DUTY 32h No TOFF_DELAY FREQUENCY_SWITCH 33h Yes TOFF_FALL 65h Yes 62h Yes VIN_ON 35h Yes TON_MAX_FAULT_LIMIT VIN_OFF 36h Yes Status Commands (Read Only) IOUT_CAL_GAIN 38h Yes CLEAR_FAULTS 03h Yes IOUT_CAL_OFFSET 39h Yes STATUS_BYTE 78h Yes VOUT_SCALE_LOOP 29h No STATUS_WORD 79h Yes VOUT_SCALE_MONITOR 2Ah No STATUS_VOUT 7Ah Yes COEFFICIENTS 30h No STATUS_IOUT 7Bh Yes STATUS_INPUT 7Ch Yes Yes STATUS_TEMPERATURE 7Dh Yes 7Eh Yes 80h Yes Fault Limit Commands POWER_GOOD_ON 5Eh POWER_GOOD_OFF 5Fh Yes STATUS_CML VOUT_OV_FAULT_LIMIT 40h Yes STATUS_MFR_SPECIFIC VOUT_OV_WARN_LIMIT 42h No Monitor Commands (Read Only) VOUT_UV_WARN_LIMIT 43h No READ_VIN 88h Yes 89h No VOUT_UV_FAULT_LIMIT 44h Yes READ_IIN IOUT_OC_FAULT_LIMIT 46h Yes READ_VOUT 8Bh Yes IOUT_OC_LV_FAULT_LIMIT 48h No READ_IOUT 8Ch Yes 59 Ericsson Internal PRODUCT SPECIFICATION Prepared (also subject responsible if other) 31/1301-BMR 461Technical EYIZJIA Approved Checked BMR461 series BURAERHBA (LisaPoL Li) Regulators jidgezou Input 4.5-14 V, Output up to 18 A / 60 W READ_TEMPERATURE_1 Designation 8Dh Code Yes Impl READ_TEMPERATURE_2 8Eh Yes READ_FAN_SPEED_1 90h No READ_DUTY_CYCLE 94h Yes READ_FREQUENCY 95h Yes READ_POUT 96h No READ_PIN 97h No INTERLEAVE 37h Yes PHASE_CONTROL F0h No 98h Yes MFR_ID 99h Yes MFR_MODEL 9Ah Yes MFR_REVISION 9Bh Yes MFR_LOCATION 9Ch Yes MFR_DATE 9Dh Yes MFR_SERIAL 9Eh Yes IC_DEVICE_ID ADh Yes IC_DEVICE_REV AEh Yes STORE_DEFAULT_ALL 11h Yes RESTORE_DEFAULT_ALL 12h Yes STORE_USER_ALL 15h Yes RESTORE_USER_ALL 16h Yes ADAPTIVE_MODE D0h Yes FEEDBACK_EFFORT D3h Yes LOOP_CONFIG D5h Yes TEST_MODE D9h Yes COMP_MODEL DBh Yes STRAP_DISABLE DCh Yes MANUF_CONF E0h Yes MANUF_LOCK E1h Yes MANUF_PASSWD E2h Yes USER_CONF E3h Yes USER_LOCK E4h Yes USER_PASSWD E5h Yes SECURITY_LEVEL E6h Yes DEADTIME_GCTRL E7h Yes ZETAP E8h Yes Group Commands Identification Commands PMBUS_REVISION Supervisory Commands Product Specific Commands Impl is short for Implemented. 5 (6) No. Date Rev Specification Reference 461 Rev. K 2015-12-2408 1/28701-BMR F © Flex November 2019 60 Ericsson Internal PRODUCT SPEC. MECHANICAL Prepared (also subject responsible if other) 4/1301-BMR 461 Technical Uen EPETSCH/EHOELII Approved BMR461 series PoL BURAERHB (LISA LI) 1 (3) No. Checked Regulators See §1 Input 4.5-14 V, Output up to 18 A / 60 W Specification Date Rev Reference 2017-05-11 1/28701-BMR 461 Rev. K D November 2019 © Flex Mechanical Information - Surface Mount Version - BMR461 X001 All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. 61 Ericsson Internal PRODUCT SPEC. MECHANICAL Prepared (also subject responsible if other) 4/1301-BMR 461 Technical Uen EPETSCH/EHOELII Approved BMR461 series PoL BURAERHB (LISA LI) 2 (3) No. Checked Regulators See §1 Input 4.5-14 V, Output up to 18 A / 60 W Specification Date Rev Reference 2017-05-11 1/28701-BMR 461 Rev. K D November 2019 © Flex Mechanical Information - Surface Mount Version with solder bumps - BMR461 X101 All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. 62 Internal Use Only PRODUCT SPECIFICATION MECHANICAL. Technical Specification Prepared (also subject responsible if other) No. jidjliaa Jessie LI 5/1301-BMR 461 3001 Uen Approved Date 1/28701-BMR 461 Rev. K Rev Reference 4/4/20189 © E Flex BMR461 series PoL Regulators Checked EAB/FJB/GM Harrisen] See Input 4.5-14[Ksenia V, Output up to 18 A / 60 W§1 1 (4) November 2019 Soldering Information - Surface Mounting Lead-free (Pb-free) solder processes The surface mount product is intended for forced convection or vapor phase reflow soldering in SnPb or Pb-free processes. For Pb-free solder processes, a pin temperature (TPIN) in excess of the solder melting temperature (TL, 217 to 221°C for SnAgCu solder alloys) for more than 30 seconds and a peak temperature of 235°C on all solder joints is recommended to ensure a reliable solder joint. The reflow profile should be optimised to avoid excessive heating of the product. It is recommended to have a sufficiently extended preheat time to ensure an even temperature across the host PCB and it is also recommended to minimize the time in reflow. A no-clean flux is recommended to avoid entrapment of cleaning fluids in cavities inside the product or between the product and the host board, since cleaning residues may affect long time reliability and isolation voltage. General reflow process specifications SnPb eutectic Pb-free Average ramp-up (TPRODUCT) 3°C/s max 3°C/s max 183°C 221°C Typical solder melting (liquidus) temperature TL Minimum reflow time above TL 30 s 30 s TPIN 210°C 235°C Peak product temperature TPRODUCT 225°C 260°C Average ramp-down (TPRODUCT) 6°C/s max 6°C/s max Maximum time 25°C to peak 6 minutes 8 minutes Pin profile Product profile Time in reflow Time in preheat / soak zone Time 25°C to peak For SnPb solder processes, the product is qualified for MSL 1 according to IPC/JEDEC standard J-STD-020C. Pb-free solder processes Temperature TL SnPb solder processes During reflow TPRODUCT must not exceed 225 °C at any time. Minimum pin temperature TPRODUCT maximum TPIN minimum Maximum Product Temperature Requirements Top of the product PCB near pin A2 or A5 is chosen as reference locations for the maximum (peak) allowed product temperature (TPRODUCT) since these will likely be the warmest part of the product during the reflow process. Time Minimum Pin Temperature Recommendations Pin number C1 or D1 are chosen as reference location for the minimum pin temperature recommendation since these will likely be the coolest solder joint during the reflow process. For Pb-free solder processes, the product is qualified for MSL 3 according to IPC/JEDEC standard J-STD-020C. During reflow TPRODUCT must not exceed 260 °C at any time. Dry Pack Information Surface mounted versions of the products are delivered in standard moisture barrier bags according to IPC/JEDEC standard J-STD-033 (Handling, packing, shipping and use of moisture/reflow sensitivity surface mount devices). Using products in high temperature Pb-free soldering processes requires dry pack storage and handling. In case the products have been stored in an uncontrolled environment and no longer can be considered dry, the modules must be baked according to J-STD-033. Thermocoupler Attachment Top of PWB near pin A2 or A5 for measurement of maximum product temperature, TPRODUCT SnPb solder processes For SnPb solder processes, a pin temperature (TPIN) in excess of the solder melting temperature, (TL, 183°C for Sn63Pb37) for more than 30 seconds and a peak temperature of 210°C is recommended to ensure a reliable solder joint. For dry packed products only: depending on the type of solder paste and flux system used on the host board, up to a recommended maximum temperature of 245°C could be used, if the products are kept in a controlled environment (dry pack handling and storage) prior to assembly. Pin C1 or D1 for measurement of minimum Pin (solder joint) temperature TPIN 63 Internal Use Only PRODUCT SPECIFICATION MECHANICAL. Technical Specification Prepared (also subject responsible if other) No. jidjliaa Jessie LI 5/1301-BMR 461 3001 Uen Approved Date 1/28701-BMR 461 Rev. K Rev Reference 4/4/20189 © E Flex BMR461 series PoL Regulators Checked EAB/FJB/GM Harrisen] See Input 4.5-14[Ksenia V, Output up to 18 A / 60 W§1 Surface Mount Assembly and Repair The LGA of the product require particular care during assembly since the LGA´s are hidden between the host board and the product’s PCB. Special procedures are required for successful rework of these products. Assembly Automatic pick and place equipment should be used to mount the product on the host board. The use of a vision system, utilizing the fiducials on the bottom side of the product, will ensure adequate accuracy. Manual mounting of solder bump products is not recommended. ROUND SPROCKET HOLES This module with inductor-glued options can be used on the bottom side of a customer host board. If such an assembly is attempted for the module with other options, components may fall off the module during the second reflow process. Repair For a successful repair (removal and replacement) of a LGA product, a dedicated rework system should be used. The rework system should preferably utilize a reflow station and a bottom side heater might also be needed for the operation. The product is an open frame design with a pick up surface on a large central component (in this case the choke). This pick up surface can be used for removal of the module provided that it is glued against module PCB before removal to prevent it from separating from the module PCB. For specific instructions regarding removal and re-solder of the module refer to 1541 - BMR 461. Delivery Package Information The products are delivered in antistatic carrier tape (EIA 481 standard). Carrier Tape Specifications Material Surface resistance Bakeability Tape width, W Pocket pitch, P1 Pocket depth, K0 Reel diameter Reel capacity Reel weight PS, antistatic < 107 Ohm/square The tape is not bakable 24 mm [0.94 inch] 20 mm [0.79 inch] 8.6 mm [0.339 inch] 330 mm [13 inch] 280 products /reel 1160 g/full reel 2 (4) PIN 1 November 2019 64 Internal Use Only PRODUCT SPECIFICATION MECHANICAL. Technical Specification Prepared (also subject responsible if other) No. jidjliaa Jessie LI 5/1301-BMR 461 3001 Uen Approved Date 1/28701-BMR 461 Rev. K Rev Reference 4/4/20189 © E Flex BMR461 series PoL Regulators Checked EAB/FJB/GM Harrisen] See Input 4.5-14[Ksenia V, Output up to 18 A / 60 W§1 3 (4) November 2019 Product Qualification Specification Characteristics External visual inspection IPC-A-610 Change of temperature (Temperature cycling) IEC 60068-2-14 Na Temperature range Number of cycles Dwell/transfer time -40 to 100°C 1000 15 min/0-1 min Cold (in operation) IEC 60068-2-1 Ad Temperature TA Duration -45°C 72 h Damp heat IEC 60068-2-67 Cy Temperature Humidity Duration 85°C 85 % RH 1000 hours Dry heat IEC 60068-2-2 Bd Temperature Duration 125°C 1000 h Electrostatic discharge susceptibility IEC 61340-3-1, JESD 22A114 IEC 61340-3-2, JESD 22A115 Human body model (HBM) Machine Model (MM) Class 2, 2000 V Class 3, 200 V Immersion in cleaning solvents IEC 60068-2-45 XA, method 2 Water Glycol ether Isopropyl alcohol 55°C 35°C 35°C Mechanical shock IEC 60068-2-27 Ea Peak acceleration Duration 100 g 6 ms Moisture reflow sensitivity J-STD-020C Level 1 (SnPb-eutectic) Level 3 (Pb Free) 225°C 260°C Operational life test MIL-STD-202G, method 108A Duration 1000 h Robustness of terminations IEC 60068-2-21 Test Ua1 IEC 60068-2-21 Test Ue1 Through hole mount products Surface mount products All leads All leads Preconditioning Temperature, SnPb Eutectic Temperature, Pb-free 150°C dry bake 16 h 215°C 235°C Frequency Spectral density Duration 10 to 500 Hz 0.07 g2/Hz 10 min in each 3 perpendicular directions IEC 60068-2-58 test Td Solderability Vibration, broad band random IEC 60068-2-64 Fh, method 1
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