CD4021BE

XBLW CD4021 8-Bit Static Shift Register General Description The CD4021 is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. Features  Tolerant of slower rise and fall times  Fully static operation  5V, 10V, and 15V parametric ratings  Standardized symmetrical output characteristics  Specified from -40℃ to +105℃  Packaging information: DIP16/SOP16/TSSOP16 ORDERING INFORMATION DEVICE Package Type MARKING Packing Packing QTY CD4021BE CD4021BDTR CD4021BTDTR DIP-16 SOP-16 TSSOP-16 CD4021BE CD4021B CD4021B Tube Tape Tape 1000/Box 2500/Reel 3000/Reel XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 1 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register Block Diagram And Pin Description Block Diagram Figure 1. Functional diagram Figure 2. Logic diagram XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 2 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register Pin Configurations Pin Description Pin No. Pin Name Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D7 Q5 Q7 D3 D2 D1 D0 VSS PL CP DS Q6 D4 D5 D6 VDD parallel data input buffered parallel output from the last three stages buffered parallel output from the last three stages parallel data input parallel data input parallel data input parallel data input ground supply voltage parallel load input clock input (LOW-to-HIGH edge-triggered) serial data input buffered parallel output from the last three stages parallel data input parallel data input parallel data input supply voltage XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 3 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register Function Table Number of clock transitions Inputs DS CP Serial operation 1 2 3 6 7 8 Outputs Q6 PL Q5 X X X data 1 data 2 data 3 no change data 1 data 2 no change data 1 no change D5 D6 D7 ↑ ↑ ↑ ↑ ↑ ↑ ↓ data 1 data 2 data 3 X X X X L L L L L L L X X H Q7 X X X X X X X X X Parallel operation Note: [1] H=HIGH voltage level; L=LOW voltage level; X=don’t care; ↑=LOW to HIGH clock transition; ↓=HIGH to LOW clock transition; data n=data (HIGH or LOW) on the DS input at the nth ↑ CP transition. Electrical Parameter Absolute Maximum Ratings (Tamb=25℃, unless otherwise specified.) Characteristic Symbol Conditions Min. supply voltage input clamping current input voltage output clamping current input/output current supply current operating temperature storage temperature total power dissipation power dissipation VDD IIK VI IOK II/O IDD Tamb Tstg Ptot PD -0.5 -0.5 -40 -65 soldering temperature TL VI < -0.5V or VI > VDD +0.5V VI < -0.5V or VI > VDD +0.5V per output DIP 10s SOP/TSSOP XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ Max. Unit +18 ±10 VDD +0.5 ±10 ±10 50 +105 +150 500 100 245 260 V mA V mA mA mh ℃ ℃ mW mW ℃ ℃ 第 4 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register Recommended Operating Conditions Parameter Symbol Conditions Min. Typ. Max. Unit supply voltage input voltage operating temperature VDD VI Tamb - 3 0 -40 - 15 VDD +105 V V ℃ Electrical Characteristics DC Characteristics 1 (Tamb=25℃, voltages are referenced to VSS (ground=0V), unless otherwise specified.) Parameter supply current LOW-level output current HIGH-level output current LOW-level output voltage HIGH-level output voltage LOW-level input voltage Symbol IDD IOL IOH VOL VOH VIL VO Conditions(V) VIN VDD Min. Tamb=25℃ Typ. Max. Unit - 0, 5 5 - - 5 μA - 0, 10 10 - - 10 μA - 0, 15 15 - - 20 μA 0.4 0, 5 5 0.5 - - mA 0.5 0, 10 10 1.3 - - mA 1.5 0, 15 15 3.4 - - mA 4.6 0, 5 5 - - -0.5 mA 2.5 0, 5 5 - - -1.4 mA 9.5 0, 10 10 - - -1.3 mA 13.5 0, 15 15 - - -3.4 mA - 0, 5 5 - - 0.05 V - 0, 10 10 - - 0.05 V - 0, 15 15 - - 0.05 V - 0, 5 5 4.95 - - V - 0, 10 10 9.95 - - V - 0, 15 15 14.95 - - V 4.5 - 5 - - 1.5 V 9 - 10 - - 3 V 13.5 - 15 - - 4 V 0.5, 4.5 - 5 3.5 - - V 1, 9 - 10 7 - - V 1.5, 13.5 - 15 11 - - V HIGH-level input voltage VIH input leakage current II - 0, 15 15 - - ±1.0 μA input capacitance CI - - - - - 7.5 pF XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 5 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register DC Characteristics 2 (Tamb=-40℃ to +105℃, voltages are referenced to VSS (ground=0V), unless otherwise specified.) Parameter supply current Symbol IDD LOW-level output current IOL HIGH-level output current IOH LOW-level output voltage VOL HIGH-level output voltage VOH LOW-level input voltage VIL HIGH-level input voltage VIH input leakage current II XBLW version 1.0 Conditions(V) VO VIN VDD Tamb=-40℃ Min. Max. Tamb=+85℃ Min. Max. Tamb=+105℃ Min. Max. Unit - 0, 5 5 - 5 - 150 - 15 μA - 0, 10 10 - 10 - 300 - 300 μA - 0, 15 15 - 20 - 600 - 600 μA 0.4 0.5 1.5 4.6 2.5 9.5 13.5 4.5 9 13.5 0.5, 4.5 1, 9 1.5, 13.5 0, 5 0, 10 0, 15 0, 5 0, 5 0, 10 0, 15 0, 5 0, 10 0, 15 0, 5 0, 10 0, 15 - 5 10 15 5 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 0.64 1.6 4.2 4.95 9.95 14.95 3.5 7 11 -0.64 -1.7 -1.6 -4.2 0.05 0.05 0.05 1.5 3 4 - 0.36 0.9 2.4 4.95 9.95 14.95 3.5 7 11 -0.36 -1.1 -0.9 -2.4 0.05 0.05 0.05 1.5 3 4 - 0.36 0.9 2.4 4.95 9.95 14.95 3.5 7 11 -0.36 -1.1 -0.9 -2.4 0.05 0.05 0.05 1.5 3 4 - mA mA mA mA mA mA mA V V V V V V V V V V V V - 0, 15 15 - ±0.1 - ±1.0 - ±1.0 μA 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 6 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register AC Characteristics (Tamb=25℃, VSS=0V, unless otherwise specified.) Parameter HIGH to LOW propagation delay Symbol Conditions CP to Qn; see Figure 4 tPHL PL to Qn; see Figure 4 CP to Qn; see Figure 4 LOW to HIGH propagation delay tPLH transition time tt PL to Qn; see Figure 4 Qn; see Figure 4 DS to CP; see Figure 5 set-up time tSU Dn to PL; see Figure 6 DS to CP; see Figure 5 hold time th Dn to PL; see Figure 6 CP=LOW; minimum width; see Figure 5 pulse width tW recovery time trec PL input; see Figure 6 maximum clock frequency Fclk(max) CP input; see Figure 5 XBLW version 1.0 PL=HIGH; minimum width; see Figure 6 VDD 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. +25 +25 +15 50 30 20 40 20 15 +15 15 15 70 30 24 70 30 24 50 40 35 - Typ. 125 55 40 135 78 65 115 50 40 135 78 72 60 30 20 +4 0 0 -11 -7 -3 8 3 0 -13 -9 -4 35 15 12 35 15 12 10 5 5 13 30 40 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ Max. 250 110 80 240 110 80 230 100 80 210 100 80 120 60 40 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 第 7 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register Testing Circuit AC Testing Circuit Definitions for test circuit: Figure 3. Test circuit for switching times DUT=Device Under Test CL=Load capacitance including jig and probe capacitance. RT=Termination resistance should be equal to the output impedance Zo of the pulse generator. AC Testing Waveforms Figure 4. Waveforms showing propagation delays for CP and PL inputs to Qn output and Qn transition times XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 8 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register Figure 5. Waveforms showing minimum clock pulse width, set-up time, and hold time for CP and DS. Figure 6. Waveforms showing minimum pulse width and recovery time for PL; set-up and hold times for Dn to PL. Measurement Points Supply voltage VDD 5V to 15V Input VM 0.5×VDD Output VX 0.1×VDD VM 0.5×VDD VY 0.9×VDD Test Data Supply voltage VDD VI tr, tf Load CL 5V to 15V VSS or VDD ≤20ns 50pF XBLW version 1.0 Input 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 9 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register Package Information DIP16 Symbol A2 A1 A L b B1 D E1 e c eB XBLW version 1.0 Min. Dimensions(mm) 3.20 0.51 3.60 3.00 0.36 Max. 3.60 5.33 3.60 0.56 1.52 18.80 6.20 19.94 6.60 2.54 0.20 7.62 0.36 9.30 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 10 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register SOP16 Symbol A1 A2 b c D E E1 e L θ XBLW version 1.0 Min. Dimensions (mm) 0.10 1.25 0.33 0.19 9.50 5.80 3.70 Max. 0.25 1.55 0.51 0.25 10.10 6.30 4.10 1.27 0.35 0° 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 0.89 8° 第 11 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register TSSOP16 SYMBOL A A1 A2 b c D E1 E e L θ XBLW version 1.0 MILLIMETER MIN 0.05 0.80 0.19 0.09 4.90 4.30 6.20 MAX 1.20 0.15 1.05 0.30 0.20 5.10 4.50 6.60 0.65 0.45 0° 0.75 8° 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 12 页 共 13 页 XBLW CD4021 8-Bit Static Shift Register Statements And Notes Part name Lead and lead compounds Lead frame ○ Plastic resin ○ ○ ○ ○ ○ ○ Chip ○ ○ ○ ○ ○ The lead Plastic sheet installed ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ explanation Cadmium and cadmium compounds ○ Hazardous substances or Elements Polybro Hexavalent Polybro minated Dibutyl chromium minated biphenyl phthalate compounds biphenyls ethers ○ ○ ○ ○ Mercury and mercury compounds ○ Butyl benzyl phthalate Di-2ethylhexyl phthalate Diisobutyl phthalate ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○: Indicates that the content of hazardous substances or elements in the detection limit of the following the SJ/T11363-2006 standard. ×: Indicates that the content of hazardous substances or elements exceeding the SJ/T11363-2006 Standard limit requirements Statement：  Shenzhen xinbole electronics co., ltd. reserves the right to change the product specifications, without notice! Before placing an order, the customer needs to confirm whether the information obtained is the latest version, and verify the integrity of the relevant information.  Any semiconductor product is liable to fail or malfunction under certain conditions, and the buyer shall be responsible for complying with safety standards in the system design and whole machine manufacturing using Shenzhen xinbole electronics co., ltd products, and take appropriate security measures to avoid the potential risk of failure may result in personal injury or property losses of the situation occurred!  Product performance is never ending, Shenzhen xinbole electronics co., ltd will be dedicated to provide customers with better performance, better quality of integrated circuit products. XBLW version 1.0 文档仅供参考，实际应用测试为准 ｗｗｗ．ｘｉｎｂｏｌｅｉｃ．ｃｏｍ　　　　　　　技术支持热线：４００９６８２００３ 第 13 页 共 13 页