XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
General Description
The SN74HC/HCT190 are asynchronously presettable up/down BCD decade counters. They contain four master/slave
flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up
and count-down operation.
Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on
the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs when
—
the parallel load (PL) input is LOW. As indicated in the function table, this operation overrides the counting
function.
—
—
Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW internal state
changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The up/down (U
/D) input signal determines the direction of counting as indicated in the function table. The CE input may
go LOW when the clock is in either state, however, the LOW-to-HIGH CE transition must occur only
—
—
when the clock is HIGH. Also, the U/D input should be changed only when either CE or CP is HIGH.
Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple
clock (RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the
count-down mode or reaches “9” in the count-up-mode. The TC output will remain HIGH until a state
change occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a
clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC
—
—
output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This feature
simplifies the design of multistage counters as shown in Figure 5 and 6.
In Figure 5, each RC output is used as the clock input to the next higher stage. It is only necessary to
—
—
inhibit the first stage to prevent counting in all stages, since a HIGH on CE inhibits the RC output pulse as
indicated in the function table. The timing skew between state changes in the first and last stages is represented by
the cumulative delay of the clock as it ripples through the preceding stages. This can be a
disadvantage of this configuration in some applications.
Figure 6 shows a method of causing state changes to occur simultaneously in all stages. The RC outputs propagate
the carry/borrow signals in ripple fashion and all clock inputs are driven in parallel. In this configuration the
duration of the clock LOW state must be long enough to allow the negative-going edge
—
of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. Since the RC
output of any package goes HIGH shortly after its CP input goes HIGH there is no such restriction on the HIGHstate duration of the clock.
In Figure.7, the configuration shown avoids ripple delays and their associated restrictions. Combining the
—
TC signals from all the preceding stages forms the CE input for a given stage. An enable must be included in
each carry gate in order to inhibit counting. The TC output of a given stage it not affected by
—
its own CE signal therefore the simple inhibit scheme of Figure 5 and 6 does not apply.
Features
Input levels:
For SN74HC190: CMOS level
For SN74HCT190: TTL level
Synchronous reversible counting
Asynchronous parallel load
Count enable control for synchronous expansion
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Single up/down control input
Specified from -40℃ to +125℃
Packaging information: DIP16/SOP16/TSSOP16
Ordering Information
Product Model
XBLW SN74HC190N
XBLW SN74HC190DTR
XBLW SN74HC190TDTR
XBLW SN74HCT190N
XBLW SN74HCT190DTR
XBLW SN74HCT190TDTR
Package Type
DIP-16
SOP-16
TSSOP-16
DIP-16
SOP-16
TSSOP-16
Marking
74HC190N
74HC190
74HC190
74HCT190N
74HCT190
74HCT190
Packing
Tube
Tape
Tape
Tube
Tape
Tape
Packing Qty
1000Pcs/Box
2500Pcs/Reel
3000Pcs/Reel
1000Pcs/Box
2500Pcs/Reel
3000Pcs/Reel
Block Diagram And Pin Description
Block Diagram
Figure 1. Logic symbol
Figure 2. IEC logic symbol
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Figure 3.Functional diagram
Figure 4. Logic diagram
Figure 5.N-stage ripple counter using ripple clock
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Figure 6. Synchronous n-stage counter using ripple carry/borrow
Figure 7. Synchronous n-stage counter with parallel gated carry/borrow
Figure 8. Typical timing sequence
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Pin Configurations
Pin Description
Pin No.
1
Pin Name
Description
D1
data input
2
Q1
flip-flop output
3
Q0
flip-flop output
4
CE
count enable input (active LOW)
5
U/D
up/down input
6
Q2
flip-flop output
7
Q3
flip-flop output
8
GND
ground (0V)
9
D3
data input
10
D2
data input
11
PL
parallel load input (active LOW)
12
TC
terminal count output
13
RC
ripple clock output (active LOW)
14
CP
15
D0
clock input (LOW-to-HIGH, edge-triggered)
data input
16
VCC
supply voltage
Function Table
Operating mode
Input
Output
PL
U/D
CE
CP
Dn
Qn
L
X
X
X
L
L
L
X
X
X
H
H
count up
H
L
l
↑
X
count up
count down
hold (do nothing)
H
H
l
↑
X
count down
H
X
H
X
X
no change
parallel load
Note: H=HIGH voltage level; L=LOW voltage level; X=don’t care; ↑=LOW-to-HIGH clock
l=LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition.
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Input
Output
Terminal count state
U/D
CE
CP
Q0
Q1
Q2
Q3
TC
RC
H
H
X
H
X
X
H
L
H
L
H
X
H
X
X
H
H
H
L
L
H
X
X
H
L
H
X
L
L
L
L
L
H
H
H
X
L
L
L
L
H
H
H
L
L
L
L
L
—
Note:
[1] H=HIGH voltage level; L=LOW voltage level; X=don’t care.
[2]
[3]
=one LOW level output pulse.
=TC goes LOW on a LOW-to-HIGH clock transition.
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Electrical Parameter
Absolute Maximum Ratings
(Voltages are referenced to GND(ground=0V), unless otherwise specified.)
Parameter
Symbol
Conditions
supply voltage
VCC
Min.
-0.5
Max.
+7.0
Unit
input clamping
current
-
IIK
VI < -0.5V or VI > VCC+0.5V
-
±20
mA
output clamping
current
IOK
VO < -0.5V or VO > VCC+0.5V
-
±20
mA
output current
IO
VO= -0.5V to VCC+0.5V
±25
mA
supply current
ICC
-
mA
IGND
-
-50
+50
ground current
storage
temperature
-
-
mA
Tstg
-
-65
+150
℃
total power
dissipation
Ptot
-
-
500
mW
Soldering
temperatur
e
TL
245
260
DIP
SOP/TSSOP
10s
V
℃
Recommended Operating Conditions
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
2.0
5.0
6.0
V
-
VCC
V
VCC
625
V
ns/V
139
ns/V
SN74HC190
supply voltage
VCC
input voltage
VI
output voltage
VO
input transition
rise and fall rate
VCC=2.0V
Δt/ΔV
VCC=4.5V
-
1.67
VCC=6.0V
-
-
83
ns/V
ambient
temperature
Tamb
-
-40
-
+125
℃
supply voltage
VCC
4.5
5.0
5.5
V
input voltage
-
VI
0
V
VO
-
VCC
output voltage
-
-
0
-
0
-
-
SN74HCT190
input transition
rise and fall rate
Δt/ΔV
ambient
temperature
Tamb
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VCC=2.0V
0
VCC=4.5V
VCC=6.0V
-
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-
VCC
V
-
1.67
139
ns/V
-
-
-
ns/V
-40
-
+125
℃
-
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
DC Characteristics 1
(Tamb=25℃, voltages are referenced to GND (ground=0V), unless otherwise specified.)
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
VCC=2.0V
1.5
1.2
V
VCC=4.5V
3.15
2.4
-
VCC=6.0V
4.2
3.2
VCC=2.0V
-
VCC=4.5V
SN74HC190
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
VIH
VIL
-
V
V
0.8
0.5
V
-
2.1
1.35
V
1.8
V
IO=-20uA; VCC=2.0V
1.9
2.8
2.0
V
IO=-20uA; VCC=4.5V
4.4
4.5
-
IO=-20uA; VCC=6.0V
5.9
6.0
IO=-4.0mA; VCC=4.5V
3.98
4.32
IO=-5.2mA; VCC=6.0V
5.48
5.81
-
VCC=6.0V
VOH
VI = VIH or VIL
IO=20uA; VCC=2.0V
LOW-level
output voltage
IO=20uA; VCC=4.5V
VOL
IO=20uA; VCC=6.0V
VI = VIH or VIL
IO=4.0mA; VCC=4.5V
IO=5.2mA; VCC=6.0V
-
-
V
V
-
V
0.1
V
0
V
0
0.1
V
0
0.1
V
0.15
0.26
V
-
0.16
0.26
V
-
input leakage
current
II
VI=VCC or GND; VCC=6.0V
-
-
±1.0
uA
supply current
ICC
VI=VCC or GND; IO=0A; VCC=6.0V
-
3.5
uA
CI
-
8.0
input
-
pF
-
capacitance
SN74HCT190
HIGH-level
input voltage
VIH
VCC=4.5V to 5.5V
2.0
1.6
-
V
LOW-level
input voltage
VIL
VCC=4.5V to 5.5V
-
1.2
0.8
V
HIGH-level
output voltage
VOH
IO=-20uA
4.4
4.5
V
IO=-4.0mA
3.98
4.32
-
-
0.1
V
0
V
-
0.16
0.26
V
VI = VIH or VIL;
VCC=4.5V
IO=20uA
LOW-level
output voltage
VOL
input leakage
current
II
VI=VCC or GND; VCC=5.5V
-
-
±1.0
uA
supply current
ICC
-
-
8.0
uA
additional
supply current
ΔICC
VI=VCC or GND; IO=0A; VCC=5.5V
VI=VCC-2.1V;
other inputs at VCC or GND; IO=0A;
VCC=4.5V to 5.5V
-
-
360
uA
input
capacitance
CI
-
-
3.5
-
pF
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VI = VIH or VIL;
VCC=4.5V
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
DC Characteristics 2
(Tamb=-40℃ to +85℃, voltages are referenced to GND (ground=0V), unless otherwise specified.)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
VCC=2.0V
1.5
VCC=4.5V
-
-
V
3.15
4.2
-
V
VCC=6.0V
-
-
-
0.5
V
VCC=2.0V
-
V
-
-
1.35
V
-
1.8
V
IO=-20uA; VCC=2.0V
1.9
IO=-20uA; VCC=4.5V
-
-
V
4.4
IO=-20uA; VCC=6.0V
5.9
-
-
IO=-4.0mA; VCC=4.5V
3.84
-
IO=-5.2mA; VCC=6.0V
-
-
V
5.34
-
-
0.1
V
IO=20uA; VCC=2.0V
-
V
-
-
0.1
V
-
-
0.1
V
-
-
0.33
V
-
-
0.33
V
SN74HC190
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VIH
VIL
VCC=4.5V
VCC=6.0V
VOH
VI = VIH or VIL
IO=20uA; VCC=4.5V
VOL
IO=20uA; VCC=6.0V
VI = VIH or VIL
IO=4.0mA; VCC=4.5V
IO=5.2mA; VCC=6.0V
V
V
input leakage
current
II
VI=VCC or GND; VCC=6.0V
-
-
±1.0
uA
supply current
ICC
VI=VCC or GND; IO=0A; VCC=6.0V
-
-
80
uA
SN74HCT190
HIGH-level
input voltage
VIH
VCC=4.5V to 5.5V
2.0
-
-
V
LOW-level
input voltage
VIL
VCC=4.5V to 5.5V
-
-
0.8
V
HIGH-level
output voltage
VOH
VI = VIH or VIL;
VCC=4.5V
IO=-20uA
4.4
-
V
IO=-4.0mA
3.84
-
LOW-level
output voltage
VOL
VI = VIH or VIL;
VCC=4.5V
-
-
0.1
V
IO=20uA
-
V
-
V
input leakage
current
-
0.33
II
VI=VCC or GND; VCC=5.5V
-
-
±1.0
uA
supply current
ICC
-
-
80
uA
additional
supply current
ΔICC
VI=VCC or GND; IO=0A; VCC=5.5V
VI=VCC-2.1V;
other inputs at VCC or GND; IO=0A;
VCC=4.5V to 5.5V
-
-
450
uA
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IO=4.0mA
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
DC Characteristics 3
(Tamb=-40℃ to +125℃, voltages are referenced to GND (ground=0V), unless otherwise specified.)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
VCC=2.0V
1.5
-
-
V
VCC=4.5V
3.15
4.2
-
V
VCC=6.0V
-
V
VCC=2.0V
-
-
0.5
V
-
-
1.35
V
-
1.8
V
IO=-20uA; VCC=2.0V
1.9
IO=-20uA; VCC=4.5V
-
-
V
4.4
IO=-20uA; VCC=6.0V
5.9
-
-
IO=-4.0mA; VCC=4.5V
3.7
-
-
5.2
-
-
V
IO=-5.2mA; VCC=6.0V
-
-
0.1
V
IO=20uA; VCC=2.0V
-
V
-
-
0.1
V
-
-
0.1
V
-
-
0.4
V
-
-
0.4
V
SN74HC190
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VIH
VCC=4.5V
VIL
VCC=6.0V
VOH
VI = VIH or VIL
IO=20uA; VCC=4.5V
VOL
IO=20uA; VCC=6.0V
VI = VIH or VIL
IO=4.0mA; VCC=4.5V
IO=5.2mA; VCC=6.0V
V
V
input leakage
current
II
VI=VCC or GND; VCC=6.0V
-
-
±1.0
uA
supply current
ICC
VI=VCC or GND; IO=0A; VCC=6.0V
-
-
160
uA
SN74HCT190
HIGH-level
input voltage
VIH
VCC=4.5V to 5.5V
2.0
-
-
V
LOW-level
input voltage
VIL
VCC=4.5V to 5.5V
-
-
0.8
V
HIGH-level
output voltage
VOH
VI = VIH or VIL;
VCC=4.5V
IO=-20uA
4.4
-
V
IO=-4.0mA
3.7
-
LOW-level
output voltage
VOL
VI = VIH or VIL;
VCC=4.5V
-
V
IO=4.0mA
-
0.1
V
IO=20uA
-
V
input leakage
current
-
0.4
II
VI=VCC or GND; VCC=5.5V
-
-
±1.0
uA
supply current
ICC
VI=VCC or GND; IO=0A; VCC=5.5V
-
160
uA
additional
supply current
ΔICC
-
-
490
uA
XBLWversion1.0
VI=VCC-2.1V;
other inputs at VCC or GND; IO=0A;
VCC=4.5V to 5.5V
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
AC Characteristics 1
(Tamb=25℃, GND=0V; tr=tf=6ns; CL=50pF, unless otherwise specified.)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
SN74HC190
VCC=2.0V
CP to Qn;
see Figure
10
CP to TC;
see Figure
10
—
CP to RC;
see Figure 11
—
propagation
delay
tpd
—
CE to RC;
see Figure
11
Dn to Qn;
see Figure
12
PL to Qn;
see Figure
13
—
U/D to TC;
see Figure 14
—
—
U/D to RC;
see Figure 14
VCC=4.5V
VCC=5.0V; CL=15pF
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
tt
see Figure 15
pulse width
tW
—
PL; LOW;
see Figure 15
recovery time
trec
set-up time
tsu
XBLWversion1.0
PL to CP;
see Figure
15
—
U/D to CP;
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-
220
ns
44
ns
22
ns
21
37
83
255
ns
30
51
ns
ns
24
43
ns
44
150
ns
16
30
ns
13
26
ns
33
130
ns
12
26
ns
10
22
ns
63
220
ns
23
44
ns
18
37
ns
63
220
ns
23
44
ns
18
37
ns
44
190
ns
16
38
ns
13
32
ns
210
ns
18
42
ns
14
36
ns
19
75
ns
-
7
15
ns
155
6
13
ns
VCC=2.0V
28
ns
VCC=4.5V
31
10
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=4.5V
VCC=6.0V
CP; HIGH or
LOW;
see Figure 10
-
72
26
50
VCC=6.0V
VCC=2.0V
transition time
-
-
VCC=6.0V
26
8
VCC=2.0V
100
25
VCC=4.5V
20
9
VCC=6.0V
17
7
VCC=2.0V
35
8
VCC=4.5V
7
3
VCC=6.0V
6
2
VCC=2.0V
205
61
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
see Figure 16
—
Dn to PL;
see Figure 17
CE to CP;
see Figure
16
—
U/D to CP;
see Figure 16
—
hold time
th
Dn to PL;
see Figure 17
CE to CP;
see Figure
16
maximum
frequency
fmax
CP;
see Figure 10
VCC=4.5V
41
22
VCC=6.0V
35
18
VCC=2.0V
100
19
VCC=4.5V
20
7
VCC=6.0V
17
6
VCC=2.0V
140
39
VCC=4.5V
28
14
VCC=6.0V
24
11
VCC=2.0V
0
-44
VCC=4.5V
0
-16
VCC=6.0V
0
-13
VCC=2.0V
0
-14
VCC=4.5V
0
-5
VCC=6.0V
0
-4
VCC=2.0V
0
-19
VCC=4.5V
0
-7
VCC=6.0V
0
-6
VCC=2.0V
3.0
8.3
VCC=4.5V
VCC=5.0V; CL=15pF
15
25
18
28
-
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
MHz
-
MHz
MHz
MHz
36
-
pF
28
48
ns
-
24
-
ns
VCC=4.5V
-
34
58
ns
VCC=4.5V
-
20
35
ns
CE to RC;
see Figure
11
Dn to Qn;
see Figure
12
VCC=4.5V
-
18
33
ns
VCC=4.5V
-
24
44
ns
PL to Qn;
see Figure
13
VCC=4.5V
-
29
49
ns
VCC=4.5V
-
24
45
ns
-
26
45
ns
-
7
15
ns
25
10
-
ns
PL; LOW; VCC=4.5V; see Figure 15
22
12
-
ns
PL to CP; VCC=4.5V; see Figure 15
7
1
-
ns
CPD
VI=GND to VCC
30
ns
-
VCC=6.0V
power
dissipation
capacitanc
e
-
SN74HCT190
CP to Qn;
see Figure
10
CP to TC;
see Figure
10
—
CP to RC;
see Figure 11
propagation
delay
—
tpd
VCC=4.5V
VCC=5.0V; CL=15pF
—
—
—
U/D to TC;
see Figure 14
—
transition time
tt
pulse width
tW
recovery time
XBLWversion1.0
trec
—
U/D to RC;
VCC=4.5V
see Figure 14
VCC=4.5V; see Figure 15
CP; HIGH or LOW; VCC=4.5V
see Figure 10
—
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
set-up time
hold time
U/D to CP; VCC=4.5V; see Figure 16
42
25
-
ns
Dn to PL; VCC=4.5V; see Figure 17
20
10
-
ns
CE to CP; VCC=4.5V;see Figure 16
31
18
-
ns
U/D to CP; VCC=4.5V; see Figure 16
0
-18
-
ns
0
-6
-
ns
-
ns
-
MHz
tsu
—
Dn to PL; VCC=4.5V; see Figure 17
th
CE to CP; VCC=4.5V;see Figure 16
maximum
frequency
fmax
power
dissipation
capacitanc
e
CPD
CP;
see Figure 10
VCC=4.5V
VCC=5.0V; CL=15pF
VI=GND to VCC- 1.5V
0
-10
16
27
-
30
-
38
-
MHz
-
pF
Note:
[1] tpd is the same as tPLH and tPHL.
[2] tt is the sameastTHL and tTLH.
[3] CPD isused to determine the dynamic power dissipation (PD in uW).
PD=CPD ×VCC2 ×fi+Σ(CL×VCC2 ×fo) where:
f i=input frequency in MHz;
fo=output frequency in MHz;
CL=output load capacitance in pF;
VCC=supply voltage in V;
Σ(CL×VCC2 ×fo)=sum of outputs.
AC Characteristics 2
(Tamb=-40℃ to +85℃, GND=0V; tr=tf=6ns; CL=50pF, unless otherwise specified.)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
VCC=2.0V
-
-
275
ns
VCC=4.5V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SN74HC190
CP to Qn;
see Figure
10
CP to TC;
see Figure
10
—
propagation
delay
CP to RC;
see Figure 11
tpd
—
—
CE to RC;
see Figure
11
Dn to Qn;
see Figure
12
PL to Qn;
see Figure
13
XBLWversion1.0
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VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
Technical Support:4009682003
55
ns
47
ns
320
ns
64
ns
54
ns
190
ns
38
ns
33
ns
165
ns
33
ns
28
ns
275
ns
55
ns
47
ns
275
ns
55
ns
47
ns
13 / 24
XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
—
U/D to TC;
see Figure 14
—
—
U/D to RC;
see Figure 14
VCC=2.0V
transition time
tt
pulse width
tW
—
PL; LOW;
see Figure 15
recovery time
trec
PL to CP;
see Figure
15
—
U/D to CP;
see Figure 16
set-up time
—
tsu
Dn to PL;
see Figure 17
CE to CP;
see Figure
16
—
U/D to CP;
see Figure 16
—
hold time
th
Dn to PL;
see Figure 17
CE to CP;
see Figure
16
maximum
frequency
fmax
CP;
see Figure 10
propagation
delay
tpd
—
CP to RC;
see Figure 11
XBLWversion1.0
www.xinboleic.com
ns
265
ns
53
ns
45
ns
95
ns
19
ns
-
16
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
-
-
ns
MHz
-
-
-
-
MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC=2.0V
195
VCC=4.5V
39
VCC=6.0V
33
VCC=2.0V
125
VCC=4.5V
25
VCC=6.0V
21
VCC=2.0V
45
VCC=4.5V
9
VCC=6.0V
8
VCC=2.0V
255
VCC=4.5V
51
VCC=6.0V
43
VCC=2.0V
125
VCC=4.5V
25
VCC=6.0V
21
VCC=2.0V
175
VCC=4.5V
35
VCC=6.0V
30
VCC=2.0V
0
VCC=4.5V
0
VCC=6.0V
0
VCC=2.0V
0
VCC=4.5V
0
VCC=6.0V
0
VCC=2.0V
0
VCC=4.5V
0
VCC=6.0V
0
VCC=2.0V
2.4
VCC=4.5V
12
VCC=6.0V
14
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=4.5V
SN74HCT190
CP to Qn;
see Figure
10
CP to TC;
see Figure
10
ns
41
-
VCC=4.5V
VCC=6.0V
CP; HIGH or
LOW;
see Figure 10
ns
48
-
VCC=2.0V
see Figure 15
240
-
MHz
VCC=4.5V
-
-
60
ns
VCC=4.5V
-
-
73
ns
VCC=4.5V
-
-
44
ns
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
—
—
CE to RC;
see Figure
11
Dn to Qn;
see Figure
12
VCC=4.5V
-
-
41
ns
VCC=4.5V
-
-
55
ns
PL to Qn;
see Figure
13
VCC=4.5V
-
-
61
ns
VCC=4.5V
-
-
56
ns
-
-
56
ns
-
-
19
ns
31
-
-
ns
PL; LOW; VCC=4.5V; see Figure 15
28
-
-
ns
PL to CP; VCC=4.5V; see Figure 15
9
-
-
ns
U/D to CP; VCC=4.5V; see Figure 16
53
-
-
ns
Dn to PL; VCC=4.5V; see Figure 17
25
-
-
ns
CE to CP; VCC=4.5V;see Figure 16
39
-
-
ns
U/D to CP; VCC=4.5V; see Figure 16
0
-
-
ns
—
U/D to TC;
see Figure 14
—
transition time
tt
pulse width
tW
recovery time
set-up time
hold time
maximum
frequency
trec
tsu
—
U/D to RC;
VCC=4.5V
see Figure 14
VCC=4.5V; see Figure 15
CP; HIGH or LOW; VCC=4.5V
see Figure 10
—
th
Dn to PL; VCC=4.5V; see Figure 17
0
-
-
ns
0
-
-
ns
fmax
CE to CP; VCC=4.5V;see Figure 16
CP;
VCC=4.5V
see Figure 10
13
-
-
MHz
Min.
Typ.
Max.
Unit
-
-
330
ns
-
-
66
ns
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note:
[1] tpd is the same as tPLH and tPHL.
[2] tt is the sameastTHL and tTLH.
AC Characteristics 3
(Tamb=-40℃ to +125℃, GND=0V; tr=tf=6ns; CL=50pF, unless otherwise specified.)
Parameter
Conditions
Symbol
SN74HC190
CP to Qn;
see Figure
10
CP to TC;
see Figure
10
propagation
delay
tpd
—
CP to RC;
see Figure 11
—
—
CE to RC;
see Figure
11
Dn to Qn;
see Figure
12
XBLWversion1.0
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VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
Technical Support:4009682003
56
ns
384
ns
77
ns
65
ns
228
ns
46
ns
40
ns
198
ns
40
ns
34
ns
330
ns
66
ns
15 / 24
XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
VCC=6.0V
VCC=2.0V
PL to Qn;
see Figure
13
VCC=4.5V
VCC=6.0V
—
U/D to TC;
see Figure 14
—
—
U/D to RC;
see Figure 14
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
transition time
pulse width
tt
see Figure 15
CP; HIGH or
LOW;
see Figure 10
tW
—
PL; LOW;
see Figure 15
recovery time
trec
PL to CP;
see Figure
15
—
U/D to CP;
see Figure 16
set-up time
—
tsu
Dn to PL;
see Figure 17
CE to CP;
see Figure
16
—
U/D to CP;
see Figure 16
—
hold time
th
Dn to PL;
see Figure 17
CE to CP;
see Figure
16
maximum
frequency
fmax
CP;
see Figure 10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
XBLWversion1.0
tpd
CP to Qn;
www.xinboleic.com
ns
ns
66
ns
56
ns
288
ns
58
ns
49
ns
318
ns
64
ns
54
ns
114
ns
23
ns
-
-
VCC=4.5V
-
-
VCC=6.0V
-
19
ns
VCC=2.0V
234
47
-
-
ns
VCC=4.5V
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
-
-
ns
MHz
-
-
-
-
MHz
-
72
ns
VCC=6.0V
40
VCC=2.0V
150
VCC=4.5V
30
VCC=6.0V
25
VCC=2.0V
54
VCC=4.5V
11
VCC=6.0V
10
VCC=2.0V
306
VCC=4.5V
61
VCC=6.0V
52
VCC=2.0V
150
VCC=4.5V
30
VCC=6.0V
25
VCC=2.0V
210
VCC=4.5V
42
VCC=6.0V
36
VCC=2.0V
0
VCC=4.5V
0
VCC=6.0V
0
VCC=2.0V
0
VCC=4.5V
0
VCC=6.0V
0
VCC=2.0V
0
VCC=4.5V
0
VCC=6.0V
0
VCC=2.0V
2
VCC=4.5V
10
VCC=6.0V
12
SN74HCT190
propagation
56
330
VCC=4.5V
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-
MHz
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
delay
see Figure 10
CP to TC;
see Figure
10
VCC=4.5V
-
-
88
ns
VCC=4.5V
-
-
53
ns
CE to RC;
see Figure
11
Dn to Qn;
see Figure
12
VCC=4.5V
-
-
49
ns
VCC=4.5V
-
-
66
ns
PL to Qn;
see Figure
13
VCC=4.5V
-
-
73
ns
VCC=4.5V
-
-
67
ns
U/D to RC;
VCC=4.5V
see Figure 14
VCC=4.5V; see Figure 15
CP; HIGH or LOW; VCC=4.5V
see Figure 10
-
-
67
ns
-
-
23
ns
37
-
-
ns
PL; LOW; VCC=4.5V; see Figure 15
34
-
-
ns
PL to CP; VCC=4.5V; see Figure 15
11
-
-
ns
U/D to CP; VCC=4.5V; see Figure 16
64
-
-
ns
Dn to PL; VCC=4.5V; see Figure 17
30
-
-
ns
CE to CP; VCC=4.5V;see Figure 16
47
-
-
ns
U/D to CP; VCC=4.5V; see Figure 16
0
-
-
ns
Dn to PL; VCC=4.5V; see Figure 17
0
-
-
ns
CE to CP; VCC=4.5V;see Figure 16
CP;
VCC=4.5V
see Figure 10
0
-
-
ns
11
-
-
MHz
—
CP to RC;
see Figure 11
—
—
—
U/D to TC;
see Figure 14
—
transition time
tt
pulse width
tW
recovery time
set-up time
trec
tsu
—
—
hold time
maximum
frequency
th
fmax
Note:
[1] tpd is the same as tPLH and tPHL.
[2] tt is the sameastTHL and tTLH.
XBLWversion1.0
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Testing Circuit
AC Testing Circuit
Figure 9. Test circuit for measuring switching times
Definitions for test circuit:
CL=Load capacitance including jig and probe capacitance.
RT=Termination resistance should be equal to the output impedance Zo of the pulse generator.
RL=Load resistance.
S1=Test selection switch
AC Testing Waveforms
Figure 10. The clock input (CP) to outputs (Qn, TC) propagation delays, clock pulse width and maximum
clock frequency
Figure 11. The clock and count enable inputs (CP, CE) to ripple clock output (RC) propagation
delays
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Figure 12. The input (Dn) to output (Qn) propagation delays
Figure 13. The parallel load input (PL) to output (Qn) propagation delays
Figure 14. The up/down count input (U/D) to terminal count and ripple clock output (TC,
RC) propagation delays
Figure 15. The parallel load input (PL) to clock (CP) recovery times, parallel load pulse width and
output (Qn) transition times
XBLWversion1.0
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Figure 16. The count enable and up/down count inputs (CE, U/D) to clock input (CP) set-up and
hold times
Figure 17. Waveforms showing the set-up and hold times from the parallel load input (PL) to the
data input (Dn)
Measurement Points
Type
Input
Output
SN74HC190
VM
VM
0.5×VCC
0.5×VCC
SN74HCT190
1.3V
1.3V
Test Data
Type
Input
S1 position
Load
VI
CL
RL
tPLH , tPHL
SN74HC190
t r ,t f
VCC
6ns
15pF, 50pF
1kΩ
open
SN74HCT190
3V
6ns
15pF, 50pF
1kΩ
open
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Package Information
DIP16
XBLWversion1.0
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
SOP16
XBLWversion1.0
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
TSSOP16
XBLWversion1.0
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XBLW SN74HC/HCT190
Asynchronously Presettable Up/Down BCD Decade Counters
Statement：
Shenzhen xinbole electronics co., ltd. reserves the right to change the product specifications, without notice!
Before placing an order, the customer needs to confirm whether the information obtained is the latest version,
and verify the integrity of the relevant information.
Any semiconductor product is liable to fail or malfunction under certain conditions, and the buyer shall be
responsible for complying with safety standards in the system design and whole machine manufacturing using
Shenzhen xinbole electronics co., ltd products, and take appropriate security measures to avoid the potential risk
of failure may result in personal injury or property losses of the situation occurred!
This document is for referenceonly,and the actual use should be based on the application test results.
Product performance is never ending, Shenzhen xinbole electronics co., ltd will be dedicated to provide
customers with better performance, better quality of integrated circuit products.
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