AM35x SOM-M2 Hardware Specification
Hardware Documentation
Logic PD // Products
Published: November 2009
Last revised: July 2010
This document contains valuable proprietary and confidential information and the attached file contains source code, ideas, and
techniques that are owned by Logic Product Development Company (collectively “Logic PD’s Proprietary Information”). Logic PD’s
Proprietary Information may not be used by or disclosed to any third party except under written license from Logic Product
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Logic Product Development Company makes no representation or warranties of any nature or kind regarding Logic PD’s Proprietary
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pursuant and subject to the terms and conditions of a duly executed license or agreement to purchase or lease equipment. The only
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forth in such license or agreement. Logic Product Development Company shall have no liability of any kind, express or implied,
arising out of the use of the Information in this document, including direct, indirect, special or consequential damages.
Logic Product Development Company may have patents, patent applications, trademarks, copyrights, trade secrets, or other
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The Information contained herein is subject to change without notice. Revisions may be issued regarding changes and/or additions.
© Copyright 2010, Logic Product Development Company. All Rights Reserved.
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AM35x SOM-M2 Hardware Specification
Revision History
REV
1
2
3
4
5
A
REVISION DESCRIPTION
Schematic
PN & REV
APPROVAL
DATE
Initial Release
1013603
Rev B
JCA
10/04/09
JCA
Beta Release
1013603
Rev B
JCA
11/04/09
CM
-Section 3.2: Updated DC Main Battery Active Current measurement
and clarified note explaining the conditions of that measurement; Added
note 4 regarding the 802.11 measurements;
-Section 6.3: Changed J3.36 to RFU from NAND_nCS; Changed
voltages for J3.35 and J3.37 to 1.8V from 3.3V or 1.8V; Changed J3.39
to UART_DBG from RFU; Changed J3.41 to BT_DBG from RFU;
Changed J3.46 to NAND_SEL from RFU
-Minor grammatical edits throughout
1014320
Rev A
NJK
02/18/10
JCA
-Added Sections 2.3.4 & 2.3.5 to point to the Appendices for mechanical
drawings
-Added Example Retention Methods mechanical drawings
-Section 3.10.2: Corrected number of McBSPs available on the SOM to 1014320
four since McBSP5 is used by the uP_HSBUSB signal.
Rev A
JCA
04/02/10
JCA
-Section 3.6 & 3.7: Updated MAC address sticker information;
-Section 3.7.1: Added note about FM interface;
-Section 4.5.1.1: Corrected supported voltage range for MAIN_BATT_IN
input;
-Section 6.2 pins J2.49–52: Updated voltage and signal descriptions for 1014320
MAIN_BATT_IN
Rev A
CM
05/27/10
JCA,
NJK
Official Release
-Added FCC Certification language throughout;
-Added 802.11n protocol throughout;
-Changed AM3517 microprocessor core to 600 MHz per TI spec;
-Section 2.3.1: Updated height for wireless configuration; Updated
weight for standard configuration SOM;
-Section 2.3.3: Added antenna note pertaining to FCC guidelines;
-Section 2.4: Added Industrial Temp range and note that Industrial Temp
models do not include Wi-Fi/BT;
-Section 3.1: Added USB0 and USB1 voltage parameters;
-Section 3.2: Updated Note 3 to indicate the Main Battery Active Current
was measured using a fully-populated SOM and the LCD current was
not included in the measurement; Added USB0 and USB1 voltage
parameters; Added 802.11n parameters.
-Added Section 3.7.1: 2.4GHz Antenna Information;
-Added Section 3.7.2: Wireless Software Requirements;
-Section 3.11: Updated USB information to reflect what is available on
the SOM, not the microprocessor;
-Section 4.2: Corrected typo in reset signal names;
-Section 6.1: Throughout, updates to clarify signal descriptions; J1.37
added microprocessor name and voltage; J1.85 specified signal as Input
and 5V, was N/A; Specified or changed IO direction on J1.70, 89, 91;
Added clarification to Note 1 that all IO pins must be set to same
voltage;
-Section 6.2: Throughout, updates to clarify signal descriptions; J2.57
&J2.63 signal descriptions were reversed for Ethernet activity and speed
LEDs, this has been corrected; J2.84 description mistakenly called out
McBSP1 instead of McBSP2; Specified or changed IO direction on
J2.17, 34, 36, 38, 40, 42, 44, 46, 72, 78, 81, 82, 84-86, 88; Added
clarification to Note 1 that all IO pins must be set to same voltage;
-Section 6.3: Throughout, updates to clarify signal descriptions; J3.16
changed direction to Input and updated description; J3.26 description
mistakenly called out McBSP4 instead of McBSP3; J3.47 changed
direction to Output, voltage to 3.3V, and updated description; Specified
or changed IO direction on J3.1-5, 7-13, 15, 23-29, 77, 85-88; Added
clarification to Note 1 that all IO pins must be set to same voltage;
1015592
-Added mechanical drawing for AM35x SOM-M2 with wireless
Rev A
NJK
07/22/10
EDITOR
CM
Please check www.logicpd.com for the latest revision of this specification and other documents.
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AM35x SOM-M2 Hardware Specification
FCC Certification
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This
device may not cause harmful interference, and (2) this device must accept any interference received, including
interference that may cause undesired operation.
Any changes or modifications not expressly approved by Logic PD could void the user's authority to use this device.
See Application Note 447 for FCC guidelines pertaining to use of this device in end products.
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to
part 15 of the FCC Rules. These limits are designed t o provide reasonable protection against harmful interference in
a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed
and used in accordance with the instructions, may cause harmful interference to radio communications. However,
there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful
interference to radio or television reception, which can be determined by turning the equipment off and on, the user is
encouraged to try to correct the interference by one or more of the following measures:
—Reorient or relocate the receiving antenna.
—Increase the separation between the equipment and receiver.
—Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
—Consult the dealer or an experienced radio/TV technician for help.
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AM35x SOM-M2 Hardware Specification
Table of Contents
1
Introduction ........................................................................................................................................... 1
1.1 Product Overview ............................................................................................................................. 1
1.2 Abbreviations, Acronyms, & Definitions ........................................................................................... 1
1.3 Nomenclature ................................................................................................................................... 2
1.4 Scope of Document.......................................................................................................................... 2
1.5 Additional Documentation Resources .............................................................................................. 2
2 Functional Specification ...................................................................................................................... 4
2.1 Microprocessor ................................................................................................................................. 4
2.1.1 AM35x Microprocessor .............................................................................................................. 4
2.1.2 AM35x Microprocessor Block Diagram ..................................................................................... 5
2.2 SOM Interface .................................................................................................................................. 5
2.2.1 AM35x SOM-M2 Block Diagram................................................................................................ 6
2.3 Mechanical Specifications ................................................................................................................ 6
2.3.1 Mechanical Characteristics of SOM-M2 .................................................................................... 6
2.3.2 Interface Connectors ................................................................................................................. 7
2.3.3 Wireless Antenna Connection ................................................................................................... 7
2.3.4 AM35x SOM-M2 Mechanical Drawings ..................................................................................... 7
2.3.5 Example AM35x SOM-M2 Retention Methods .......................................................................... 7
2.4 Temperature Specifications ............................................................................................................. 7
3 Electrical Specification ........................................................................................................................ 8
3.1 Absolute Power Maximum Ratings .................................................................................................. 8
3.2 Recommended Power Operating Conditions................................................................................... 8
3.3 Clocks............................................................................................................................................... 8
3.4 Memory ............................................................................................................................................ 9
3.4.1 Memory Management Unit (MMU) ............................................................................................ 9
3.4.2 DDR ........................................................................................................................................... 9
3.4.3 NAND Flash ............................................................................................................................... 9
3.4.4 MMC/SD Support .................................................................................................................... 10
3.5 DMA ............................................................................................................................................... 10
3.6 10/100 Ethernet PHY ..................................................................................................................... 10
3.7 802.11 Wireless Ethernet + Bluetooth ........................................................................................... 10
3.7.1 2.4 GHz Antenna Information .................................................................................................. 11
3.7.2 Software Requirements ........................................................................................................... 11
3.7.3 FM Interface............................................................................................................................. 11
3.8 Display Interface ............................................................................................................................ 11
3.9 Video Processing Front End .......................................................................................................... 12
3.9.1 TV_OUT................................................................................................................................... 12
3.10 Serial Interfaces ............................................................................................................................. 12
3.10.1 CAN Controller......................................................................................................................... 12
3.10.2 McBSP ..................................................................................................................................... 13
3.10.3 UARTs ..................................................................................................................................... 13
3.10.4 McSPI ...................................................................................................................................... 13
3.10.5 I2C ........................................................................................................................................... 13
3.10.5.1 I2C1 ................................................................................................................................... 14
3.11 USB Interface ................................................................................................................................. 14
3.12 ADC/Touch Interface...................................................................................................................... 15
3.13 Real Time Clock (RTC) .................................................................................................................. 15
3.14 General Purpose I/O (GPIO) .......................................................................................................... 15
3.15 Sysboot I/O .................................................................................................................................... 15
3.16 Expansion/Feature Options ........................................................................................................... 15
4 System Integration ............................................................................................................................. 17
4.1 Custom Configuration .................................................................................................................... 17
4.2 Resets ............................................................................................................................................ 17
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AM35x SOM-M2 Hardware Specification
4.2.1 Master Reset (RESPWRONn)—Reset Input .......................................................................... 17
4.2.2 SOM-M2 Reset (RESOUTn)—Reset Output .......................................................................... 17
4.2.3 SOM-M2 Reset (uP_RESWARMn)—Reset Input/Output ....................................................... 18
4.3 Interrupts ........................................................................................................................................ 18
4.4 JTAG Debugger Interface .............................................................................................................. 18
4.5 Power Management ....................................................................................................................... 18
4.5.1 System Power Supplies ........................................................................................................... 18
4.5.1.1 MAIN_BATT_IN ................................................................................................................ 18
4.5.1.2 VRTC_IN ........................................................................................................................... 19
4.5.2 Dual Voltage I/O ...................................................................................................................... 19
4.5.3 System Power Management ................................................................................................... 19
4.5.4 System Power Sequencing ..................................................................................................... 19
4.6 ESD Considerations ....................................................................................................................... 19
5 Memory & I/O Mapping ....................................................................................................................... 21
6 Pin Descriptions & Functions ........................................................................................................... 22
6.1 J1 Connector 100-Pin Descriptions ............................................................................................... 22
6.2 J2 Connector 100-Pin Descriptions ............................................................................................... 26
6.3 J3 Connector 100-Pin Descriptions ............................................................................................... 30
Appendix A: AM35x SOM-M2 Mechanical Drawing (with Wireless)..................................................... 37
Appendix B: AM35x SOM-M2 Mechanical Drawing (without Wireless) ............................................... 39
Appendix C: Example AM35x SOM-M2 Retention Methods ................................................................. 41
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AM35x SOM-M2 Hardware Specification
Table of Figures
Figure 2.1: AM35x Microprocessor Block Diagram ...................................................................................... 5
Figure 2.2: AM35x SOM-M2 Block Diagram ................................................................................................. 6
Table 2.1: Board-to-Board Socket Connectors Manufacturer Information ................................................... 7
Table 2.2: Wireless Antenna Cable Manufacturer Information ..................................................................... 7
Table 3.1: AM3517Microprocessor Clocks ................................................................................................... 9
Table 3.2: I2C1 Bus Devices & Addresses ................................................................................................. 14
Table 3.3: Boot Strap Options ..................................................................................................................... 15
Table 5.1: Chip Select Signals .................................................................................................................... 21
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AM35x SOM-M2 Hardware Specification
1
Introduction
1.1
Product Overview
The AM35x System on Module (SOM) is a compact, product-ready hardware and software
solution that fast forwards embedded designs. Based on Texas Instruments’ Sitara AM35x
microprocessor and designed in the SOM-M2 form factor, the AM35x SOM-M2 offers essential
features for handheld and embedded networking applications.
The SOM-M2 is an off-the-shelf solution that allows customers to focus on their high-value core
technologies. The standard SOM-M2 form factor allows developers to reuse existing baseboard
designs when upgrading to new AM processors, which extends roadmap possibilities for their
end-product. By starting with the corresponding AM3517 EVM or eXperimenter Development Kit,
engineers can write application software on the same hardware that will be used in the final
product.
The AM35x SOM-M2 is ideal for medical patient monitoring wearables and other portable
instrumentation applications. The AM3517 includes an SGX530 graphics accelerator and multiple
communication ports, including Bluetooth, wireless 802.11b/g/n, and wired 10/100 Ethernet. For
commercial signage, medical imaging, avionics, and industrial displays, the AM3517 SOM-M2
allows for powerful versatility, long-life, and greener products.
1.2
Abbreviations, Acronyms, & Definitions
ADC
BSP
BTB
DDR
DMA
ESD
FIFO
GPIO
GPMC
GPO
HECC
I2C
I2S
IDC
IC
I/O
IRQ
LCD
LDO
McBSP
OTG
PCB
PCMCIA
PHY
PLL
PWM
RTC
SCC
SDIO
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Analog to Digital Converter
Board Support Package
Board-to-Board
Double Data Rate (RAM)
Direct Memory Access
Electrostatic Discharge
First In First Out
General Purpose Input Output
General Purpose Memory Controller
General Purpose Output
High End CAN Controller
Inter-Integrated Circuit
Inter-Integrated Circuit Sound
Insulation Displacement Connector
Integrated Circuit
Input/Output
Interrupt Request
Liquid Crystal Display
Low Dropout (Regulator)
Multi-channel Buffered Serial Port
On-the-Go (USB)
Printed Circuit Board
Personal Computer Memory Card International Association (PC Cards)
Physical Layer
Phase Lock Loop
Pulse Width Modulation
Real Time Clock
Standard CAN Controller
Secure Digital Input Output
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AM35x SOM-M2 Hardware Specification
SDRAM
SCCB
SOM
SOM-M2
SSP
SPI
STN
TFT
TI
TLB
TSC
TTL
UART
1.3
1.4
Nomenclature
■
The terms “SOM” and “SOM-M2” are used interchangeably throughout this document and
can be assumed to mean the same thing within this text. The SOM-M2 is a specific form
factor type of Logic PD’s SOM.
■
Within this document, AM35x is used to denote the AM3505 and AM3517 microprocessors;
where differences between microprocessor features occur, the specific microprocessor name
is used.
Scope of Document
■
1.5
Synchronous Dynamic Random Access Memory
Serial Camera Control Bus
System on Module
SOM form factor type
Synchronous Serial Port
Standard Programming Interface
Super-Twisted Nematic (LCD)
Thin Film Transistor (LCD)
Texas Instruments
Translation Look-Aside Buffer
Touch Screen Controller
Transistor-Transistor Logic
Universal Asynchronous Receive Transmit
This Hardware Specification is unique to the design and use of the AM3517 SOM-M2 as
designed by Logic PD and does not intend to include information outside of that scope.
Detailed information about the Texas Instruments (TI) AM3517 microprocessor or any other
device component on the SOM can be found in their respective manuals and specification
documents; please see Section 1.5 for additional resources.
Additional Documentation Resources
The following documents or documentation resources are referenced within this Hardware
Specification.
■
TI’s AM3517/05 ARM Microprocessor Datasheet, Technical Reference Manual, User Guides,
Application Notes, White Papers, and Errata
http://www.ti.com/am3517
■
TI’s TPS65023 Datasheet
http://focus.ti.com/docs/prod/folders/print/tps65023.html
■
TI’s TSC2004 Datasheet
http://focus.ti.com/docs/prod/folders/print/tsc2004.html
■
ARM Cortex-A8 Technical Reference Manual
http://infocenter.arm.com/help/index.jsp.
■
USB 2.0 Specification, available from USB.org
http://www.usb.org/developers/docs/
■
U-Boot documentation
http://www.denx.de/wiki/U-Boot/WebHome
■
Logic PD AM3517 SOM-M2 BOM, Schematic, and Layout
http://support.logicpd.com/downloads/1238/
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AM35x SOM-M2 Hardware Specification
■
Logic PD AM3517 eXperimenter Baseboard BOM, Schematic, and Layout
http://support.logicpd.com/downloads/1239/
■
Logic PD AM3517 Application Board BOM, Schematic, and Layout
http://support.logicpd.com/downloads/1240/
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AM35x SOM-M2 Hardware Specification
2
Functional Specification
2.1
Microprocessor
2.1.1
AM35x Microprocessor
The AM35x SOM-M2 uses TI’s high-performance Sitara AM35x microprocessor. This device
features the Superscalar ARM® Cortex™-A8 RISC core and provides many integrated on-chip
peripherals, including:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Superscalar ARM® Cortex™-A8 RISC core
□ Vector floating point unit
□ 16 Kbytes instruction L1 cache
□ 16 Kbytes data L1 cache
□ 256 Kbyte L2 cache
□ 64 Kbyte RAM
□ 112 Kbyte ROM
Integrated display sub-system
□ Parallel HD at 24 bit color, plus NTSC, Composite
Video Processing Front End
POWERVR™ SGX530 graphics accelerator from Imagination Technologies (AM3517 only)
SDRAM Memory controller with EMIF4 and 1GByte address space
GPMC memory controller with 16 bit bus, 8 chip selects, and NOR/NAND support
Four UARTs
Five multi-channel buffered serial ports (McBSP)
Four McSPI
CAN controller
Three MMC/SD interfaces
One 1-wire interface
Three I2C interfaces
10/100 MBit Ethernet MAC with RMII interface
High/Full/Low speed USB 2.0 On-the-Go (OTG) interface with integrated PHY
High speed USB 2.0 Host interfaces
Many general purpose I/O (GPIO) signals
Programmable timers
Watchdog timers
Low power modes
IMPORTANT NOTE: The AM35x microprocessor is heavily multiplexed; using one peripheral
may preclude the use of another. Users should carefully review the microprocessor pinout, SOM
pinout, and AM35x multiplexing table. See TI’s AM35x ARM Microprocessor Technical Reference
Manual and Data Sheet for additional information; the documents are available from TI’s website.
IMPORTANT NOTE: Please visit TI’s website for errata on the AM35x.
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AM35x SOM-M2 Hardware Specification
2.1.2
AM35x Microprocessor Block Diagram
Figure 2.1: AM35x Microprocessor Block Diagram
NOTE: The block diagram pictured above comes from TI’s AM3517/05 ARM Microprocessor
Datasheet (document number SPRS550–OCTOBER 2009).
2.2
SOM Interface
Logic PD’s common SOM interface allows for easy migration to new microprocessors and
technology. Logic PD is constantly researching and developing new technologies to improve
performance, lower cost, and increase feature capabilities. By using the common SOM footprint,
it is possible to take advantage of Logic PD’s work without having to re-spin the old design in
certain cases dependent upon peripheral usage. Please contact Logic PD for more information.
In fact, encapsulating a significant amount of your design onto the SOM reduces any long-term
risk of obsolescence. If a component on the SOM design becomes obsolete, Logic PD will simply
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AM35x SOM-M2 Hardware Specification
design for an alternative part that is transparent to your product. Furthermore, Logic PD tests all
SOMs prior to delivery, decreasing time-to-market and ensuring a simpler and less costly
manufacturing process.
2.2.1
AM35x SOM-M2 Block Diagram
Figure 2.2: AM35x SOM-M2 Block Diagram
2.3
Mechanical Specifications
2.3.1
Mechanical Characteristics of SOM-M2
Parameter
Min
Typical
Max
Unit
Dimensions (without wireless)
—
40.9 x 51.2 x 4.4
—
mm
Notes
Dimensions (with wireless)
—
40.9 x 51.2 x 5.4
—
mm
Weight
—
11.0
—
Grams 1
Connector Insertion/Removal
—
30
—
Cycles
NOTES:
1.
May vary depending on SOM configuration.
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AM35x SOM-M2 Hardware Specification
2.3.2
Interface Connectors
The AM35x SOM-M2 connects to a PCB baseboard through three 100-pin board-to-board (BTB)
socket connectors.
Table 2.1: Board-to-Board Socket Connectors Manufacturer Information
2.3.3
Ref Designator
Manufacturer
SOM-M2 Connector P/N
Mating Connector P/N
J1:3
Hirose
DF40C-100DP-0.4V(51)
DF40C-100DS-0.4V(51)
Wireless Antenna Connection
The mechanical drawing in Appendix A shows the location of the 802.11b/g/n Ethernet and
Bluetooth antenna connector (J4) on the top side of the PCB. Table 2.2 contains the
manufacturer information for the cables that Logic PD provides in the AM3517 EVM Development
Kit.
NOTE: To comply with FCC certification already completed on the AM35x SOM-M2, the antenna
selected for an end product must meet FCC guidelines as described in Section 3.7.1.
Table 2.2: Wireless Antenna Cable Manufacturer Information
2.3.4
Ref Designator
Manufacturer
P/N
J4
Hirose
U.FL
Coax cable
Sunridge Corp.
MCBG-RH-54-080-SMAJB281
AM35x SOM-M2 Mechanical Drawings
Please see Appendix A for mechanical drawings of the AM35x SOM-M2 and recommended
baseboard footprint layout.
2.3.5
Example AM35x SOM-M2 Retention Methods
Please see Appendix B for mechanical drawings demonstrating three possible retention methods
for the AM35x SOM-M2. These drawings are only meant to serve as possible solutions and
should not be considered final designs for retention.
2.4
Temperature Specifications
Parameter
Min
Typical
Max
0
25
70
°C
Industrial Operating Temperature
-40
25
85
°C
Storage Temperature
-40
25
85
°C
Commercial Operating Temperature
Unit
Notes
1
NOTES:
1.
Industrial temperature model will be available in the second half of 2010. Industrial
temperature model does not include Wi-Fi/Bluetooth module.
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AM35x SOM-M2 Hardware Specification
3
Electrical Specification
3.1
Absolute Power Maximum Ratings
Parameter
Symbol
Rating
Unit
DC Main Battery Input Voltage
MAIN_BATT_IN
0.0 to 7.0
V
RTC Backup Battery Voltage
VRTC_IN
0.0 to 5
V
USB0 VBUS Voltage
USB0_VBUS
0.0 to 5.5
V
USB1 VBUS Voltage
USB1_VBUS
0.0 to 6.0
V
NOTE: These stress ratings are only for transient conditions. Operation at, or beyond, absolute
maximum rating conditions may affect reliability and cause permanent damage to the SOM-M2
and its components.
3.2
Recommended Power Operating Conditions
Parameter
Min
Typical
Max
Unit
DC Main Battery Input Voltage
3.5
5
6
V
DC Main Battery Active Current
—
302
—
mA
DC RTC Backup Battery Voltage
1.8
3.2
5
V
DC USB0_VBUS Voltage
—
5
—
V
Notes
3
DC USB1_VBUS Voltage
0
5
5.5
V
802.11b Transmit Power
+16
+18
+20
dBm
4
802.11b Receive Sensitivity
802.11g Transmit Power
802.11g Receive Sensitivity
802.11n Transmit Power
802.11n Receive Sensitivity
BT Transmit Power
BT Receive Sensitivity
—
-87
-76
dBm
4
+11
+13
+15
dBm
4
—
-73
-68
dBm
4
+10
+12
+14
dBm
4
-64
dBm
4
dBm
4
dBm
4
V
2
0.35 x VREF V
2
—
-67
+4.5
+8.0
—
-90
-70
Input Signal High Voltage
0.65 x VREF
—
VREF
Input Signal Low Voltage
-0.3
—
Output Signal High Voltage
--
—
VREF
V
Output Signal Low Voltage
GND
—
0.2
V
2
NOTES:
1.
2.
3.
4.
3.3
General note: CPU power rails are sequenced on the module.
VREF represents the peripheral I/O supply reference for the specific CPU voltage rail.
Measured across R178 with 4.2V input. Fully populated SOM running Demo application
on U-Boot/Linux version 2009.08. 4.3” display attached (but current from the display is
not included in the measurement); no other peripherals attached.
Wireless numbers taken from the Murata LBEH19XMMC Module Datasheet (Rev. I).
Logic PD is working to verify these numbers on the SOM application.
Clocks
The AM35x requires an oscillator to enable proper internal timing. A 26.000 MHz oscillator is
used to generate many of the microprocessor’s internal clocks via a series of Phase Lock Loops
(PLLs) and signal dividers. To generate the core CPU clock, the 26.000 MHz signal is run through
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AM35x SOM-M2 Hardware Specification
a Digital PLL controlled by the PRCM registers. Divisors are used to divide down the internal bus
frequency to set the LCD, memory controller, camera interface, etc.
IMPORTANT NOTE: Please see TI’s AM35x ARM Microprocessor Technical Reference Manual
for additional information about microprocessor clocking.
The second required clock runs at 32.768 kHz and is connected directly to the AM35x. The
32.768 kHz clock is used for CPU start up and reference.
The CPU’s core clock speed is initialized by software on the SOM-M2. The SDRAM bus speed is
set at 166 MHz in U-Boot. Other clock speeds, such as core speed and specific serial baud rates,
can be supported and modified in software for specific user applications.
The SOM-M2 provides an external bus clock, uP_OBSCLK. This clock is driven by the
SYS_CLKOUT1 pin.
Table 3.1: AM3517Microprocessor Clocks
AM35x Microprocessor
Signal Name
SOM-M2
Net Name
Default Software Value
in U-Boot
CORE
N/A
Up to 600 MHz
SDRC_CLK
uP_DDR_CLK
166 MHz
SYSCLKOUT1
uP_OBSCLK
26MHz
3.4
Memory
3.4.1
Memory Management Unit (MMU)
The AM35x SOM has one MMU for the microprocessor unit (MPU). The MPU MMU is described
in the ARM Cortex-A8 Technical Reference Manual, available at
http://infocenter.arm.com/help/index.jsp.
3.4.2
DDR
The AM35x SOM uses a 32-bit memory bus to interface to two 16-bit DDR2 SDRAM memories.
The memory on the SOM-M2 included in the AM3517 EVM Development Kit is 256 MB DDR2,
organized as 64 Meg x 32.
Other memory densities may be available for SOMs in production volumes. Please contact Logic
PD about custom configurations if your design requires different memory densities from Logic
PD’s standard SOM configurations.
3.4.3
NAND Flash
The SOM-M2 uses the 16-bit GPMC memory bus to interface to a single 512 MB NAND flash
memory chip.
It is possible to expand the system’s non-volatile storage capability by adding external flash ICs,
SD memory, NOR, or NAND flash on the user application board. See the AM3517 EVM
Development Kit for reference designs or contact Logic PD for other possible peripheral designs.
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3.4.4
MMC/SD Support
The SOM-M2 directly supports a single SD/MMC slot. The SOM-M2 routes the signals for MMC1
to the baseboard connectors, allowing connections on a user design to a socket where a card can
be mounted. MMC1 supports up to 8 data bits. The AM35x microprocessor has functionality for
two more MMC peripherals: MMC2 is used for the Murata Wi-Fi/Bluetooth module on the SOM. It
has functionality on the upper 4 data bits to support direction control for an SD/MMC buffer.
MMC3 is an alternate pin mapping for other peripherals used elsewhere on the SOM.
The AM3517 eXperimenter Board reference design includes a single SD/MMC connector. Please
contact Logic PD for more information on implementing additional slots.
3.5
DMA
The AM35x has several DMA controllers:
■ SDMA – data transfers from the microprocessor to peripherals
■ Display DMA
■ USB High Speed (HS) DMA
The SDMA controller (DMA4) has the following features:
■ 32 channels (independent, concurrent, variable data size, burst/chain, endian conversion)
■ Memory to memory, memory to peripheral
■ Interrupts
■ 256 32-bit FIFOs
3.6
10/100 Ethernet PHY
The AM35x SOM-M2 uses an SMSC LAN8710 Ethernet PHY to provide an easy-to-use
networking interface. The four analog PHY interface signals (transmit/receive) each require an
external impedance matching circuit to operate properly. Logic PD provides an example circuit
schematic in the AM35x eXperimenter Board Schematics. Please note the TX+/- and RX+/- pairs
must be routed as differential pairs (at 100 ohms) on the baseboard PCB.
The 10/100 Ethernet MAC address can be found in two ways. One, the MAC address is printed
on a sticker affixed to the top side of the SOM and is the address that does not follow this
convention: 00:08:EE:xx:xx:xx. Two, the 10/100 Ethernet MAC address is stored within the
AM35x microprocessor and can be obtained using software; please refer to TI’s AM35x ARM
Microprocessor Technical Reference Manual for this procedure.
3.7
802.11 Wireless Ethernet + Bluetooth
The SOM-M2 uses a Murata LBEH19XMMC 802.11b/g/n + Bluetooth 2.1 Wireless IC to provide
an easy-to-use wireless networking interface. The LBEH19XMMC is connected to the AM35x
through a combination of MMC, SDIO, and GPIO. The RF connector is located on the SOM at
reference designator J4; J4 is shared between 802.11 and Bluetooth.
The MAC address for 802.11b/g/n is printed on a sticker affixed to the top side of the SOM. The
802.11b/g/n MAC address follows this convention: 00:08:EE:xx:xx:xx
NOTE: Transmit power (VBAT) comes from U22, which converts the incoming voltage
(MAIN_BATT_IN) to ~3.5V.
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NOTE: See Application Note 447 for FCC guidelines pertaining to use of the AM35x SOM-M2 in
end products.
3.7.1
2.4 GHz Antenna Information
The AM35x SOM-M2 has been qualified to use a Pulse W1038, 4.9 dBi Omni-directional
antenna. Use of this antenna will satisfy FCC regulations. A different Omni-directional antenna
with a peak gain of 4.9 dBi or less may be substituted and still satisfy FCC regulations. If an
antenna with higher gain or of a different type is to be used, the end product must be put through
intentional radiation testing at a qualified test lab. Please refer to FCC rules 47 CFR § 15.204 for
more information.
3.7.2
Software Requirements
In order to be FCC compliant with the 802.11b/g/n and Bluetooth devices, the following software
must be used:
■
■
802.11b/g/n:
Bluetooth:
Firmware Version: Rev 6.1.0.0.313
Firmware Version: 7.2.31; initialization script TI_P31.91
Any other version of the firmware must be approved by the FCC. If another version of the
firmware is desired, please contact Logic PD for assistance with certification.
3.7.3
FM Interface
The Murata module on the SOM-M2 has FM capabilities. FM signals are routed to the baseboard
connectors (see Section 6) for connection to audio processing and antenna.
NOTE: The FM interface is untested and not supported with software.
IMPORTANT NOTE: The FCC certification for the AM35x SOM-M2 does not cover FM signals;
therefore, use of FM signals will require independent FCC testing and certification.
3.8
Display Interface
The AM35x has a built-in graphics controller supporting up to 24-bit parallel RGB (pixel rates up
to 74.25 MHz enabling HD resolutions) along with two 10-bit Digital-to-Analog Converters (DAC)
supporting composite NTSC/PAL video and Luma/Chroma Separate Video (S-Video). Image
rotation, resizing, color space conversion, and 8-bit alpha blending functions are built in. See TI’s
AM35x Technical Reference Manual for further information on the integrated LCD controller.
The signals from the AM35x LCD controller are organized by bit and color and can be interfaced
through the SOM-M2 expansion connectors. The signals from the SOM-M2 are driven from the
3.3V_or_1.8V rail. Logic PD has written drivers for panels of different types and sizes. Please
contact Logic PD before selecting a display for your application.
NOTE: In 3.3V IO mode, an LCD can be driven directly from the AM3517.
NOTE: The eXperimenter Baseboard uses the standard Logic PD 16-bit LCD interface as well as
a 24-bit HDMI transceiver.
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AM35x SOM-M2 Hardware Specification
IMPORTANT NOTE: Using the internal graphics controller may affect microprocessor
performance. Selecting display resolutions and color bits per pixel will vary microprocessor
busload.
3.9
Video Processing Front End
The AM35x has a built-in 16-bit video input port supporting RAW data interface, up 75 MHz pixel
clock, REC656/CCIR656, YCbCr422 format (8- and 16-bit), black clamping signal generation,
10-bit to 8-bit A-law compression, and up to 16K pixels in horizontal and vertical directions. The
signal input to the VPFE is through the CCDC bus connections. The SOM-M2 supports an 8-bit
video input interface with control lines on the CCDC bus (see Section 6). See TI’s AM35x
Technical Reference Manual and Logic PD’s AM3517 Application Board Schematics for
connection details.
3.9.1
TV_OUT
The AM35x supports S-Video on the TV_OUT signals (see Section 6 for details). Note that the
TV_OUT signals need to be routed at 75 ohms single ended. There are optional noise-filtering
component locations on the SOM-M2 for the TV_OUT signals.
3.10
Serial Interfaces
The SOM-M2 comes with the following serial channels: high end CAN controller, multichannel
buffered serial ports (McBSPs), four McSPI ports, up to four UARTS, and three I2C ports. If
additional serial channels are required, please contact Logic PD for reference designs. Please
see TI’s AM35x Technical Reference Manual for further information regarding serial
communications.
3.10.1 CAN Controller
The AM3517 has a high performance CAN 2.0B controller. It includes a CAN Protocol Kernel, a
Standard CAN Controller (SCC), and a High End CAN Controller (HECC). The SCC supports 16
receive/transmit message objects, while the HECC supports 32 receive/transmit message
objects. The HECC also supports 32 receive-identifier masks.
Other features of the CAN controller include:
■
■
■
■
■
■
■
■
1 Mbps data rate
Programmable sampling rate
Selectable edge for synchronization
Automatic re-transmission
Bus failure diagnostic
Self test
Wake-up on bus activity
Auto reply
The signals from the SOM-M2 are driven from the 3.3V_or_1.8V rail. The end-product design
must provide an external CAN transceiver. Logic PD has provided an example reference design
with the AM3517 Application Board Schematics. When choosing a CAN transceiver, the designer
should keep in mind bus loading, availability, ESD protection, and data rates.
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3.10.2 McBSP
The SOM-M2 provides access to four multi-channel buffered serial ports (McBSP) with the
following capabilities:
■
■
■
■
■
■
Full-duplex and multi-drop
512B FIFO on McBSP1, 3, 4; 5KB FIFO on McBSP2
Max data rate of 48 Mbps
I2S, PCM, and TDMI support
Support for external clocks and frame sync
Sidetone support on McBSP2/3 (requires channels are looped back)
The signals from the SOM-M2 are scaled to IO voltage levels (3.3V_or_1.8V), not RS232 level
signals.
NOTE: McBSP5 is an alternate pin mapping of the HSUSB bus. On the AM35x SOM-M2,
uP_HSUSB is used for the USB host port and McBSP5 is not available.
3.10.3 UARTs
The AM35x microprocessor has up to four asynchronous serial ports with the following
capabilities:
■
■
■
■
■
16C750-compatible.
IrDA and CIR support (UART3 only)
64 byte FIFO on receive and transmit
Hardware or software flow control
Baud rates to 3686400 bps
The signals from the SOM-M2 are TTL level signals (3.3V_or_1.8V), not RS232 level signals.
NOTE: UART4 is an alternate pin function of GPMC_WAIT1/2.
3.10.4 McSPI
The SOM-M2 makes McSPI ports 1 and 2 available. They have the following characteristics:
■
■
■
■
■
■
■
Four channels / chip selects (McSPI1)
Two channels / chip selects (McSPI2)
Programmable frequency, polarity, and phase for each channel
SPI word lengths ranging from 4 bits to 32 bits
Up to four master channels or single channel in slave mode
Master multichannel mode with either full duplex or half duplex
64 byte FIFO
Please see TI’s AM35xx Technical Reference Manual for further information. The signals from the
SOM-M2 are TTL level signals (3.3V or 1.8V), not RS232 level signals. Note that McSPI3 is an
alternate function of MMC2, which is used for the on-board Murata WiFi module.
3.10.5 I2C
The AM35x microprocessor has three I2C ports with the following characteristics:
■
■
■
Slave or master mode
Serial camera control bus (SCCB) mode
Compliant with I2C version 2.1
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AM35x SOM-M2 Hardware Specification
■
■
■
■
Standard (100Kbps) and fast mode (400Kbps)
High-speed mode up to 3.4Mbps
7- and 10-bit addressing
8 byte (I2C1, I2C2) and 64 byte (I2C3) FIFOs
Please see TI’s AM35x ARM Microprocessor Technical Reference Manual for further information.
The signals from the SOM-M2 are TTL level signals (3.3V or 1.8V), not RS232 level signals.
3.10.5.1 I2C1
Table 3.2 lists the devices that are connected to the SOM-M2 I2C1 bus.
IMPORTANT NOTE: the INA219 Power Measurement ICs are only populated on the AM3517
SOM-M2 included with the AM3517 EVM Development Kit; they are connected to I2C1 only when
resistors R200 and R201 are populated.
Table 3.2: I2C1 Bus Devices & Addresses
3.11
Device
Hex Address
S35390
0x30
Binary Address Function
0b0110000
RTC on I2C1
TPS65023
0x48
0b1001000
PMIC on I2C1
TSC2004
0x4B
0b1001011
Touch on I2C1
INA219
0x40
0b1000000
5V power measure on PM/I2C1
INA219
0x41
0b1000001
1.2V power measure on PM/I2C1
INA219
0x42
0b1000010
VIO power measure on PM/I2C1
INA219
0x43
0b1000011
1.8V power measure on PM/I2C1
USB Interface
The AM35x SOM-M2 supports one USB 2.0 high-speed host port and one USB 2.0 OTG port; the
USB PHY for the OTG port (USB0) is internal to the AM35x microprocessor. The SOM-M2 adds
an external SMSC USB3320 PHY connected to the HSUSB bus to implement a high-speed host
port (USB1). All ports can operate at up to 480 Mbit/sec.
NOTE: The host port (USB1) does not support full- or low-speed; to use full- or low-speed
peripherals, an external hub is required.
A second host port can be implemented by connecting to the ETK bus (labeled uP_HSUSB1) on
connector J3. The third host port is an alternate pin function of other interfaces. Refer to the
AM3517 Application Board Schematics for example circuitry.
For more information on pin-mapping and using both USB host and OTG interfaces, please see
TI’s AM35xx Technical Reference Manual.
IMPORTANT NOTE: In order to correctly implement USB on the SOM-M2, additional impedance
matching circuitry may be required on the USBx_D+ and USBx_D- signals before they can be
used. USB 2.0 requirements specify the signals must be routed as differential pairs with a 90 ohm
differential impedance. Refer to the USB 2.0 Specification for detailed information.
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AM35x SOM-M2 Hardware Specification
3.12
ADC/Touch Interface
The SOM-M2 uses TI’s TSC2004 touch screen controller (TSC). The controller includes a 12-bit
analog-to-digital converter (ADC). This TSC is used to support standard 4-wire resistive touch
panels and one auxiliary A/D signal. The device is connected to the CPU by the I2C1 interface.
Please see TI’s TSC2004 Datasheet for more information.
3.13
Real Time Clock (RTC)
The SOM-M2 has a Seiko S35390 real time clock connected to I2C1. Note that the RTC requires
an additional voltage (VRTC_IN) to operate and to perform timekeeping when MAIN_BATT_IN is
not present.
The voltage for the RTC comes from VRTC_IN (see Section 6). The AM3517 EVM Development
Kit reference design includes example circuitry to power VRTC_IN from either the power supply
or backup battery.
3.14
General Purpose I/O (GPIO)
Logic PD designed the SOM-M2 to be flexible and provide multiple options for analog and digital
GPIO. There are numerous digital GPIO pins on the SOM-M2 that interface to the AM35x. See
Section 6 of this document for more information. If certain peripherals are not desired, such as
the LCD controller, chip selects, or UARTs, then more GPIO pins become available.
3.15
Sysboot I/O
The AM35x has eight lines dedicated for Sysboot functionality. Two of these are pulled down on
the SOM and not connected externally (uP_SYSBOOT7:8); the remainder are routed to the
baseboard connectors. Default resistors on the SOM-M2 set a boot order of: NAND, EMAC, USB,
MMC1.
Changes to the boot order can be made with baseboard circuitry; however, four of the Sysboot
lines (Sysboot1,3,4,6) are used as GPIO on the SOM-M2 after boot.
IMPORTANT NOTE: When using the Sysboot pins as IO, be aware that they cannot be driven
during reset.
Table 3.3: Boot Strap Options
3.16
BOOT[8:0]
Boot Order [BOOT5 = 0 default]
Boot Order [BOOT5 = 1]
0b0 01X0 1100
(Default) NAND, EMAC, USB, MMC1
EMAC, USB, MMC1, NAND
0b0 01X0 1101
XIP, USB, UART, MMC1
USB, UART, MMC1, XIP
0b0 01X0 1000
XDOC, EMAC, USB, EMAC
USB, XDOC
0b0 01X0 1001
MMC2, EMAC, USB, EMAC
USB, MMC2
Expansion/Feature Options
The SOM was designed for expansion and a variable feature set, providing all the necessary
control signals and bus signals to expand the user’s design. Some of these signals are buffered
and brought out to the expansion connectors. It is possible for a user to expand the SOM’s
functionality even further by adding host bus or ISA bus devices. Some features that are
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AM35x SOM-M2 Hardware Specification
implemented on the AM35x microprocessor, but are not discussed herein, include: pulse width
modulation (PWM), Secure Digital, MMC cards, SDIO cards, 1wire interface, watchdog timers, or
the debug module. See TI’s AM35xx Technical Reference Manual and Logic PD’s AM3517 SOMM2 Schematics for more details. Logic PD has experience implementing additional options,
including other audio codecs, Ethernet ICs, co-processors, and components on SOMs. Please
contact Logic PD for potential reference designs before selecting your peripherals.
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AM35x SOM-M2 Hardware Specification
4
System Integration
4.1
Custom Configuration
The AM3517 SOM-M2 was designed to meet multiple applications for users with specific design
and budget requirements. As a result, this SOM supports a variety of embedded operating
systems, flexible DDR and flash memory footprints, and other hardware configurations. If your
application needs require unique hardware or software configurations, please contact Logic PD
about custom SOMs available in production volumes.
4.2
Resets
The SOM-M2 has a reset input (RESPWRONn) and a reset output (RESOUTn). External devices
should use RESPWRONn to assert reset to the product. The SOM-M2 uses RESOUTn to
indicate to other devices that the SOM-M2 is in reset.
4.2.1
Master Reset (RESPWRONn)—Reset Input
Logic PD suggests that custom designs implementing the AM35x SOM-M2 use the RESPWRONn
signal as the “pin-hole” reset used in commercial embedded systems. The RESPWRONn triggers
a power-on-reset event to the AM35x microprocessor via the TPS65023 PMIC and resets the
entire CPU.
IMPORTANT NOTE: Any custom reset circuit design should guard the assertion of the reset lines
during a low power state so as to prevent power-up in a low or bad power condition. (Powering up
in a low or bad power condition will cause data corruption and, possibly, temporary system lock.
Either one of the following two conditions will cause a system-wide reset: power on the
RESPWRONn signal or a low pulse on the RESPWRONn signal.
Low Pulse on RESPWRONn Signal
A low pulse on the RESPWRONn signal for longer than 30mS—asserted by an external source
(for example, the reset button on the custom design application)—will bring RESOUTn low for
100mS after the assertion source is de-asserted.
Logic PD suggests that for any external assertion source that triggers the RESPWRONn signal,
analog or digital, de-bouncing should be used to generate a clean, one-shot reset signal.
4.2.2
SOM-M2 Reset (RESOUTn)—Reset Output
All hardware peripherals should connect their hardware-reset pin to the RESOUTn signal on the
expansion connector. Internally, all SOM-M2 peripheral hardware reset pins are connected to the
RESOUTn net.
If the reset circuit is asserted (active low), the user can expect to lose information stored in RAM.
The data loss occurs because the CPU is reset to its reset defaults.
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AM35x SOM-M2 Hardware Specification
4.2.3
SOM-M2 Reset (uP_RESWARMn)—Reset Input/Output
uP_RESWARMn is the raw AM35x reset I/O. As such, it is sensitive to external loading and no
devices with active pull-ups should be added to this line. It is permissible to have active low
circuitry on this line.
4.3
Interrupts
The AM35x incorporates the ARM Cortex-A8 interrupt controller which provides many
inter-system interrupt sources and destinations. Most external GPIO signals can also be
configured as interrupt inputs by configuring their pin control registers. Logic PD BSPs setup and
process all SOM-M2 interrupt sources, onboard and external. Refer to TI’s AM35xx Reference
Manual for further information on using interrupts. IRQn is routed to the baseboard, see Section 6
for details.
4.4
JTAG Debugger Interface
The JTAG connection on the AM35x allows recovery of corrupted flash memory, and real-time
application debug. There are several third-party JTAG debuggers available for TI
microprocessors. The following signals make up the JTAG interface to the AM35x
microprocessor: TDI, TMS, TCK, TDO, nTRST, RTCK, EMU0, EMU1, and RESOUTn (RESOUTn
is only required for some JTAG tools; see the JTAG tool documentation for exact pinout). These
signals should interface directly to a 20-pin 0.1” through-hole connector, as shown on the
AM3517 eXperimenter Baseboard Schematics.
IMPORTANT NOTE: When laying out the 20-pin connector, realize that it may not be numbered
as a standard 20-pin 0.1” insulation displacement connector (IDC) through-hole connector. See
the EVM Development Kit reference design for further details. Each JTAG tool vendor may define
the 20-pin IDC connector pin-out differently.
4.5
Power Management
4.5.1
System Power Supplies
In order to ensure a flexible design, the SOM-M2 has the following power inputs: MAIN_BATT_IN
and VRTC. MAIN_BATT_IN is the power input to the SOM-M2 PMIC (TPS65023). The
TPS65023 generates the on-board voltages for the AM35x and associated peripherals.
Note that 3.3V_or_1.8V is an output of the SOM PMIC, and is the selectable IO voltage rail. The
setting is determined by the baseboard design by using signal IO_VOLTAGE_SEL (see Section 6
for details).
IMPORTANT NOTE: 3.3V_or_1.8V is an output from the SOM-M2, and should only be used as a
reference voltage input to level shifting devices on baseboard designs.
4.5.1.1
MAIN_BATT_IN
The MAIN_BATT_IN input is the main source of power for the SOM-M2. In normal configuration,
this input expects a voltage from 3.5V to 5V. The TPS65023 power management controller takes
the MAIN_BATT_IN rail input and creates all onboard voltages. If the design is required to
maintain RAM contents in a critical power situation (e.g., low battery, loss of power), the
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AM35x SOM-M2 Hardware Specification
MAIN_BATT_IN supply should be maintained above the minimum level at all costs (see Section
2).
4.5.1.2
VRTC_IN
VRTC_IN is used to power the real time clock, U35. Always power this rail to maintain the clock
and power state of the product. A lithium-ion coin cell typically supplies power to this rail. See the
AM3517 eXperimenter Baseboard Schematic for details on powering VRTC_IN.
4.5.2
Dual Voltage I/O
The AM35x microprocessor and SOM-M2 uniquely support dual-voltage I/O. The user may select
an operating voltage of either 1.8V or 3.3V through “IO_VOLTAGE_SEL” J1.37. For 3.3V
operation, J1.37 should be left unconnected. For 1.8V operation, J1.37 should be tied directly to
GND.
IMPORTANT NOTE: The IO_VOLTAGE_SEL line should only be changed with the SOM
powered off.
4.5.3
System Power Management
Good power management design is important in any system development and embedded system
design is no exception. In embedded system design, power management is typically one of the
most complicated areas due to the dramatic effect it has on product cost, performance, usability,
and overall customer satisfaction. Many factors affect a power-efficient hardware design: power
supply selection (efficiency), clocking design, IC and component selection, etc. The SOM was
designed with these aspects in mind while also providing maximum flexibility in software and
system integration.
On the AM35x there are many different software configurations that drastically affect power
consumption: microprocessor core clock frequency, bus clock frequency, peripheral clocks, bus
modes, power management states; peripheral power states and modes; product user scenarios;
interrupt handling; and display settings (resolution, backlight, refresh, bits per pixel, etc). These
settings are typically initialized in the startup software routines and may be modified later in the
operating system and application software. Information for these items can be found in the
appropriate documents such as the U-Boot User’s Manual or the specific BSP manual.
4.5.4
System Power Sequencing
Power sequencing for the AM35x is handled by the TPS65023 PMIC.
IMPORTANT NOTE: External circuitry should guarantee that any voltages applied to SOM pins
are present only after the SOM-M2 has completed its power up sequence. Failure to do so may
result in erratic SOM-M2 operation or device damage. One way to ensure this is to use the
external reset (RESOUTn) as a gating signal for all external power supplies.
4.6
ESD Considerations
The SOM was designed to interface to a customer’s peripheral board, while remaining low cost
and adaptable to many different applications. The SOM does not provide any onboard ESD
protection circuitry—this must be provided by the product it is used in. Logic PD has extensive
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AM35x SOM-M2 Hardware Specification
experience in designing products with ESD requirements. Please contact Logic PD if you need
any assistance in ESD design considerations.
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AM35x SOM-M2 Hardware Specification
5
Memory & I/O Mapping
On the AM35x microprocessor, all address mapping for the GPMC chip select signals is listed
below.
Mapped “Chip Select” signals for the AM35x are available as outputs from the microprocessor
and are assigned as described in Table 5.1.
Table 5.1: Chip Select Signals
Chip Select
Device/Feature
Notes
nCS0
NAND / boot NOR
Boot chip select for NAND device or external NOR
(when configured on AM3517 Application Board)
nCS1
External CS
Available for use by an off-board external device
nCS2
External CS
Available for use by an off-board external device
nCS3
External CS
Available for use by an off-board external device
nCS4:7
Used as GPIO
See Section 6 for details
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AM35x SOM-M2 Hardware Specification
6
Pin Descriptions & Functions
SOM Net Name: This is the name used in Logic PD’s AM3517 SOM-M2 Schematics.
Microprocessor Name: This is the name used TI’s AM35x ARM Microprocessor Datasheet.
I/O: This indicates the default pin usage. Most pins can be configured as either input or output.
Consult Logic PD’s AM3517 SOM-M2 Schematics and TI’s AM35x ARM Microprocessor
Datasheet for more information.
IMPORTANT NOTE: All IO is run at either 3.3V or 1.8V; there is no individual pin selection of IO
voltages.
Description: If a pull-up or pull-down resistor is present on the AM3517 SOM-M2, it will be noted
here. Special usage tips and cautions will be noted here. Consult Logic PD’s AM3517 SOM-M2
Schematics and TI’s AM35x ARM Microprocessor Datasheet for more information.
6.1
J1 Connector 100-Pin Descriptions
J1 Pin# SOM Net Name
1
uP_DSS_DOUT8
2
uP_DSS_DOUT0
3
uP_DSS_DOUT9
4
uP_DSS_DOUT1
5
uP_DSS_DOUT10
6
uP_DSS_DOUT2
7
uP_DSS_DOUT11
8
uP_DSS_DOUT3
9
uP_DSS_DOUT12
10
uP_DSS_DOUT4
11
uP_DSS_DOUT13
12
uP_DSS_DOUT5
13
uP_DSS_DOUT14
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Microprocessor
Name
I/O Voltage
Description
DSS_DATA8/GPIO
3.3V or 1.8V LCD G3 data bit when operating in 16 bpp
_78/HW_DBG16
O (see Note 1) 5:6:5 color mode.
DSS_DATA0/UAR
T1_CTS/DSSVEN
3.3V or 1.8V LCD B1 data bit when operating in 16 bpp
C656_DATA0/GPI
O_70
O (see Note 1) 5:6:5 color mode.
DSS_DATA9/GPIO
3.3V or 1.8V LCD_G4 data bit when operating in 16 bpp
_79/HW_DBG17
O (see Note 1) 5:6:5 color mode.
DSS_DATA1/UAR
T1_RTS/DSSVEN
3.3V or 1.8V LCD_B2 data bit when operating in 16 bpp
C656_DATA1/GPI
O_71
O (see Note 1) 5:6:5 color mode.
DSS_DATA10/GPI
3.3V or 1.8V LCD_G5 data bit when operating in 16 bpp
O_80
O (see Note 1) 5:6:5 color mode.
DSS_DATA2/DSS
VENC656_DATA2/
3.3V or 1.8V LCD_B3 data bit when operating in 16 bpp
GPIO_72
O (see Note 1) 5:6:5 color mode.
DSS_DATA11/GPI
3.3V or 1.8V LCD_R1 data bit when operating in 16 bpp
O_81
O (see Note 1) 5:6:5 color mode.
DSS_DATA3/DSS
VENC656_DATA3/
3.3V or 1.8V LCD_B4 data bit when operating in 16 bpp
GPIO_73
O (see Note 1) 5:6:5 color mode.
DSS_DATA12/GPI
3.3V or 1.8V LCD_R2 data bit when operating in 16 bpp
O_82
O (see Note 1) 5:6:5 color mode.
LCD_B5 data bit when operating in 16 bpp
DSS_DATA4/UAR
5:6:5 color mode. Notice that LCD_B0 is
T3_RX_IRRX/DSS
omitted; LCD_B5 (Blue MSB) is also
3.3V or 1.8V connected to LCD_B0 (Blue LSB) when
VENC656_DATA4/
GPIO_74
O (see Note 1) driving an 18 bit display with 16 bits.
DSS_DATA13/GPI
3.3V or 1.8V LCD_R3 data bit when operating in 16 bpp
O_83
O (see Note 1) 5:6:5 color mode.
DSS_DATA5/UAR
T3_TX_IRTX/DSS
3.3V or 1.8V LCD_G0 data bit when operating in 16 bpp
VENC656_DATA5/
GPIO_75
O (see Note 1) 5:6:5 color mode.
DSS_DATA14/GPI
3.3V or 1.8V LCD_R4 data bit when operating in 16 bpp
O_84
O (see Note 1) 5:6:5 color mode.
Logic Product Development Company, All Rights Reserved
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AM35x SOM-M2 Hardware Specification
Microprocessor
Name
DSS_DATA6/UAR
T1_TX/DSSVENC
656_DATA6/GPIO
_76/HW_DBG14
J1 Pin# SOM Net Name
14
uP_DSS_DOUT6
15
uP_DSS_DOUT15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I/O Voltage
O
Description
3.3V or 1.8V LCD_G1 data bit when operating in 16 bpp
(see Note 1) 5:6:5 color mode.
LCD_R5 data bit when operating in 16 bpp
5:6:5 color mode. Notice that LCD_R0 is
omitted; LCD_R5 (Red MSB) is also
3.3V or 1.8V connected to LCD_R0 (Red LSB) when
(see Note 1) driving an 18 bit display with 16 bits.
DSS_DATA15/GPI
O_85
O
DSS_DATA7/UAR
T1_RX/DSSVENC
3.3V or 1.8V LCD_G2 data bit when operating in 16 bpp
656_DATA7/GPIO
uP_DSS_DOUT7
_77/HW_DBG15
O (see Note 1) 5:6:5 color mode.
DSS_HSYNC/GPI
3.3V or 1.8V
uP_DSS_HSYNC
O_67/HW_DBG13 O (see Note 1) LCD Horizontal Sync signal.
DSS_PCLK/GPIO_
3.3V or 1.8V LCD Pixel Clock signal. This signal has a
uP_DSS_PCLK
66/HW_DBG12
O (see Note 1) 22 ohm series resistor on the SOM.
DGND
VSS
I GND
Ground. Connect to digital ground.
DGND
VSS
I GND
Ground. Connect to digital ground.
DSS_VSYNC/GPI
3.3V or 1.8V
uP_DSS_VSYNC
O_68
O (see Note 1) LCD Vertical Sync signal.
RFU
—
NA NA
Reserved for future use. Do not connect.
3.3V or 1.8V LCD AC bias control (STN) or pixel data
DSS_ACBIAS/GPI
uP_DSS_ACBIAS
O_69
O (see Note 1) enable (TFT) signal.
CCDC_PCLK/GPI
3.3V or 1.8V
CCDC_PCLK
O_94/HW_DBG0
I (see Note 1) Video Processor Pixel Clock signal.
USB0_DRVVBUS/
UART3_TX_IRTX/
3.3V or 1.8V Power enable for external USB0 power
uP_USB0_DRVVBUS GPIO_125
O (see Note 1) switch.
CCDC_HD/UART4
3.3V or 1.8V
CCDC_HD
_RTS/GPIO_96
I (see Note 1) Video Processor Horizontal Sync signal.
FM_AINR
—
I Analog input to FM on Murata module.
CCDC_VD/UART4
3.3V or 1.8V
_CTS/GPIO_97/H
CCDC_VD
W_DBG2
I (see Note 1) Video Processor Vertical Sync signal.
Active low. External reset input to the
SOM-M2. This signal should be used to
reset all devices on the SOM-M2 including
TPS65023
MAIN_BATT_ the CPU. 4.7k pull-up on SOM to
RESPWRONn
HOT_RESET
I IN
MAIN_BATT_IN.
CCDC_WEN/CCD
C_DATA9/UART4_
3.3V or 1.8V Video Processor Memory Write Enable
RX/GPIO_98/HW_
CCDC_WEN
DBG3
I (see Note 1) signal.
Active low. Software can use as a
SYS_NIRQ/GPIO_
3.3V or 1.8V hardware interrupt. This signal has a 4.7k
IRQn
0
I (see Note 1) pull-up on the SOM.
CCDC_FIELD/CC
DC_DATA8/UART
3.3V or 1.8V
4_TX/I2C3_SCL/G
CCDC_FLD
PIO_95/HW_DBG1 I (see Note 1) Video Processor Field ID signal.
RFU
—
NA NA
Reserved for future use. Do not connect.
CCDC_DATA7/GP
3.3V or 1.8V
CCDC_D7
IO_106
I (see Note 1) Video Processor data bit 7.
RFU
—
NA NA
Reserved for future use. Do not connect.
CCDC_DATA6/GP
3.3V or 1.8V
CCDC_D6
IO_105
I (see Note 1) Video Processor data bit 6.
PN 1014249 Rev A
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AM35x SOM-M2 Hardware Specification
Microprocessor
Name
J1 Pin# SOM Net Name
37
IO_VOLTAGE_SEL
38
39
CCDC_D5
FM_AOUTR
40
41
CCDC_D4
FM_AOUTL
42
43
CCDC_D3
DGND
44
45
UART1_TX
FM_RXI
46
47
UART1_CTS
DGND
48
UART1_RTS
49
CAN_RX
50
UART1_RX
51
CAN_TX
52
53
UART3_RTS
DGND
54
55
UART3_CTS
FM_TXO
56
57
MMC1_D6
FM_AINL
58
MMC1_D7
59
MMC1_D0
60
MMC2_D0
61
MMC1_D1
62
MMC2_D1
63
MMC1_D2
64
MMC2_D2
PN 1014249 Rev A
TPS65023
DEFDCDC2
CCDC_DATA5/GP
IO_104/HW_DBG7
-CCDC_DATA4/GP
IO_103/HW_DBG6
-CCDC_DATA3/GP
IO_102/HW_DBG5
—
UART1_TX/GPIO_
148
-UART1_CTS/GPIO
_150
—
UART1_RTS/GPIO
_149
HECC1_RXD/UAR
T3_RTS_SD/GPIO
_131
UART1_RX/MCBS
P1_CLKR/MCSPI4
_CLK/GPIO_151
HECC1_TXD/UAR
T3_RX_IRRX/GPI
O_130
UART3_RTS_SD/
GPIO_164
—
UART3_CTS_RCT
X/GPIO_163
-MMC1_DAT6/GPI
O_128
-MMC1_DAT7/GPI
O_129
MMC1_DAT0/MCS
PI2_CLK/GPIO_12
2
MMC2_DAT0/MCS
PI3_SOMI/UART4
_TX/GPIO_132
MMC1_DAT1/MCS
PI2_SIMO/GPIO_1
23
MMC2_DAT1/UAR
T4_RX/GPIO_133
MMC1_DAT2/MCS
PI2_SOMI/GPIO_1
24
MMC2_DAT2/MCS
PI3_CS1/GPIO_13
4
I/O Voltage
O
Description
Input to TPS65023 PMIC. This signal has a
MAIN_BATT_ 4.7k pull-up resistor. See Section 4.5.2 for
IN
more information.
3.3V or 1.8V
(see Note 1) Video Processor data bit 5.
-Connected to FM output of Murata module.
3.3V or 1.8V
(see Note 1) Video Processor data bit 4.
Connected to FM output of Murata module.
3.3V or 1.8V
(see Note 1) Video Processor data bit 3.
GND
Ground. Connect to digital ground.
3.3V or 1.8V
(see Note 1) UART1 Transmit signal.
—
RX input of Murata module
3.3V or 1.8V
(see Note 1) UART1 Clear To Send signal.
GND
Ground. Connect to digital ground.
3.3V or 1.8V
(see Note 1) UART1 Ready To Send signal.
I
3.3V or 1.8V HECC Receive input. Connect to CAN
(see Note 1) transceiver on baseboard.
I
3.3V or 1.8V
(see Note 1) UART1 Receive signal.
I
I
O
I
O
I
I
O
I
I
I
3.3V or 1.8V
(see Note 1)
3.3V or 1.8V
O (see Note 1)
I GND
3.3V or 1.8V
I (see Note 1)
O —
3.3V or 1.8V
I/O (see Note 1)
I —
3.3V or 1.8V
I/O (see Note 1)
O
HECC Transmit output. Connect to CAN
transceiver on baseboard.
UART3 Ready To Send signal.
Ground. Connect to digital ground.
UART3 Clear To Send signal.
Connected to FM output of Murata module.
—
Analog input to FM on Murata module.
MMC1 Data bit 7.
3.3V or 1.8V
I/O (see Note 1) MMC1 Data bit 0.
3.3V or 1.8V
I/O (see Note 1) MMC2 Data bit 0.
3.3V or 1.8V
I/O (see Note 1) MMC1 Data bit 1.
3.3V or 1.8V
I/O (see Note 1) MMC2 Data bit 1.
3.3V or 1.8V
I/O (see Note 1) MMC1 Data bit 2.
3.3V or 1.8V
I/O (see Note 1) MMC2 Data bit 2.
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AM35x SOM-M2 Hardware Specification
J1 Pin# SOM Net Name
65
3.3V_or_1.8V
66
MMC2_D3
67
68
3.3V_or_1.8V
TOUCH_X1
69
70
MMC1_D3
TOUCH_X2
71
72
MMC1_D4
TOUCH_Y1
73
74
MMC1_D5
TOUCH_Y2
75
MMC1_CMD
76
MMC2_CMD
77
MMC1_CLK
78
79
80
MMC2_CLK
DGND
DGND
81
uP_USB1_DM
82
uP_USB0_DM
83
uP_USB1_DP
84
uP_USB0_DP
85
86
87
88
USB1_VBUS
uP_USB0_ID
USB0_VBUS
USB0_VBUS
89
90
UART2_CTS
5V_IN
91
92
UART2_RTS
5V_IN
PN 1014249 Rev A
Microprocessor
Name
I/O Voltage
Description
I/O Voltage Output from SOM. Do not use
3.3V or 1.8V this as a general purpose power source.
(see Note 1) Use this pin to power level shifters etc.
VDDSHV
O
MMC2_DAT3/MCS
PI3_CS0/GPIO_13
3.3V or 1.8V
5
I/O (see Note 1) MMC2 Data bit 3.
I/O Voltage Output from SOM. Do not use
3.3V or 1.8V this as a general purpose power source.
VDDSHV
O (see Note 1) Use this pin to power level shifters etc.
—
I 1.8V
Touch Left (X+) Input to TSC2004.
MMC1_DAT3/MCS
PI2_CS0/GPIO_12
3.3V or 1.8V
5
I/O (see Note 1) MMC1 Data bit 3.
—
I 1.8V
Touch Left (X-) Input to TSC2004.
MMC1_DAT4/GPI
3.3V or 1.8V
O_126
I/O (see Note 1) MMC1 Data bit 4.
—
I 1.8V
Touch Left (Y+) Input to TSC2004.
MMC1_DAT5/GPI
3.3V or 1.8V
O_127
I/O (see Note 1) MMC1 Data bit 5.
—
I 1.8V
Touch Left (Y-) Input to TSC2004.
MMC1_CMD/GPIO
3.3V or 1.8V
_121
I/O (see Note 1) MMC1 Command signal.
MMC2_CMD/MCS
PI3_SIMO/UART4
3.3V or 1.8V
_RTS/GPIO_131
I/O (see Note 1) MMC2 Command signal.
MMC1_CLK/GPIO
3.3V or 1.8V MMC1 Clock signal. This signal has a 47
_120
O (see Note 1) ohm series resistor on the SOM.
MMC2_CLK/MCSP
I3_CLK/UART4_C
3.3V or 1.8V MMC2 Clock signal. This signal has a 47
TS/GPIO_130
O (see Note 1) ohm series resistor on SOM.
—
I GND
Ground. Connect to digital ground.
—
I GND
Ground. Connect to digital ground.
USB1 Data Minus (see Note 4). Connects
-I/O (see Note 3) to USB3320 on the SOM.
USB0_DM/UART3
_RX_IRRX
I/O (see Note 3) USB0 Data Minus (see Note 4).
USB1 Data Plus (see Note 4). Connects to
-I/O (see Note 3) USB3320 on the SOM.
USB0_DP/UART3
_TX_IRTX
I/O (see Note 3) USB0 Data Plus (see Note 4).
USB1 VBus. This signal is used by the
USB3320 to determine when a device is
—
I 5V
connected/disconnected.
USB0_ID
I (see Note 3) USB0 ID signal.
USB0_VBUS
I 5V or GND
USB0 VBus.
USB0_VBUS
I 5V or GND
USB0 VBus.
UART2_CTS/MCB
SP3_DX/GPT9_P
3.3V or 1.8V
WM_EVT/GPIO_1
44
I (see Note 1) UART2 Clear To Send signal.
—
I 5V
Not used on SOM-M2. Do not connect.
UART2_RTS/MCB
SP3_DR/GPT10_P
3.3V or 1.8V
WM_EVT/GPIO_1
45
O (see Note 1) UART2 Ready To Send signal.
—
I 5V
Not used on SOM-M2. Do not connect.
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25
AM35x SOM-M2 Hardware Specification
93
94
UART2_TX
DGND
95
96
UART2_RX
5V_IN
Microprocessor
Name
UART2_TX/MCBS
P3_CLKX/GPT11_
PWM_EVT/GPIO_
146
VSS
UART2_RX/MCBS
P3_FSX/GPT8_P
WM_EVT/GPIO_1
47
—
97
98
UART3_TX
5V_IN
UART3_TX_IRTX
—
O
I
99
100
UART3_RX
DGND
UART3_RX_IRRX
VSS
I
I
J1 Pin# SOM Net Name
I/O Voltage
O
I
O
I
Description
3.3V or 1.8V
(see Note 1) UART2 Transmit signal.
GND
Ground. Connect to digital ground.
3.3V or 1.8V
(see Note 1)
5V
3.3V or 1.8V
(see Note 1)
5V
3.3V or 1.8V
(see Note 1)
GND
UART2 Receive signal.
Not used on SOM-M2. Do not connect.
UART3 Transmit signal.
Not used on SOM-M2. Do not connect.
UART3 Receive signal.
Ground. Connect to digital ground.
NOTE 1: Most AM3517 SOM-M2 I/O pins are dual-voltage capable; that is, the SOM I/O pins
may be configured to operate at 3.3V or 1.8V; however, all IO pins must be set to the same
voltage. The desired I/O voltage is set via J1.37. See Section 4.5.2 for more information.
NOTE 2: At startup, the boot mode is determined by sampling uP_SYS_BOOT [0:6]. Resistors on
the SOM pull these pins to a default value. User boards may select alternate boot modes by
pulling selected pins opposite their default value; to do this, the user board must use resistors of
much lower impedance than those used on the SOM. User boards must ensure that other circuits
do not drive or load down these pins at startup. Driving/loading these pins at startup may cause
the AM3517 microprocessor to latch an incorrect boot mode.
NOTE 3: USB voltage levels follow the USB specification and depend on the USB operating
speed. Please see the USB 2.0 Specification for more information.
NOTE 4: Route USB signals as 45 ohms single ended, 90 ohm differential.
6.2
J2 Connector 100-Pin Descriptions
J2 Pin# SOM Net Name
1
GPMC_D7
2
ENET_INTn
3
GPMC_D8
4
GPMC_WAIT1
5
GPMC_D9
6
GPMC_WAIT2
7
GPMC_D10
8
GPMC_NBE1
PN 1014249 Rev A
Microprocessor
Name
I/O Voltage
Description
3.3V or 1.8V
I/O (see Note 1) GPMC Bus Data Bit 7.
GPMC_D7
GPMC_NCS7/GP
MC_IO_DIR/0/GPT
3.3V or 1.8V Interrupt for Ethernet PHY (LAN9710). 4.7K
8_PWM_EVT/GPI
O_58
I (see Note 1) pull-up on SOM.
GPMC_D8/GPIO_
3.3V or 1.8V
44
I/O (see Note 1) GPMC Bus Data Bit 8.
GPMC_WAIT1/UA
3.3V or 1.8V
RT4_TX/GPIO_63
I (see Note 1) WAIT1 signal for GPMC interface.
GPMC_D9/GPIO_
3.3V or 1.8V
45
I/O (see Note 1) GPMC Bus Data Bit 9.
GPMC_WAIT2/UA
3.3V or 1.8V
RT4_RX/GPIO_64
I (see Note 1) WAIT2 signal for GPMC interface.
GPMC_D10/GPIO
3.3V or 1.8V
_46
I/O (see Note 1) GPMC Bus Data Bit 10.
GPMC_NBE1/GPI
3.3V or 1.8V
O_61
O (see Note 1) BYTE Enable 1 for GPMC Interface.
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AM35x SOM-M2 Hardware Specification
J2 Pin# SOM Net Name
9
GPMC_D11
10
GPMC_NBE0_CLE
11
GPMC_D12
12
GPMC_WEn
13
GPMC_D13
14
GPMC_OEn
15
GPMC_D14
16
GPMC_NADV_ALE
17
GPMC_D15
18
19
20
21
GPMC_CLK
DGND
DGND
RFU
22
GPMC_nCS5
23
GPMC_A1
24
RTCINTn
25
GPMC_A2
26
GPMC_nCS3
27
GPMC_A3
28
GPMC_nCS2
29
GPMC_A4
30
GPMC_nCS1
31
GPMC_A5
32
GPMC_nCS0
33
GPMC_A6
34
GPMC_D0
35
GPMC_A7
PN 1014249 Rev A
Microprocessor
Name
GPMC_D11/GPIO
_47
GPMC_NBE0_CL
E/GPIO_60
GPMC_D11/GPIO
_48
GPMC_NWE
GPMC_D11/GPIO
_49
GPMC_NOE
GPMC_D11/GPIO
_50
GPMC_NADV_AL
E
GPMC_D11/GPIO
_51
GPMC_CLK/GPIO
_59
VSS
VSS
—
GPMC_NCS5/SYS
_NDMAREQ2/0/G
PT10_PWM_EVT/
GPIO_56
GPMC_A1/GPIO_
34
GPMC_NCS4/SYS
_NDMAREQ1/GPT
9_PWM_EVT/GPI
O_55
GPMC_A2/GPIO_
35
GPMC_NCS3/SYS
_NDMAREQ0/GPT
10_PWM_EVT/GPI
O_54
GPMC_A3/GPIO_
36
GPMC_NCS2/GPT
9_PWM_EVT/GPI
O_53
GPMC_A4/GPIO_
37
GPMC_NCS1/GPI
O_52
GPMC_A5/GPIO_
38
GPMC_nCS0
GPMC_A6/GPIO_
39
GPMC_D0
GPMC_A7/GPIO_
40
I/O Voltage
3.3V or 1.8V
I/O (see Note 1)
3.3V or 1.8V
O (see Note 1)
3.3V or 1.8V
I/O (see Note 1)
3.3V or 1.8V
O (see Note 1)
3.3V or 1.8V
I/O (see Note 1)
3.3V or 1.8V
O (see Note 1)
3.3V or 1.8V
I/O (see Note 1)
3.3V or 1.8V
O (see Note 1)
3.3V or 1.8V
I/O (see Note 1)
3.3V or 1.8V
O (see Note 1)
I GND
I GND
NA NA
O
O
O
O
O
O
GPMC Bus Data Bit 11.
BYTE Enable 0 for GPMC Interface.
GPMC Bus Data Bit 12.
GPMC Bus Write Enable.
GPMC Bus Data Bit 13.
GPMC Bus Output Enable.
GPMC Bus Data Bit 14.
GPMC Bus Address Latch Enable.
GPMC Bus Data Bit 15.
GPMC Bus Clock.
Ground. Connect to digital ground.
Ground. Connect to digital ground.
Reserved for future use. Do not connect.
3.3V or 1.8V
(see Note 1) GPMC Bus Chip Select 5.
3.3V or 1.8V
(see Note 1) GPMC Bus Address Bit 1.
3.3V or 1.8V Active low. Real Time Clock Interrupt. This
(see Note 1) signal has a 4.7k pull-up.
3.3V or 1.8V
(see Note 1) GPMC Bus Address Bit 2.
3.3V or 1.8V
(see Note 1) GPMC Bus Chip Select 3.
3.3V or 1.8V
(see Note 1) GPMC Bus Address Bit 3.
3.3V or 1.8V
(see Note 1)
3.3V or 1.8V
O (see Note 1)
3.3V or 1.8V
O (see Note 1)
3.3V or 1.8V
O (see Note 1)
3.3V or 1.8V
O (see Note 1)
3.3V or 1.8V
O (see Note 1)
3.3V or 1.8V
I/O (see Note 1)
3.3V or 1.8V
O (see Note 1)
O
Description
GPMC Bus Chip Select 2.
GPMC Bus Address Bit 4.
GPMC Bus Chip Select 1.
GPMC Bus Address Bit 5.
GPMC Bus Chip Select 0.
GPMC Bus Address Bit 6.
GPMC Bus Data Bit 0.
GPMC Bus Address Bit 7.
Logic Product Development Company, All Rights Reserved
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AM35x SOM-M2 Hardware Specification
Microprocessor
Name
J2 Pin# SOM Net Name
36
GPMC_D1
37
GPMC_A8
38
GPMC_D2
39
GPMC_A9
40
GPMC_D3
41
GPMC_A10
GPMC_D3
GPMC_A10/SYS_
NDMAREQ3/GPIO
_43
42
43
GPMC_D4
RFU
GPMC_D4
—
I/O
NA
44
45
GPMC_D5
RFU
GPMC_D5
—
I/O
NA
46
47
48
GPMC_D6
DGND
DGND
GPMC_D6
VSS
VSS
I/O
I
I
49
MAIN_BATT_IN
—
I
max 6V
50
MAIN_BATT_IN
—
I
max 6V
51
MAIN_BATT_IN
—
I
max 6V
52
53
54
55
56
MAIN_BATT_IN
DGND
DGND
RFU
TV_OUT1
ETHER_LINK_ACT_L
EDn
TV_OUT2
—
VSS
VSS
—
TV_OUT1
I
I
I
NA
O
max 6V
GND
GND
NA
—
57
58
59
60
61
62
63
GPMC_D1
GPMC_A8/GPIO_
41
I/O Voltage
3.3V or 1.8V
I/O (see Note 1)
3.3V or 1.8V
O (see Note 1)
3.3V or 1.8V
I/O (see Note 1)
GPMC_D2
GPMC_A9/SYS_N
DMAREQ2/GPIO_
42
Description
GPMC Bus Data Bit 1.
GPMC Bus Address Bit 8.
GPMC Bus Data Bit 2.
3.3V or 1.8V
(see Note 1) GPMC Bus Address Bit 9.
3.3V or 1.8V
I/O (see Note 1) GPMC Bus Data Bit 3.
O
O
3.3V or 1.8V
(see Note 1)
3.3V or 1.8V
(see Note 1)
NA
3.3V or 1.8V
(see Note 1)
NA
3.3V or 1.8V
(see Note 1)
GND
GND
GPMC Bus Address Bit 10.
GPMC Bus Data Bit 4.
Reserved for future use. Do not connect.
GPMC Bus Data Bit 5.
Reserved for future use. Do not connect.
GPMC Bus Data Bit 6.
Ground. Connect to digital ground.
Ground. Connect to digital ground.
External power source input. This signal
should be driven directly by a single cell
lithium-ion battery or a fixed regulated
power source. See Sections 3.2 & 4.5.1.1.
External power source input. This signal
should be driven directly by a single cell
lithium-ion battery or a fixed regulated
power source. See Sections 3.2 & 4.5.1.1.
External power source input. This signal
should be driven directly by a single cell
lithium-ion battery or a fixed regulated
power source. See Sections 3.2 & 4.5.1.1..
External power source input. This signal
should be driven directly by a single cell
lithium-ion battery or a fixed regulated
power source. See Sections 3.2 & 4.5.1.1.
Ground. Connect to digital ground.
Ground. Connect to digital ground.
Reserved for future use. Do not connect.
Composite/Luma S-Video (See Note 4).
—
O —
Connect to anode of Ethernet Activity LED.
TV_OUT2
O
Chroma S-Video (See Note 4).
I2C3_SDA/GPIO_1
3.3V or 1.8V
uP_I2C3_SDA
85
I/O (see Note 1) I2C3 Serial Data.
I2C2_SDA/GPIO_1
3.3V or 1.8V
uP_I2C2_SDA
83
I/O (see Note 1) I2C2 Serial Data.
I2C3_SCL/GPIO_1
3.3V or 1.8V
uP_I2C3_SCL
84
O (see Note 1) I2C3 Serial Clock.
I2C2_SDA/GPIO_1
3.3V or 1.8V
uP_I2C2_SCL
68
O (see Note 1) I2C2 Serial Clock.
Connect to cathode of Ethernet Speed
ETHER_SPEED_LED —
O —
LED.
PN 1014249 Rev A
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28
AM35x SOM-M2 Hardware Specification
Microprocessor
Name
—
J2 Pin# SOM Net Name
64
VRTC_IN
65
3.3V_or_1.8V
66
uP_McBSP1_CLKR
VDDSHV
MCBSP1_CLKR/M
CSPI4_CLK/GPIO
_156
67
3.3V_or_1.8V
VDDSHV
68
69
uP_McBSP_CLKS
RFU
McBSP_CLKS
—
70
uP_MCBSP1_FSX
MCBSP1_FSX
71
ETHER_TX+
—
72
uP_MCBSP1_DR
MCBSP1_DR
73
ETHER_TX-
—
74
uP_MCBSP1_DX
MCBSP1_DX
75
ETHER_RX+
—
76
uP_MCBSP1_FSR
MCBSP1_FSR
77
ETHER_RX-
78
79
80
uP_MCBSP1_CLKX
DGND
DGND
81
uP_SPI1_CLK
82
uP_MCBSP2_CLKX
83
uP_SPI1_SOMI
84
uP_MCBSP2_FSX
85
uP_SPI1_SIMO
86
uP_MCBSP2_DX
87
uP_SPI1_SCSn0
88
uP_MCBSP2_DR
—
MCBSP1_CLKX/M
CBSP3_CLKX/GPI
O_162
—
—
MCSPI1_CLK/MM
C2_DAT4/GPIO_1
71
MCBSP2_CLKX/G
PIO_117
MCSPI1_SOMI/M
MC2_DAT6/GPIO_
173
MCBSP2_FSX/GPI
O_116
MCSPI1_SIMO/M
MC2_DAT5/GPIO_
172
MCBSP2_DX/GPI
O_119
MCSPI1_CS0/MM
C2_DAT7/GPIO_1
74
MCBSP2_DR/GPI
O_118
PN 1014249 Rev A
I/O Voltage
I 2V-5V
O
Description
Voltage for Real Time Clock on the SOM.
I/O Voltage Output from SOM. Do not use
3.3V or 1.8V this as a general purpose power source.
(see Note 1) Use this pin to power level shifters etc.
3.3V or 1.8V McBSP1 Receive Clock. This signal has a
(see Note 1) 22 ohm series resistor on the SOM.
I/O Voltage Output from SOM. Do not use
3.3V or 1.8V this as a general purpose power source.
O (see Note 1) Use this pin to power level shifters etc.
3.3V or 1.8V McBSP Shared Clock. This signal has a 22
O (see Note 1) ohm series resistor on the SOM.
NA NA
Reserved for future use. Do not connect.
3.3V or 1.8V
O (see Note 1) McBSP1 Transmit Frame Sync signal.
Ethernet Transmit plus (+). This signal has
a 49.9 ohm pull-up on the SOM. See Note
O —
2.
3.3V or 1.8V
I (see Note 1) McBSP1 Receive Data signal.
Ethernet Transmit minus (-). This signal
has a 49.9 ohm pull-up on the SOM. See
O —
Note 2.
3.3V or 1.8V
O (see Note 1) McBSP1 Transmit Data signal.
Ethernet Receive plus (+). This signal has
a 49.9 ohm pull-up on the SOM. See Note
I —
2
3.3V or 1.8V
I (see Note 1) McBSP1 Receive Frame Synch signal.
Ethernet Receive minus (-). This signal has
a 49.9 ohm pull-up on the SOM. See Note
I —
2.
O
O
I
I
O
O
I
O
O
O
O
I
3.3V or 1.8V
(see Note 1)
GND
GND
McBSP1 Transmit Clock. This signal has a
22 ohm series resistor on the SOM.
Ground. Connect to digital ground.
Ground. Connect to digital ground.
3.3V or 1.8V
(see Note 1)
3.3V or 1.8V
(see Note 1)
SPI1 clock signal. This signal has a 22 ohm
series resistor on the SOM.
McBSP2 Transmit Clock. This signal has a
22 ohm series resistor on the SOM.
3.3V or 1.8V
(see Note 1) SPI1 Slave Out, Master In signal.
3.3V or 1.8V
(see Note 1) McBSP2 Transmit Frame Sync signal.
3.3V or 1.8V
(see Note 1) SPI1 Slave In, Master Out signal.
3.3V or 1.8V
(see Note 1) McBSP2 Transmit Data signal.
3.3V or 1.8V
(see Note 1) Chip Select 0 for SPI1.
3.3V or 1.8V
(see Note 1) McBSP2 Receive Data.
Logic Product Development Company, All Rights Reserved
29
AM35x SOM-M2 Hardware Specification
Microprocessor
Name
MCSPI1_CS1/ADP
LLV2D_DITHERIN
G_EN2/MMC3_CM
D/GPIO_175
—
MCSPI1_CS2/MM
C3_CLK/GPIO_17
6
—
MCSPI1_CS3/HSU
SB2_TLL_DATA2/
HSUSB2_DATA2/
GPIO_177/MM_FS
USB2_TXDAT
—
—
MCSPI2_CLK/HSU
SB2_TLL_DATA7/
HSUSB2_DATA7/
GPIO_178
MCSPI2_CS1/GPT
8_PWM_EVT/HSU
SB2_TLL_DATA3/
HSUSB2_DATA3/
GPIO_182/MM_FS
USB2_TXEN_N
MCSPI2_SOMI/GP
T10_PWM_EVT/H
SUSB2_TLL_DAT
A5/HSUSB2_DAT
A5/GPIO_180
MCSPI2_CS0/GPT
11_PWM_EVT/HS
USB2_TLL_DATA
6/HSUSB2_DATA6
/GPIO_181
MCSPI2_SIMO/GP
T9_PWM_EVT/HS
USB2_TLL_DATA
4/HSUSB2_DATA4
/GPIO_179
J2 Pin# SOM Net Name
89
90
uP_SPI1_SCSn1
RFU
91
92
uP_SPI1_SCSn2
RFU
93
94
95
uP_SPI1_SCSn3
RFU
RFU
96
uP_SPI2_CLK
97
uP_SPI2_SCSn1
98
uP_SPI2_SOMI
99
uP_SPI2_SCSn0
100
uP_SPI2_SIMO
I/O Voltage
Description
3.3V or 1.8V
O (see Note 1) Chip Select 1 for SPI1.
NA NA
Reserved for future use. Do not connect.
3.3V or 1.8V Chip Select 2 for SPI1. This signal has a 47
O (see Note 1) ohm series resistor on the SOM.
NA NA
Reserved for future use. Do not connect.
3.3V or 1.8V
O (see Note 1) Chip Select 3 for SPI1.
NA NA
Reserved for future use. Do not connect.
NA NA
Reserved for future use. Do not connect.
O
3.3V or 1.8V SPI2 Clock signal. This signal has a 22
(see Note 1) ohm series resistor on the SOM.
O
3.3V or 1.8V
(see Note 1) Chip Select 1 for SPI2.
I
3.3V or 1.8V
(see Note 1) SPI2 Slave Out, Master In signal.
O
3.3V or 1.8V
(see Note 1) Chip Select 0 for SPI2.
O
3.3V or 1.8V
(see Note 1) SPI1 Slave In, Master Out signal.
NOTE 1: Most AM3517 SOM-M2 I/O pins are dual-voltage capable; that is, the SOM I/O pins
may be configured to operate at 3.3V or 1.8V; however, all IO pins must be set to the same
voltage. The desired I/O voltage is set via J1.37. See Section 4.5.2 for more information.
NOTE 2: Route Ethernet signals as 50 ohms single ended, 100 ohm differential.
6.3
J3 Connector 100-Pin Descriptions
J3 Pin# SOM Net Name
1
up_DSS_DOUT16
PN 1014249 Rev A
Microprocessor
Name
DSS_DATA16/GPI
O_86
I/O Voltage
Description
3.3V or 1.8V
O (see Note 1) DSS bus data bit 16.
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30
AM35x SOM-M2 Hardware Specification
Microprocessor
Name
J3 Pin# SOM Net Name
2
up_SYS_BOOT2
3
up_DSS_DOUT17
4
up_SYS_BOOT5
5
up_DSS_DOUT18
6
HDQ_SIO
7
8
up_DSS_DOUT19
PM_I2C_SCL
9
10
up_DSS_DOUT20
PM_I2C_SDA
11
up_DSS_DOUT21
12
up_SYS_BOOT0
13
14
up_DSS_DOUT22
RFU
15
up_DSS_DOUT23
16
17
SYS_CLKREQ
RFU
18
19
20
uP_OBSCLK
DGND
DGND
PN 1014249 Rev A
SYS_BOOT2/GPI
O_4
DSS_DATA17/GPI
O_87
I/O Voltage
I
O
Description
Boot Select 2. This signal may be used
as a GPIO after the boot process is
complete. This signal must not have a
load during boot so the boot sequence is
3.3V or 1.8V not disrupted. This signal has a 4.7k pull(see Note 1) up.
3.3V or 1.8V
(see Note 1) DSS bus data bit 17.
Boot Select 5. This signal may be used
as a GPIO after the boot process is
complete. This signal must not have a
load during boot so the boot sequence is
3.3V or 1.8V not disrupted. This signal has a 4.7k pull(see Note 1) down.
SYS_BOOT5/MMC
2_DIR_DAT3/GPI
O_7
I
DSS_DATA18/MC
3.3V or 1.8V
SPI3_CLK/DSS_D
ATA4/GPIO_88
O (see Note 1) DSS bus data bit 18.
HDQ_SIO/SYS_AL
TCLK/I2C2_SCCB
E/I2C3_SCCBE/G
3.3V or 1.8V
PIO_170
I/O (see Note 1) One wire interface signal.
DSS_DATA19/MC
3.3V or 1.8V
SPI3_SIMO/DSS_
DATA3/GPIO_89
O (see Note 1) DSS bus data bit 19.
NA
I —
Power measurement I2C clock signal.
DSS_DATA20/MC
SPI3_SOMI/DSS_
3.3V or 1.8V
DATA2/GPIO_90
O (see Note 1) DSS bus data bit 20.
NA
I/O —
Power measurement I2C data signal.
DSS_DATA21/MC
SPI3_CS0/DSS_D
3.3V or 1.8V
ATA1/GPIO_91
O (see Note 1) DSS bus data bit 21.
Boot Select 0. This signal may be used
as a GPIO after the boot process is
complete. This signal must not have a
load during boot so the boot sequence is
SYS_BOOT2/GPI
3.3V or 1.8V not disrupted. This signal has a 4.7k pullO_2
I (see Note 1) down.
DSS_DATA22/MC
3.3V or 1.8V
SPI3_CS1/DSS_D
ATA0/GPIO_92
O (see Note 1) DSS bus data bit 22.
—
NA N/A
Reserved for future use. Do not connect.
DSS_DATA23/DS
S_DATA5/GPIO_9
3.3V or 1.8V
O (see Note 1) DSS bus data bit 23.
3
Active high. SYS_CLKREQ is connected
to the enable of the 26MHz main clock
oscillator. This signal may be driven high
when the SOM is in sleep state to drive
SYS_CLKOUT1 (uP_OBSCLK) out
without waking the AM3517. Please see
SYS_CLKREQ/GP
3.3V or 1.8V TI’s AM35xx Reference Manual for more
IO_1
I (see Note 1) information.
—
NA NA
Reserved for future use. Do not connect.
SYS_CLKOUT1/G
3.3V or 1.8V AM35x output clock (26MHz). This signal
PIO_10
O (see Note 1) has a 22 ohm series resistor on the SOM.
VSS
I GND
Ground. Connect to digital ground.
VSS
I GND
Ground. Connect to digital ground.
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AM35x SOM-M2 Hardware Specification
J3 Pin# SOM Net Name
21
uP_McBSP4_CLKX
22
uP_McBSP3_CLKX
23
uP_McBSP4_DX
24
uP_McBSP3_DX
25
uP_McBSP4_DR
26
uP_McBSP3_DR
27
uP_McBSP4_FSX
28
29
uP_McBSP3_FSX
BUFF_DIS
30
31
CCDC_D0
RFU
32
33
CCDC_D1
RFU
34
35
36
37
CCDC_D2
WLAN_RS232_RX
RFU
WLAN_RS232_TX
38
39
MMC2_D4
UART_DBG
40
41
MMC2_D5
BT_DBG
42
43
MMC2_D6
RFU
44
45
MMC2_D7
RFU
PN 1014249 Rev A
Microprocessor
Name
MCBSP4_CLKX/G
PIO_152/MM_FSU
SB3_TXSE0
MCBSP3_CLKX/U
ART2_TX/GPIO_1
42/0
MCBSP4_DX/GPI
O_154/0/MM_FSU
SB3_TXDAT
MCBSP3_DX/UAR
T2_CTS/GPIO_14
0/0
MCBSP4_DR/GPI
O_153/0/MM_FSU
SB3_RXRCV
MCBSP3_DR/UAR
T2_RTS/GPIO_14
1/0
MCBSP4_FSX/GPI
O_155/0/MM_FSU
SB3_TXEN_N
MCBSP3_FSX/UA
RT2_RX/GPIO_14
3/0
—
CCDC_DATA0/I2C
3_SDA/GPIO_99
—
CCDC_DATA1/GP
IO_100
—
CCDC_DATA2/GP
IO_101/HW_DBG4
NA
—
NA
MMC2_DAT4/MM
C2_DIR_DAT0/MM
C3_DAT0/GPIO_1
36
—
MMC2_DAT5/MM
C2_DIR_DAT1/MM
C3_DAT1/GPIO_1
37/MM_FSUSB3_
RXDP
—
MMC2_DAT6/MM
C2_DIR_CMD/MM
C3_DAT2/GPIO_1
38/0
—
MMC2_DAT7/MM
C2_CLKIN/MMC3_
DAT3/GPIO_139/0
/MM_FSUSB3_RX
DM
—
I/O Voltage
Description
O
3.3V or 1.8V
(see Note 1) McBSP4 Transmit Clock signal.
O
3.3V or 1.8V
(see Note 1) McBSP3 Transmit Clock signal.
O
3.3V or 1.8V
(see Note 1) McBSP4 Transmit Data signal.
O
3.3V or 1.8V
(see Note 1) McBSP3 Transmit Data signal.
I
3.3V or 1.8V
(see Note 1) McBSP4 Receive Data signal.
I
3.3V or 1.8V
(see Note 1) McBSP3 Receive Data signal.
O
3.3V or 1.8V
(see Note 1) McBSP4 Transmit Sync signal.
3.3V or 1.8V
(see Note 1)
NA
3.3V or 1.8V
I (see Note 1)
NA NA
3.3V or 1.8V
I (see Note 1)
NA NA
3.3V or 1.8V
I (see Note 1)
I 1.8V
NA NA
O 1.8V
O
I
McBSP3 Transmit Sync signal.
Used for test only. Do not connect.
CCDC bus data bit 0.
Reserved for future use. Do not connect.
CCDC bus data bit 1.
Reserved for future use. Do not connect.
CCDC bus data bit 2.
Used for test only. Do not connect.
Reserved for future use. Do not connect.
Used for test only. Do not connect.
3.3V or 1.8V
I/O (see Note 1) MMC2 data bit 4.
O 1.8V
Used for test only. Do not connect.
3.3V or 1.8V
I/O (see Note 1) MMC2 data bit 5.
O 1.8V
Used for test only. Do not connect.
3.3V or 1.8V
I/O (see Note 1) MMC2 data bit 6.
NA NA
Reserved for future use. Do not connect.
3.3V or 1.8V
I/O (see Note 1) MMC2 data bit 7.
NA NA
Reserved for future use. Do not connect.
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32
AM35x SOM-M2 Hardware Specification
J3 Pin# SOM Net Name
Microprocessor
Name
46
NAND_SEL
—
I
47
48
49
50
51
USB1_CPEN
RFU
RFU
RFU
DGND
NA
—
—
—
—
O
NA
NA
NA
I
52
53
uP_RESWARMn
RFU
SYS_NRESWARM
3.3V or 1.8V
I/O (see Note 1)
/GPIO_30
—
NA NA
54
55
56
57
58
59
RESOUTn
RFU
RFU
RFU
RFU
RFU
NA
—
—
—
—
—
60
61
uP_I2C1_SCL
RFU
I2C1_SCL
—
62
uP_I2C1_SDA
63
64
ETK_D15
RSRV01
65
66
3.3V_or_1.8V
RSRV02
67
68
3.3V_or_1.8V
RSRV10
69
ETK_D14
I2C1_SDA
ETK_D15/HSUSB2
_DATA1/GPIO_29/
MM_FSUSB2_TXS
E0/HSUSB2_TLL_
3.3V or 1.8V
DATA1/HW_DBG1
7
I/O (see Note 1) ETK bus data bit 15.
—
NA NA
Reserved for future use. Do not connect.
I/O Voltage Output from SOM. Do not use
3.3V or 1.8V this as a general purpose power source.
VDDSHV
O (see Note 1) Use this pin to power level shifters etc.
—
NA NA
Reserved for future use. Do not connect.
I/O Voltage Output from SOM. Do not use
3.3V or 1.8V this as a general purpose power source.
VDDSHV
O (see Note 1) Use this pin to power level shifters etc.
—
NA NA
Reserved for future use. Do not connect.
ETK_D14/HSUSB2
_DATA0/GPIO_28/
MM_FSUSB2_RX
RCV/HSUSB2_TL
3.3V or 1.8V
L_DATA0/HW_DB
G16
I/O (see Note 1) ETK bus data bit 14.
PN 1014249 Rev A
I/O Voltage
3.3V or 1.8V
(See Note 1)
3.3V
NA
NA
NA
GND
Description
Select line to choose between
GPMC_nCS0 and GPMC_nCS2 for
NAND. NAND_SEL high (default) will
send GPMC_nCS0 to NAND; NAND_SEL
low will send GPMC_nCS2 to NAND.
Please refer to the Application Board
schematics for an example of external
chip select usage.
External VBUS power supply control for
USB1. Please see the SMSC USB3320
Datasheet for more information.
Reserved for future use. Do not connect.
Reserved for future use. Do not connect.
Reserved for future use. Do not connect.
Ground. Connect to digital ground.
Active low. Reset output from the
AM3517 microprocessor. This signal is
open collector only. There should be no
pull-ups on this line. Use RESOUTn to
drive external device reset lines.
Reserved for future use. Do not connect.
Active low. Buffered reset output from the
AM3517 microprocessor that drives all
onboard reset inputs. This signal should
be used to drive reset inputs on external
chips that require similar timing to the
onboard devices.
Reserved for future use. Do not connect.
Reserved for future use. Do not connect.
Reserved for future use. Do not connect.
Reserved for future use. Do not connect.
Reserved for future use. Do not connect.
3.3V or 1.8V
(see Note 1)
NA
NA
NA
NA
NA
3.3V or 1.8V
O (see Note 1) I2C1 clock signal.
NA NA
Reserved for future use. Do not connect.
3.3V or 1.8V
I/O (see Note 1) I2C1 data signal.
O
NA
NA
NA
NA
NA
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33
AM35x SOM-M2 Hardware Specification
71
72
ETK_D13
RSRV12
73
74
ETK_D12
RSRV13
75
76
uP_HSUSB1_CLK
RSRV14
77
78
79
80
uP_HSUSB1_STP
RSRV15
DGND
DGND
81
ETK_D11
Microprocessor
Name
—
ETK_D13/HSUSB2
_NXT/GPIO_27/M
M_FSUSB2_RXD
M/HSUSB2_TLL_
NXT/HW_DBG15
—
ETK_D12/HSUSB2
_DIR/GPIO_26/HS
USB2_TLL_DIR/H
W_DBG14
—
ETK_CTL/MMC3_
CMD/HSUSB1_CL
K/GPIO_13/MM_F
SUSB1_RXDP/HS
USB1_TLL_CLK/H
W_DBG1
—
ETK_CLK/MCBSP
5_CLKX/MMC3_C
LK/HSUSB1_STP/
GPIO_12/HSUSB1
_TLL_STP/HW_D
BG0
—
—
—
ETK_D11/MCSPI3
_CLK/HSUSB2_ST
P/GPIO_25/MM_F
SUSB2_RXDP/HS
USB2_TLL_STP/H
W_DBG13
82
uP_TCK
TCK
83
ETK_D10
—
84
uP_RTCK
85
uP_HSUSB1_NXT
RTCK/ GP8[0]
ETK_D9/SYS_SE
CURE_INDICATO
R/MMC3_DAT5/H
SUSB1_NXT/GPIO
_23/MM_FSUSB1_
RXDM/HSUSB1_T
LL_NXT/HW_DBG
11
86
uP_EMU1
87
uP_HSUSB1_DIR
J3 Pin# SOM Net Name
70
RSRV11
PN 1014249 Rev A
EMU1
ETK_D8/SYS_DR
M_MSECURE/MM
C3_DAT6/HSUSB
1_DIR/GPIO_22/H
SUSB1_TLL_DIR/
HW_DBG10
I/O Voltage
NA NA
Description
Reserved for future use. Do not connect.
3.3V or 1.8V
I/O (see Note 1) ETK bus data bit 13.
NA NA
Reserved for future use. Do not connect.
3.3V or 1.8V
I/O (see Note 1) ETK bus data bit 12.
NA NA
Reserved for future use. Do not connect.
3.3V or 1.8V
O (see Note 1) Not connected on the SOM (R1 absent).
NA NA
Reserved for future use. Do not connect.
O
NA
I
I
3.3V or 1.8V
(see Note 1)
NA
GND
GND
3.3V or 1.8V
I/O (see Note 1)
3.3V or 1.8V
I (see Note 1)
3.3V or 1.8V
I/O (see Note 1)
3.3V or 1.8V
O (see Note 1)
High speed USB1 bus STOP signal.
Reserved for future use. Do not connect.
Ground. Connect to digital ground.
Ground. Connect to digital ground.
ETK bus data bit 11.
JTAG TCK signal.
ETK bus data bit 10.
JTAG RTCK signal.
I
3.3V or 1.8V
(see Note 1) High speed USB1 bus NEXT signal.
uP_EMU1 is part of the JTAG interface.
Please reference TI’s AM35xx Reference
3.3V or 1.8V Manual for more information. This signal
(see Note 1) has a 4.7k pull-up on the SOM.
O
3.3V or 1.8V
(see Note 1) High speed USB1 bus direction.
O
Logic Product Development Company, All Rights Reserved
34
AM35x SOM-M2 Hardware Specification
J3 Pin# SOM Net Name
88
uP_EMU0
89
uP_HSUSB1_D3
90
uP_TDO
91
uP_HSUSB1_D6
92
uP_TDI
93
uP_HSUSB1_D5
94
uP_TMS
95
uP_HSUSB1_D4
96
uP_TRSTn
97
uP_HSUSB1_D7
98
uP_HSUSB1_D0
99
uP_HSUSB1_D2
PN 1014249 Rev A
Microprocessor
Name
I/O Voltage
Description
uP_EMU0 is part of the JTAG interface.
Please reference TI’s AM35xx Reference
3.3V or 1.8V Manual for more information. This signal
(see Note 1) has a 4.7k pull-up on the SOM.
EMU0
I
ETK_D3/MCSPI3_
CLK/MMC3_DAT3/
HSUSB1_DATA7/
GPIO_17/HSUSB1
3.3V or 1.8V
_TLL_DATA7/HW_
I/O (see Note 1)
DBG5
3.3V or 1.8V
TDO
O (see Note 1)
ETK_D6/MCBSP5
_DX/MMC3_DAT2/
HSUSB1_DATA6/
GPIO_20/HSUSB1
3.3V or 1.8V
_TLL_DATA6/HW_
I/O (see Note 1)
DBG8
3.3V or 1.8V
TDI
I (see Note 1)
ETK_D5/MCBSP5
_FSX/MMC3_DAT
1/HSUSB1_DATA5
/GPIO_19/HSUSB
3.3V or 1.8V
1_TLL_DATA5/HW
I/O (see Note 1)
_DBG7
3.3V or 1.8V
TMS
I (see Note 1)
ETK_D4/MCBSP5
_DR/MMC3_DAT0/
HSUSB1_DATA4/
GPIO_18/HSUSB1
3.3V or 1.8V
_TLL_DATA4/HW_
I/O (see Note 1)
DBG6
3.3V or 1.8V
TRST
I (see Note 1)
ETK_D3/MCSPI3_
CLK/MMC3_DAT3/
HSUSB1_DATA7/
GPIO_17/HSUSB1
3.3V or 1.8V
_TLL_DATA7/HW_
I/O (see Note 1)
DBG5
ETK_D0/MCSPI3_
SIMO/MMC3_DAT
4/HSUSB1_DATA0
/GPIO_14/MM_FS
USB1_RXRCV/HS
3.3V or 1.8V
USB1_TLL_DATA
I/O (see Note 1)
0/HW_DBG2
ETK_D2/MCSPI3_
CS0/HSUSB1_DA
TA2/GPIO_16/MM
_FSUSB1_TXDAT/
3.3V or 1.8V
HSUSB1_TLL_DA
I/O (see Note 1)
TA2/HW_DBG4
High speed USB1 bus data bit 3.
JTAG TDO signal.
High speed USB1 bus data bit 6.
JTAG TDI signal.
High speed USB1 bus data bit 5.
JTAG TMS signal.
High speed USB1 bus data bit 4.
JTAG TRSTn signal.
High speed USB1 bus data bit 7.
High speed USB1 bus data bit 0.
High speed USB1 bus data bit 2.
Logic Product Development Company, All Rights Reserved
35
AM35x SOM-M2 Hardware Specification
J3 Pin# SOM Net Name
100
uP_HSUSB1_D1
Microprocessor
Name
I/O Voltage
Description
ETK_D1/MCSPI3_
SOMI/HSUSB1_D
ATA1/GPIO_15/M
M_FSUSB1_TXSE
3.3V or 1.8V
0/HSUSB1_TLL_D
I/O (see Note 1) High speed USB1 bus data bit 1.
ATA1/HW_DBG3
NOTE 1: Most AM3517 SOM-M2 I/O pins are dual-voltage capable; that is, the SOM I/O pins
may be configured to operate at 3.3V or 1.8V; however, all IO pins must be set to the same
voltage. The desired I/O voltage is set via J1.37. See Section 4.5.2 for more information.
PN 1014249 Rev A
Logic Product Development Company, All Rights Reserved
36
8
7
6
4
5
1
2
3
REV.
A
Appendix A: AM35x SOM-M2 Mechanical Drawing (with Wireless)
REVISIONS
DESCRIPTION
INITIAL ENGINEERING RELEASE
ECO NUMBER
C029634
DATE
07.21.10
51.2 (REF)
F
F
NOTES:
36.1
40.9 (REF)
E
1
DO NOT PLACE ANY COMPONENTS WITHIN
LAYOUT AREA OF SOM
2
BASEBOARD CONNECTOR SPECIFICATION:
HIROSE DF40C-100DS-0.4V
3
MACHINE PLACEMENT OF J1,J2, AND J3
IS HIGHLY RECOMMENDED
4
ALL ALIGNED COMPONENTS TO BE WITHIN .075
5.
DO NOT SCALE DRAWING
E
J4
1.9
D
2x R1.2
TOP
D
2.7 (MAX)
0
1.6
2.7
C
C
B
B
THIS DRAWING PREPARED
IN ACCORDANCE WITH
ASME Y14.5-2000
ALL DIMENSIONS
ARE IN MILLIMETERS
UNLESS OTHERWISE
SPECIFIED
TOLERANCES UNLESS
OTHERWISE SPECIFIED
X
± 0.5
X.X
± 0.2
X.XX ± 0.1
X°
± 1°
BOTTOM
A
THIRD ANGLE PROJECTION
ENG
5
4
REV
07.21.10
C
AM35X SOM-M2
WITH WIRELESS
07.21.10
A
SCALE
DWG NO
SHEET
3:1
1016392
1 OF 2
PMH
MANF
6
TITLE
KAG
MGR
7
SIZE
07.21.10
CHECK
8
DATE
NWR
DATE
DATE
DATE
3
2
1
A
8
7
6
4
5
1
2
3
F
F
E
E
D
D
BOTTOM
40.7
35.560 .075
30.988 .075
0
10.5
TOP
PIN LOCATIONS
ISOMETRIC VIEWS
FOR REFERENCE ONLY
13.9
C
1
2
1
1
4
B
1
C
2
3
J1
0
2
J3
99 100
J2
99 100
2
2
B
99 100
2
27
RECOMMENDED BASEBOARD FOOTPRINT
A
A
8
7
6
5
4
3
2
SIZE
TITLE
REV
A
C
AM35X SOM-M2
WITH WIRELESS
SCALE
DWG NO
SHEET
3:1
1016392
2 OF 2
1
8
7
6
4
5
1
2
3
Appendix B: AM35x SOM-M2 Mechanical Drawing (without Wireless)
REV.
A
ECO NUMBER
C06984
REVISIONS
DESCRIPTION
INITIAL ENGINEERING RELEASE
DATE
10.30.09
B
C029634
UPDATED PIN LOCATIONS ON BASEBOARD FOOTPRINT
07.21.10
51.2 (REF)
F
F
NOTES:
36.1
40.9 (REF)
E
1
DO NOT PLACE ANY COMPONENTS WITHIN
LAYOUT AREA OF SOM
2
BASEBOARD CONNECTOR SPECIFICATION:
HIROSE DF40C-100DS-0.4V
3
MACHINE PLACEMENT OF J1,J2, AND J3
IS HIGHLY RECOMMENDED
4
ALL ALIGNED COMPONENTS TO BE WITHIN .075
5.
DO NOT SCALE DRAWING
E
J4
1.9
D
2x R1.2
TOP
D
1.7 (MAX)
0
1.6
2.7
C
C
B
B
THIS DRAWING PREPARED
IN ACCORDANCE WITH
ASME Y14.5-2000
ALL DIMENSIONS
ARE IN MILLIMETERS
UNLESS OTHERWISE
SPECIFIED
TOLERANCES UNLESS
OTHERWISE SPECIFIED
X
± 0.5
X.X
± 0.2
X.XX ± 0.1
X°
± 1°
BOTTOM
A
THIRD ANGLE PROJECTION
ENG
5
4
REV
10.30.09
C
AM35X SOM-M2
10.30.09
B
SCALE
DWG NO
SHEET
3:1
1014529
1 OF 2
PMH
MANF
6
TITLE
KAG
MGR
7
SIZE
10.30.09
CHECK
8
DATE
MHC
DATE
DATE
DATE
3
2
1
A
8
7
6
4
5
1
2
3
F
F
E
E
D
D
BOTTOM
40.7
35.560 .075
30.988 .075
0
10.5
TOP
PIN LOCATIONS
ISOMETRIC VIEWS
FOR REFERENCE ONLY
13.9
C
1
2
1
1
4
B
1
C
2
3
J1
0
2
J3
99 100
J2
99 100
2
2
B
99 100
2
27
RECOMMENDED BASEBOARD FOOTPRINT
A
A
8
7
6
5
4
3
2
SIZE
TITLE
REV
B
C
AM35X SOM-M2
SCALE
DWG NO
SHEET
3:1
1014529
2 OF 2
1
Appendix C: Example Retention Methods
REV.
A
ECO NUMBER
-
REVISIONS
DESCRIPTION
INITIAL RELEASE
DATE
02.12.10
NOTES:
1. BASED ON TESTING A LIMITED NUMBER OF SAMPLES, THE AM3517 SOM-M2
REQUIRES 10 LBS OF EXTRACTION FORCE AFTER ONE INSERTION CYCLE.
AFTER 30 INSERTION AND EXTRACTION CYCLES, THIS IS REDUCED TO 7 LBS.
THIS INFORMATION IS PROVIDED FOR REFERENCE ONLY.
THIS DRAWING PREPARED
IN ACCORDANCE WITH
ASME Y14.5-2000
ALL DIMENSIONS
ARE IN MILLIMETERS
UNLESS OTHERWISE
SPECIFIED
TOLERANCES UNLESS
OTHERWISE SPECIFIED
X
± 0.5
X.X ± 0.2
X.XX ± 0.1
X°
± 1°
THIRD ANGLE PROJECTION
ENG
DATE
NWR
02.04.10
CHECK
DATE
KAG
02.04.10
MGR
DATE
PMH
02.12.10
MANF
DATE
SIZE
TITLE
REV
A
AM3517 SOM-M2
Retention System- None
A
SCALE
DWG NO
SHEET
1015273
1 OF 1
REV.
ECO NUMBER
A
-
REVISIONS
DESCRIPTION
DATE
INITIAL RELEASE
02.12.10
NOTES:
1. THIS IS AN EXAMPLE RETENTION METHOD USING A CLIP.
THIS DRAWING PREPARED
IN ACCORDANCE WITH
ASME Y14.5-2000
ALL DIMENSIONS
ARE IN MILLIMETERS
SPECIFIED
TOLERANCES UNLESS
OTHERWISE SPECIFIED
X
± 0.5
X.X ± 0.2
X.XX ± 0.1
X°
± 1°
THIRD ANGLE PROJECTION
ENG
DATE
NWR
02.04.10
CHECK
DATE
KAG
02.04.10
MGR
DATE
PMH
02.12.10
MANF
DATE
SIZE
TITLE
REV
A
AM3517 SOM-M2
Retention System - Clip
A
SCALE
DWG NO
SHEET
1015274
1 OF 1
REV.
ECO NUMBER
A
-
REVISIONS
DESCRIPTION
DATE
INITIAL RELEASE
02.12.10
NOTES:
1. THE AM3517 SOM-M2 CAN BE RETAINED IN PLACE BY THE SURROUNDING ENCLOSURE.
2. REPRESENTATIVE ENCLOSURE
2
THIS DRAWING PREPARED
IN ACCORDANCE WITH
ASME Y14.5-2000
ALL DIMENSIONS
ARE IN MILLIMETERS
UNLESS OTHERWISE
SPECIFIED
TOLERANCES UNLESS
OTHERWISE SPECIFIED
X
± 0.5
X.X ± 0.2
X.XX ± 0.1
X°
± 1°
THIRD ANGLE PROJECTION
ENG
DATE
NWR
02.04.10
CHECK
DATE
KAG
02.04.10
MGR
DATE
PMH
02.12.10
MANF
DATE
SIZE
TITLE
REV
A
AM3517 SOM-M2 Retention
System - Housing
A
SCALE
DWG NO
SHEET
1015275
1 OF 1
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