NJU8725V-TE1

NJU8725 PRELIMINARY CLASS D AMPLIFIER FOR DIGITAL AUDIO ! GENERAL DESCRIPTION ! PACKAGE OUTLINE The NJU8725 is an 800mW-output class D th Amplifier featuring 6 ∆Σ modulation. It includes Digital Attenuator, Mute, and De-emphasis circuits. It converts digital source input to PWM signal output which is converted to analog signal with simple external LC low-pass filter. The NJU8725 realizes very high power-efficiency by class D operation. Therefore, it is suitable for battery-powered applications and others. NJU8725V ! FEATURES # # # # # # # # # # # # # Stereo BTL Power Amplifier Sixth-order 32fS Over Sampling ∆Σ & PWM Internal 8fS Over Sampling Digital Filter Sampling Frequency : 96kHz (Max.) De-Emphasis : 32kHz, 44.1kHz, 48kHz System Clock : 256fS Digital Processing : Attenuator 107step, LOG Curve : Mute Digital Audio Interface : 16bit, 18bit 2 : I S, LSB Justified, MSB Justified Short Circuit Protection Operating Voltage : 2.4 to 3.6V Driving Voltage : VDD to 5.25V C-MOS Technology Package Outline : SSOP24 / QFN28 NJU8725KN1 1 2 3 MUTE VDDL OUTLP VSSL OUTLN VDDL MODE RST VSS 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SSOP24 Ver.2004-04-26 F0/DATA F1/REQ F2/SCK DIN VDDR OUTRP VSSR OUTRN VDDR LRCK BCK MCK 28 1 MUTE VDDL OUTLP VSSL VSSL OUTLN VDDL DIN VDDR OUTRP VSSR VSSR OUTRN VDDR MODE RST VSS MCK BCK LRCK NC VDD STBY TEST TEST STBY VDD F0/DATA F1/REQ F2/SCK NC ! PIN CONFIGURATION QFN28 -1- NJU8725 ! BLOCK DIAGRAM VDD VSS Short Circuit Protection Power On Reset Circuit VDDL RST Synchronization Circuit OUTLP VSSL VDDL MCK LRCK BCK DIN MUTE STBY MODE F0/DATA F1/REQ F2/SCK -2- Serial Audio Data Interface 8fS Over Sampling Digital Filter th 32fS 6 ∆Σ & PWM OUTLN VSSL VDDR OUTRP System Control VSSR VDDR OUTRN VSSR Ver.2004-04-26 NJU8725 ! TERMINAL DESCRIPTION No. SSOP24 QFN28 1 26 SYMBOL I/O FUNCTION VDD − Logic Power Supply, VDD=3.3V Standby Control Terminal Low : Standby ON High : Standby OFF Manufacturer Testing Terminal Normally connect to GND. Mute Control Terminal Low : Mute ON High : Mute OFF Lch Power Supply, VDDL=VDD to 5.0V Lch Positive Output Terminal Lch Power GND, VSSL=0V Lch Negative Output Terminal Lch Power Supply, VDDL=VDD to 5.0V Control Mode selection Terminal Low : Parallel Control Mode High : Serial Control Mode Reset Terminal Low : Reset ON High : Reset OFF Logic Power GND, VSS=0V Master Clock Input Terminal 256fS clock inputs this terminal. Serial Audio Data Bit Clock Input Terminal This clock must synchronize with MCK input signal. L/R Channel Clock Input Terminal This clock must synchronize with MCK input signal. Rch Power Supply, VDDR=VDD to 5.0V Rch Negative Output Terminal Rch Power GND, VSSR=0V Rch Positive Output Terminal Rch Power Supply, VDDR=VDD to 5.0V Serial Audio Data Input Terminal MODE=”Low” : Serial Audio Interface Format Selection Terminal 2 MODE=”High” : Control Register Data Shift Clock Input Terminal The data is fetched into the control register by rise edge of SCK signal. MODE=”Low” : Serial Audio Interface Format Selection Terminal 1 MODE=”High” : Control Register Data Request Input Terminal MODE=”Low” : Serial Audio Interface Format Selection Terminal 0 MODE=”High” : Control Register Data Input Terminal Non connection 2 27 STBY I 3 28 TEST I 4 1 MUTE I 5 6 7 8 9 2 3 4,5 6 7 VDDL OUTLP VSSL OUTLN VDDL − O − O − 10 8 MODE I 11 9 RST I 12 10 VSS − 13 11 MCK I 14 12 BCK I 15 13 LRCK I 16 17 18 19 20 21 15 16 17,18 19 20 21 VDDR OUTRN VSSR OUTRP VDDR DIN − O − O − I 22 23 F2/SCK I 23 24 F1/REQ I 24 25 F0/DATA I − 14,22 NC − ! INPUT TERMINAL STRUCTURE VDD Input Terminal Inside Circuit VSS Ver.2004-04-26 -3- NJU8725 ! FUNCTIONAL DESCRIPTION (1) Signal Output PWM signals of L channel and R output from OUTLP/LN and OUTRP/RN terminals respectively. These signals are converted to analog signal by external 2nd-order or over LC filter. The output driver power supplied from VDDL, VDDR, VSSL, and VSSR are required high response power supply against voltage fluctuation like as switching regulator because Output THD is effected by power supply stability. (2) Master Clock Master Clock is 256fS clock into MCK terminal for the internal circuit operation clock. (3) Reset “L” level input over than 3ms to the RST terminal is initialization signal to initialize the internal circuit. This initialization signal is synchronized with internal clock and executes logical OR with the internal power on reset signal. This Reset signal initializes the internal function setting registers also. During initialization, the output terminals are high-impedance. over than 3ms RST Output Status Audio about 350ms 1024/fs BPZ Unmute Hi-Z Hi-Z : high-impedance Audio BPZ : Charge of bipolar zero Figure 1. Reset Timing (4) 8fS Over Sampling Digital Filter 8fS Over Sampling Digital Filter interpolates Audio data and decreases aliasing noise. It realizes Attenuation and De-Emphasis function by serial function control. th (5) 32fS 6 ∆Σ & PWM th 32fS 6 ∆Σ & PWM convert from Audio data of the 8fS Over Sampling Digital Filter to the 32fS one bit PWM data. (6) Short Circuit Protection Short Circuit Protection protects IC with output terminal of high-impedance condition when output terminal is shorted to GND or other output terminal. The high-impedance condition is released automatically with master clock input, not released without master clock input. -4- Ver.2004-04-26 NJU8725 (7) System Control (7-1) Standby Standby functions by “L” level input to the STBY terminal. In busy of Standby, conditions of digital audio format set, attenuation level, de-emphasis, and attenuator operation time are kept and output terminals are high-impedance. (7-2) Control Mode Set A control mode as shown below is selected by the MODE terminal. MODE 0 1 Parallel Serial Control Method Parallel Serial Function Digital Audio interface Format Set Control Register serial data input Terminals F0, F1, F2 DATA, REQ, SCK : Digital Audio Interface Format is set directly by using F0, F1, and F2 terminals. : NJU8725 is controlled serial input data by 3-wire serial interface using DATA, REQ, and SCK terminals By this setting, the function of F0/DATA, F1/REQ, and F2/SCK are changed. Refer to  (8-5)F0,F1,F2  about function of F0, F1, and F2 terminals. Refer to  (8)Control Register  about function of DATA, REQ, and SCK terminals. (7-3) Mute Mute functions by “L” signal into the MUTE terminal. In busy of mute, a current attenuation value becomes -∞ by internal digital attenuator. And MUTE is stopped by “H” signal into the MUTE terminal, the attenuation value returns from -∞ to previous value. MUTE 0 1 Attenuation Level -∞ Set Value MUTE MCK 1024/fS 1024/fS Attenuation Value Set Value Set Value -∞ -∞ Figure 2. Mute Timing Ver.2004-04-26 -5- NJU8725 (8) Serial Audio Data Interface (8-1) Input Data Format Selection 2 The digital audio interface format is selected out of I S, MSB Justified or LSB Justified, and 16 bits or 18 bits data length. (8-2) Input Timing Digital audio signal data into DIN terminal is fetched into the internal shift register by BCK signal rising edge. The fetched data in the shift register are transferred by rising edge or falling edge of LRCK as shown below: Data Format 2 IS MSB Justified LSB Justified Rising Edge Lch Input Register Rch Input Register Rch Input Register Falling Edge Rch Input Register Lch Input Register Lch Input Register BCK and LRCK must be synchronized with MCK. Left Channel LRCK Right Channel BCK DIN 15 14 13 1 15 14 13 0 1 0 2 Figure 3.1. 16 bits I S Data Format Right Channel LRCK Left Channel BCK DIN 15 14 13 15 14 13 1 0 1 15 0 Figure 3.2. 16 bits MSB Justified Data Format Right Channel LRCK Left Channel BCK DIN 0 15 14 3 2 1 0 15 14 3 2 1 0 Figure 3.3. 16 bits LSB Justified Data Format -6- Ver.2004-04-26 NJU8725 Left Channel LRCK Right Channel BCK DIN 17 16 15 1 17 16 15 0 1 0 2 Figure 3.4. 18 bits I S Data Format Right Channel LRCK Left Channel BCK DIN 17 16 15 1 17 16 15 0 1 0 17 Figure 3.5. 18 bits MSB Justified Data Format Right Channel LRCK Left Channel BCK DIN 0 17 16 3 2 1 0 17 16 3 2 1 0 Figure 3.6. 18 bits LSB Justified Data Format (8-3) Failure of Synchronization Operation If the MCK clock fluctuates over than ±10 clocks against the LRCK and failure of synchronization is detected the attenuation value is set to -∞. When the LRCK synchronizes with MCK again, the attenuation value returns from -∞ to previous level. Internal Condition Out of Sync. Normal Operation Normal Operation Set Value Set Value Attenuation Value -∞ Figure 4. Out of Synchronization Operation Ver.2004-04-26 1024/fS -7- NJU8725 (9) Control Register When Control Mode is set to Serial control by the Mode terminal, the control register sets various modes. The Control Data is fetched by the rising edge of F2/SCK and is set into the control register by the rising edge of F1/REQ. The latest 8 bits data are valid before the F1/REQ rising pulse. F1/REQ F2/SCK F0/DATA B7 B5 B6 B4 B2 B3 B1 B0 Figure 5. Control Register Timing (9-1) Serial Data Format B7 B6 B5 B4 0 ATTN6 ATTN5 ATTN4 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Do not set other data excepting this table. B3 ATTN3 0 F2 0 0 0 0 0 B2 ATTN2 0 F1 0 0 0 MUTT2 0 B1 ATTN1 DEMP1 F0 0 0 0 MUTT1 0 B0 ATTN0 DEMP0 MUTE RST TEST 0 MUTT0 TRST (9-2) ATTN6 to ATTN0 When B7 is “0”, B0 to B6 set the attenuation data. When attenuation data is set, the attenuation value is changed to the target value in the period of transition time set by MUTT0 to MUTT2. The attenuation value (ATT) is fixed by following formula. When ATT is 14h or less, the attenuator is set -∞ at reset. (When Control Mode is Parallel Control, ATT is fixed 0db.) ATT=DATA -121[dB] DATA : attenuation point 7Fh=6 dB 7Eh=5dB 7Dh=4dB : 79h=0dB : 16h=-99dB 15h=-100dB 14h=-∞ 13h=-∞ : 00h=-∞ (initial value) -8- Ver.2004-04-26 NJU8725 (9-3) DEMP0, DEMP1 DEMP0 and DEMP1 control De-Emphasis on/off and sampling frequency. DEMP1 DEMP0 De-Emphasis Initial Value ! 0 0 OFF 0 1 32kHz 1 0 44.1kHz 1 1 48kHz (9-4) MUTE Mute operation is controlled by the “MUTE” as same as the MUTE terminal control. MUTE Mute Operation Initial Value ! 0 OFF 1 ON (9-5) F0, F1, F2 F0, F1, and F2 select Digital Audio Interface Format. As same as the F0/DATA, F1/REQ, and F2/SCK terminal control. F0 F1 F2 Interface Format Bit Length Initial Value 2 ! 0 0 0 IS 16 0 0 1 MSB Justified 16 0 1 0 LSB Justified 16 2 1 0 0 IS 18 1 0 1 MSB Justified 18 1 1 0 LSB Justified 18 (9-6) RST When the RST is “1”, the control register and inner data (Digital filter, PWM modulator) are initialized. RST Reset Operation Initial Value ! 0 OFF 1 ON (9-7) TRST When the TRST is “1”, only inner data (Digital filter, PWM modulator) is initialized. TRST Data Bus Initialize Initial Value ! 0 OFF 1 ON (9-8) MUTT2 to MUTT0 MUTT2 to MUTT0 set the attenuator transition time. This transition time is one attenuation step change time. MUTT2 MUTT1 MUTT0 Operation Time Initial Value ! 0 0 0 1 / fS 0 0 1 2 / fS 0 1 0 4 / fS 0 1 1 8 / fS 1 0 0 16 / fS 1 0 1 32 / fS 1 1 0 64 / fS 1 1 1 128 / fS Ver.2004-04-26 -9- NJU8725 ! ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL VDD VDDL VDDR Vin Topr Tstg RATING UNIT -0.3 to +4.0 V Supply Voltage -0.5 to +5.5 V -0.5 to +5.5 V Input Voltage -0.3 to VDD+0.3 V Operating Temperature -40 to +85 °C Storage Temperature -40 to +125 °C SSOP24 600 Power Dissipation PD mW QFN28 640 * * : Mounted on two-layer board of based on the JEDEC. Note 1) All voltage values are specified as VSS= VSSR= VSSL=0V. Note 2) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electrical characteristics conditions will cause malfunction and poor reliability. Note 3) Decoupling capacitors should be connected between VDD-VSS, VDDR-VSSR and VDDL-VSSL due to the stabilized operation. ! ELECTRICAL CHARACTERISTICS PARAMETER VDDL, VDDR Supply Voltage VDD Supply Voltage Output Power Efficiency Output THD Output Power S/N Dynamic Range Channel Separation Output Level Difference Between Lch and Rch Maximum Mute Attenuation Passband Response Power Supply Current At Standby Power Supply Current At Operating Input Voltage Input Leakage Current (Ta=25°C, VDD=VDDL=VDDR=3.3V, fS=44.1kHz, Input Signal=1kHz, Input Signal Level at Full Scale Output, MCK=256fS, Load Impedance=8Ω, nd Measuring Band=20Hz to 20kHz, 2 -order 34kHz LC Filter (Q=0.85), unless otherwise noted) SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Note VDD 5.25 V 3.0 3.3 3.6 V Eeff Vo= 0dB 80 % 4 THD Vo=-6dB 0.1 % Po Vo= 0dB TBD 800 mW/ch SN A weight 85 90 dB Drange A weight 85 90 dB Echn EIAJ(1kHz) 60 dB CHD MAT PR IST IDD VIH VIL ILK Note 4) Power Efficiency (%) = - 10 - 20Hz to 20kHz Stopping MCK, BCK, LRCK, DIN No-load operating No signal inputted - - 3 dB 90 - - ±1 dB dB - - 10 µA - 13 20 mA 0.7VDD 0 - - VDD 0.3VDD ±1.0 V V µA OUTL Output Power + OUTR Output Power (W) VDDL Supply Power + VDDR Supply Power (W) × 100 Ver.2004-04-26 NJU8725 Note 5) Analog AC Characteristics Test System Analog AC characteristics test system is shown in Figure 6. The analog AC characteristics of NJU8725 nd is measured with 2 -order LC LPF on the test board and Filters in the Audio Analyzer. Digital Data Digital Audio Interface Receiver Chip nd NJU8725 NJU8725 Evaluation Board 2 -order LC LPF Filters THD Measuring Apparatus Audio Analyzer Figure 6. Analog AC Characteristics Measurement System nd 2 -order LPF Filters Ver.2004-04-26 : fc=34kHz, refer to the LPF on Application Circuit. th : 22Hz HPF + 20kHz 10 -order LPF (with the A-Weighting Filter at measuring S/N and Dynamic-range) - 11 - NJU8725 ! TIMING CHARACTERISTICS • Master Clock Input tMCKH tMCKL MCK (Ta=25°C, VDD=VDDL=VDDR=3.3V, unless otherwise noted) PARAMETER MCK Frequency MCK Pulse Width (H) SYMBOL fMCKI tMCKH MCK Pulse Width (L) tMCKL Note 6) • CONDITIONS 256fS MIN. 7.28 12 TYP. - MAX. 27.648 - UNIT MHz ns 12 - - ns tMCKI shows the cycle of the MCK signal. Reset Input tRST RST (Ta=25°C, VDD=VDDL=VDDR=3.3V, unless otherwise noted) PARAMETER Reset Low Level Width • SYMBOL tRST CONDITIONS MIN. 3 TYP. - MAX. - UNIT ms tBCLK Digital Audio Signal Interface BCK tBLR tLRB tBCKL tBCKH LRCK tDS tDH DIN PARAMETER Audio DAC Sampling Rate DIN Setup Time DIN Hold Time BCK Period BCK Pulse Width (H) BCK Pulse Width (L) LRCK Hold Time LRCK Setup Time - 12 - SYMBOL fS tDS tDH tBCLK tBCKH tBCKL tBLR tLRB (Ta=25°C, VDD=VDDL=VDDR=3.3V, unless otherwise noted) CONDITIONS MIN. TYP. MAX. UNIT 28 100 KHz 20 ns 20 ns 1/(128fS) ns 20 ns 20 ns 20 ns 20 ns Ver.2004-04-26 NJU8725 • Control Register Interface tRQS tRQH tREH F1/REQ tSCL tSCH F2/SCK tSCK B7 B6 B5 B4 B2 B3 B1 B0 tDAS tDAH PARAMETER F2/SCK Period SYMBOL tSCK (Ta=25°C, VDD=VDDL=VDDR=3.3V, unless otherwise noted) CONDITIONS MIN. TYP. MAX. UNIT 2 µs F2/SCK Pulse Width (H) tSCH 0.8 - - µs F2/SCK Pulse Width (L) tSCL 0.8 - - µs F0/DATA Setup Time tDAS 0.8 - - µs F0/DATA Hold Time tDAH 0.8 - - µs F1/REQ Pulse Width (H) tREH 1.6 - - µs F2/SCK Setup Time tRQS 0.8 - - µs F1/REQ Hold Time tRQH 0.8 - - µs • Input Signal Rise and Fall Time tUP tDN (Ta=25°C, VDD=VDDL=VDDR=3.3V, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Rise Time tUP - - 100 ns Fall Time tDN - - 100 ns Note 7) Ver.2004-04-26 All timings are based on 30% and 70% voltage level of VDD. - 13 - NJU8725 ! APPLICATION CIRCUIT •A915BY-220M is manufactured by TOKO, INC. For further information, please refer to its technical papers. A915BY-220M 10µF 12(10) 22µH VDD 1.0µF 1.0µF 1(26) 3.3V 6(3) 1.0µF OUTLP 22µH VSS OUTLN 8(6) Mode Control 10(8) 24(25) 23(24) 22(23) 11(9) 2(27) 4(1) 3(28) MODE F0/DATA F1/REQ F2/SCK RST STBY MUTE TEST 1.0µF 22µH 22µH OUTRN VDDL VDDL VSSL VDDR VDDR VSSR Speaker A915BY-220M 19(19) 1.0µF DIN OUTRP NJU8725 Digital Audio Data 13(11) 14(12) MCK 15(13) BCK 21(21) LRCK 8Ω 17(16) 8Ω Speaker A915BY-220M 5(2) 100µF 9(7) 2.2µF Switching Regulator 2.2µF 7(4,5) 2.2µF 20(20) 16(15) 2.2µF 2.2µF 18(17,18) * () indicates pin number of QFN28. Note 8) Note 9) De-coupling capacitors must be connected between each power supply pin and GND pin. The power supply for VDDL and VDDR require fast driving response performance such as a switching regulator for THD. Note 10) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please consider and check the circuit carefully to fit your application. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 14 - Ver.2004-04-26