a module solution provider
WG3221E00 User Guide
WG3221-00 Evaluation Board
Drift 0.1
Prepared By
Reviewed By
Copyright © JORJIN TECHNOLOGIES INC. 2019
http://WWW.JORJIN.COM.TW
Approved By
Doc No: WG3221E00A-UG-D01
Index
1. INTRODUCTION............................................................................................................................ 2
2. HARDWARE DESCRIPTION ....................................................................................................... 3
2.1. BOARD OVERVIEW ........................................................................................................................ 3
2.2. POWER SUPPLY ............................................................................................................................. 4
2.3. SDIO INTERFACES ........................................................................................................................ 5
2.4. HCI UART INTERFACE................................................................................................................. 5
2.5. PCM/I2S INTERFACE .................................................................................................................... 5
2.6. LEDS ........................................................................................................................................... 6
2.7. WLAN/BT RESET OR OFF ............................................................................................................ 6
3. SCHEMATIC DIAGRAMS ............................................................................................................ 7
4. HISTORY CHANGE ..................................................................................................................... 11
Copyright © JORJIN TECHNOLOGIES INC. 2019
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1.
INTRODUCTION
The Jorjin WG3221-00 is a wireless local area network (WLAN) and Bluetooth (BT)
combination module to support 1 × 1 IEEE 802.11a/b/g/n/ac WLAN standards and
BT5.0. This document is a user guide for the Jorjin WG3221-00 Evaluation Board. The
WG3221E00 EVB is configured to SDIO for WLAN interface, as well as UART for
Bluetooth.
This document is intended primarily for configuring the WG3221-00 for connectivity
testing in the lab.
Figure 1: WG32210-00 Evaluation Board
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Doc No: WG3221E00A-UG-D01
2. HARDWARE DESCRIPTION
2.1. Board overview
The following figure and table describe physical sections of the board.
L
M
K
G J
H
I
D
Q
N
B
P
O
R
U
S
A
C
T
V
X
W
E
F
Figure 2: WG3221E00 board components
Table 1: WG3221E00 board component descriptions
Region Description
A
WG3221-00 module
B
WLAN/BT RF signal I-PEX connector ( part Number : 20449-001E )
C
SDIO card for WLAN
D
WLAN SDIO signals for measurement
E
WLAN SDIO signals for Renesas SK-S7G2 and PK-S5D9 evaluation
board
F
WLAN SDIO signals for Renesas TB-S5D5 evaluation board
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Doc No: WG3221E00A-UG-D01
G
External 3.3V power supply input points
H
3.3V power source selection
I
VIO power source selection
J
Current measurement jumper for 1.8V power
K
3.3V to 1.8V LDO
L
EJTAG debug mode connector. Not used.
M
Debug UART connector. Not used.
N
Current measurement jumper for 3.3V power of WG3221-00 module
O
BT function reset switch and jumper.
P
WLAN function reset switch and jumper.
Q
LED indicators
R
BT PCM signals connector.
S
Boot Strap/DEBUG connector. Not used.
T
UART to USB connector for BT function test.
U
UART to USB chip for BT function test.
V
Jumpers for BT HCI UART signals to USB interface.
W
HCI_UART_RXD test jump for debugging.
X
BT HCI UART signals for measurement or connecting to external
circuit.
2.2. Power supply
Green LED CR2 (Figure 2: WG3221E00 board components" – region Q) signals the
board is being powered 3.3V, either via:
SD card – SD1 (Figure 2: WG3221E00 board components" – region C), J13 (Figure
2: WG3221E00 board components" – region F), or J14 (Figure 2: WG3221E00
board components" – region E)
an external DC power supply from TP2 (+3.3V) and TP3(GND). (Figure 2:
WG3221E00 board components" – region G)
Green LED CR1 (Figure 2: WG3221E00 board components" – region Q) signals the
board is being powered 1.8, via the 3.3V to 1.8V LDO (Figure 2: WG3221E00 board
components" – region K).
The jumper J3 (Figure 2: WG3221E00 board components" – region I) sets the VIO
Copyright © JORJIN TECHNOLOGIES INC. 2019
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Doc No: WG3221E00A-UG-D01
power level.
Table 2: WG3221E00 VIO power supply modes
VIO power level
J3
Comment
3.3V
Fitted:1-2
The I/O pins signal level is 3.3V
1.8V
Fitted:2-3
The I/O pins signal level is 1.8V
2.3. SDIO interfaces
There are 4 SDIO connectors in the WG3221E00 for WLAN interface. The host CPU
can be connected to SDIO interface through either one of the connectors.
Table 3: WG3221E00 SDIO interface
Connector
Region
Description
SD1
C
Standard SDIO card
J17
D
For external SDIO interface
J14
E
WLAN SDIO signals for Renesas SK-S7G2 and PK-S5D9 evaluation board
J13
F
WLAN SDIO signals for Renesas TB-S5D5 evaluation board
2.4. HCI UART interface
The host CPU can be connected to HCI interface through the J12 (Figure 2:
WG3221E00 board components" – region X). When the J12 is connected to host CPU,
the jumpers in J15 (Figure 2: WG3221E00 board components" – region V) must be
removed.
The HCI UART can be also connected through USB –J18 (Figure 2: WG3221E00 board
components" – region X). When the J18 is connected to USB host, the jumpers in J15
must be installed.
2.5. PCM/I2S interface
The BT PCM signals are connected to J11 (Figure 2: WG3221E00 board
components" – region R).
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2.6. LEDs
There are 4 LEDs (Figure 2: WG3221E00 board components" – region Q) indicate the
board status.
Table 4: WG3221E00 LEDs
LED #
Description
CR1
It indicates the board is being powered 1.8V.
CR2
It indicates the board is being powered 3.3V.
CR3
It indicates the BT function.
CR4
It indicates the WLAN function.
2.7. WLAN/BT reset or off
The board has two buttons to reset the WLAN and BT function (Figure 2: WG3221E00
board components" – region O and P). The board also has two jumpers to turn off
the WLAN and BT function.
Table 5: WG3221E00 WLAN/BT reset and turn off
Button #
Jumper #
Description
SW1
J5
Push the button to reset or fit the jumper to turn off WLAN function
SW2
J6
Push the button to reset or fit the jumper to turn off BT function
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3. SCHEMATIC DIAGRAMS
Figure 3: WG3221E00: WG3221-00 module
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HEADER 1x2
H-1X2_2.54MM
3D_SY NC
PCM_CLK
GND
GND
GND
PCM_OUT
NC
PCM_IN
NC
PCM_SY NC
GND
UART RTS
NC
UART_RXD
NC
UART_TXD
GND
GND
UART CTS
GND
NC
UART_WAKE#
NC
SDIO_CLK
GND
SDIO_CMD
SDIO_DATA2
SDIO_DATA3
SDIO_INT_L
WL_EN
SDIO_DATA1
76
75
VDD_3V3_MO
74
73
72
C2
71
0.1uF
CAP0402
70
69
68
67
66
65
64
63
BT_EN
62
61
PCM_CLK
60
PCM_OUT
59
PCM_IN
58
PCM_SY NC
57
HCI_UART_RTS
56
HCI_UART_RXD
55
HCI_UART_TXD
54
HCI_UART_CTS
53
HCI_UART_WAKEHOST_L
52
SDIO_CLK
51
SDIO_CMD
50
SDIO_DATA0
49
SDIO_DATA1
48
47
29
WLAN_RF_KILL
SDIO_DATA0
GPIO35
32KHz_CLK_IN
46
28
WLAN_RF_KILL_L
GND
GPIO11
27
32KHZ_CLK_IN
NC
45
26
BT_ EN
VDDIO_AO_PM_ext
25
NC
44
24
BT_LED
GND
23
LTE_ATIVE
43
22
WLAN_LED
42
21
LTE_UART_TXD
PCIE_RXP
20
EXT_4.2V
41
19
LTE_UART_RXD
40
18
EXT_4.2V
GND
PCIE_RXN
17
GND
GND
16
NC
PCIE_TXP
15
TP1
GND
39
14
BT_USB_DN
NC
PCIE_TXN
13
NC
38
LTE_UART_TXD
BT_USB_DP
GND
12
NC
37
11
LTE_UART_RXD
GND
PCIE_REFCLKP
10
3.3V
GND
36
9
3.3V
PCIE_REFCLKN
8
3.3V
GND
35
7
3.3V
GND
GND
0.1uF
CAP0402
GND
34
6
NC
33
5
C1
GND
32
4
GND
NC
PCIE_RST_L
3
NC\1216A-LPGA-PIN OUT
NC
PCIE_CLKREQ_L
2
PCIE_WAKE_L
1
30
VDD_3V3_MO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U1
2
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
108
107
106
105
104
103
102
101
100
99
98
97
VDD_3V3_MO
J1
1
31
VDD_3V3_IN
SDIO_DATA2
VDD_IO
PCIE_WAKE_L
SDIO_DATA3
PCIE_CLKREQ_L
SDIO_INTERRUPT_L
C3
WLAN_EN
0.1uF
CAP0402
GPIO35
GPIO11
Figure 4: WG3221E00: Power
Micro SD Power
Power Supply
3.3V
Supply
Power source selection
TP3
TEST POINT
VDD_MCRSD
1
1
VDD_3V3_IN
HEADER 1x3
H-1X3_2.54MM
3
10uF
CAP0603
VDD_IO
J3
C4
2
C5
VDD_3V3_IN
VDD_3V3_IN
J2
EXT_3V3
0.1uF
CAP0402
2
HEADER 1x3
H-1X3_2.54MM
VDD_IO
C6
0.1uF
CAP0402
3
TP2
TEST POINT
1
VDD_MCRSD
1
External
EXT_3V3
VDD_1V8
3.3V to 1.8V
VDD_3V3_IN
U2
VDD_1V8
J4
1
2
C7
C8
0.1uF
CAP0402
10uF
CAP0603
3
IN
OUT
5
1
GND
EN
NR
4
C9
C10
10uF
CAP0603
0.1uF
CAP0402
2
HEADER 1x2
H-1X2_2.54MM
C11
TPS73618DBV
10nF
CAP0402
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Figure 5: WG3221E00: SDIO interface
VDD_MCRSD
SD-MMC Connect
SD1
DAT1
DAT0
VSS2
CLK
VDD
VSS1
CMD
DAT3
DAT2
8
SDIO_DATA1_R
R24
27R RES0402
SDIO_DATA1
7
SDIO_DATA0_R
R27
27R RES0402
SDIO_DATA0
SDIO_CLK_R
R30
27R RES0402
SDIO_CLK
2
SDIO_CMD_R
R32
27R RES0402
SDIO_CMD
1
SDIO_DATA3_R
R34
27R RES0402
SDIO_DATA3
9
SDIO_DATA2_R
R35
27R RES0402
SDIO_DATA2
SDIO_DATA1
SDIO_DATA0
6
5
SDIO_CLK
4
3
SDIO_CMD
SDIO_DATA3
SDIO_DATA2
SD9-PCB
VDD_IO
J13
VDD_MCRSD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J14
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
R41
VDD_MCRSD
SDIO_CLK
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
SDIO_DATA3_R
SDIO_DATA2_R
SDIO_DATA1_R
SDIO_DATA0_R
SDIO_CMD_R
SDIO_CLK_R
SDIO_CLK_R
SDIO_CMD_R
SDIO_DATA0_R
SDIO_DATA1_R
SDIO_DATA2_R
SDIO_DATA3_R
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
10K
RES0402
C24
NC
CAP0402
VDD_IO
R43
SDIO_DATA3
10K/NC
RES0402
R45
SDIO_DATA2
10K/NC
RES0402
R46
SDIO_DATA1
HEADER 20X2
TB-S5D5
SK-S7G2 / PK-S5D9
HEADER 20X2
10K/NC
RES0402
VDD_IO
VDD_MCRSD
J17
R47
SDIO_DATA0
1
2
3
4
5
6
7
8
SDIO_DATA1_R
SDIO_DATA0_R
SDIO_CLK_R
SDIO_CMD_R
SDIO_DATA3_R
SDIO_DATA2_R
10K/NC
RES0402
VDD_IO
R48
SDIO_CMD
10K/NC
RES0402
NC
Figure 6: WG3221E00: UART to USB
USB_5V
VDD_3V3_IN
R36
C18
C19
0.1uF
CAP0402
0.1uF
CAP0402
470R
R0402
C20
C21
0.1uF
CAP0402
0.1uF
CAP0402
C22
0.1uF
CAP0402
AVCC
VCC2
VCC1
VCCIOA
VCCIOB
46
3
42
14
31
U4
FIFO
LQFP-48
USB_5V
J16
SHIELD
SHIELD
SHIELD
SHIELD
SHIELD
SHIELD
VBus
DD+
ID
GND
R37
27R
RES0402
1
2
3
4
5
R38
27R
RES0402
IN
1
USB Micro-B SMT
MicroUSB-5P
GND
OUT
2
6
8
7
USB_5V
R39
1.5K
RES0402
CRS1
6M
CSTCR6M00G15
R42
1M
R0402
5
4
43
44
48
1
2
47
3V3OUT
USBDM
USBDP
ACBUS0
ACBUS1
ACBUS2
ACBUS3
SI/WUA
RSTOUT#
RESET#
XTIN
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
USB_WL/BT
XTOUT
EECS
EESK
EEDATA
TEST
BCBUS0
BCBUS1
BCBUS2
BCBUS3
SI/WUB
3
15
13
12
11
10
40
39
38
37
36
35
33
32
30
29
28
27
26
HOST_HCI_TX
HOST_HCI_RX
HOST_HCI_RTS
HOST_HCI_CTS
1
3
5
7
2
4
6
8
HCI_UART_RXD_K
HCI_UART_TXD
HCI_UART_CTS
HCI_UART_RTS
HEADER 4X2
R40
10K
RES0402
VDD_3V3_IN
USB_TX
USB_RX
USB_RTS
USB_CTS
TP4
TP5
TP6
TP7
R44
10K
RES0402
VDD_3V3_IN
41
AGND
GND
GND
GND
GND
PWREN#
24
23
22
21
20
19
17
16
45
9
18
25
34
6
7
8
9
10
11
C23
33nF
CAP0402
J15
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
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Figure 7: WG3221E00: HCI UART and PCM/I2S interface
R25
PCM_OUT
0R
R26
RES0402
R28
PCM_CLK
J11
1
3
5
7
0R
RES0402
PCM_IN
VDD_3V3_IN
J12
2
4
6
8
R29
0R
RES0402
HEADER 4X2
R33
0R
RES0402
R31
0R
1
2
3
4
5
6
PCM_SY NC
VDD_3V3_IN
0R
RES0402
HCI_UART_TXD
HCI_UART_RXD_K
HCI_UART_CTS
HCI_UART_RTS
C17
HEADER 6
RES0402
0.1uF
CAP0402
Figure 8: WG3221E00: LEDs
VDD_3V3_IN
VDD_3V3_LED
VDD_3V3_LED
VDD_3V3_LED
LED(WLAN/BT)
R1
0R
Power Indicator LED
R7
R8
RES0402
VDD_3V3_LED
220R
R0402
VDD_3V3_LED
220R
R0402
BT
R2
R4
CR2
LTST-C191KGKT
2
CR3
LTST-C191KGKT
LTST-C191KGKT
CR4
LTST-C191KGKT
PCIE_WAKE_L
Q1
BSS138W-7-F
2
VDD_1V8
220R
R0402
1
1
220R
R0402
WLAN
2
CR1
2
1
R3
HCI_UART_WAKEHOST_L
1
10K
RES0402
Figure 9: WG3221E00: WLAN/BT reset and off
WLAN RESET
BT RESET
VDD_IO
J5
1
VDD_IO
J6
R5
2
1
10K
RES0402
HEADER 1x2
H-1X2_2.54MM
R6
R10
BT_EN
27R
RES0402
C12
SW-SPST
10K
RES0402
HEADER 1x2
H-1X2_2.54MM
WLAN_EN
SW1
R9
2
SW2
C14
0.1uF
CAP0402
SW-SPST
27R
RES0402
0.1uF
CAP0402
Figure 10: WG3221E00: 32.768KHz Clock source
VDD_3V3_IN
C13
Y1
1
2
3
4
5
6
VIO
NC1
NC2
NC3
NC4
GND
SG-3030LC
VCC
NC8
NC7
NC6
NC5
OUT
12
11
10
9
8
7
32.768K
Clock
Source
0.1uF
CAP0402
R11
32KHZ_CLK_IN
27R
RES0402
C15
NC
CAP0402
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Figure 11: WG3221E00: 32.768KHz Clock source
VDD_3V3_IN
EJTAG/SDIO mode
3.3V level
R15
R16
R17
R18
R19
R20
10K
RES0402
10K
RES0402
10K
RES0402
100R
R0402
NC
RES0402
10K
RES0402
TDI
WLAN_RF_KILL_L
SDIO_INTERRUPT_L
LTE_UART_TXD
J9
1
3
5
7
9
11
13
TDO
TCK
TRSTN
HCI_UART_WAKEHOST_L
2
4
6
8
10
12
14
LTE_UART_RXD
HEADER 7X2
Boot Strap/DEBUG
J7
2
4
6
8
10
12
ISO_SW
HCI_UART_RXD
HCI_UART_TXD
1
3
5
7
9
11
R13
R14
10K
RES0402
10K
RES0402
HEADER 6X2
DEBUG UART
VDD_IO
VDD_3V3_IN
VDD_IO
R21
R22
R23
10K
RES0402
10K
RES0402
VDD_3V3_IN
1
3
5
7
PCIE_CLKREQ_L
PCIE_WAKE_L
10K
RES0402
J10
2
4
6
8
GPIO11
GPIO35
SDIO_INTERRUPT_L
GPIO11
GPIO35
SDIO_INTERRUPT_L
HEADER 4X2
VDD_3V3_IN
VDD_3V3_IN
R12
U3
C16
10K
RES0402
ISO_SW
HCI_UART_RXD_K
4
1
VCC
5
0.1uF
CAP0402
C
A
B
GND
2
HCI_UART_RXD
3
SN74LVC1G66
J8
1
2
HEADER 1x2
H-1X2_2.54MM
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4. HISTORY CHANGE
Revision
Date
Description
D 0.1
2019/Jan/16
Draft release
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