SIT2018AERS3-33N-24.000000

SiT2018 High Temp, Single-Chip, One-Output Clock Generator The Smart Timing Choice The Smart Timing Choice Features Applications  Frequencies between 1 MHz and 110 MHz accurate to 6 decimal places  Industrial, medical, automotive, avionics and other high temperature applications  Operating temperature from -40°C to 125°C. For -55°C option, refer to SiT2020 and SiT2021  Industrial sensors, PLC, motor servo, outdoor networking equipment, medical video cam, asset tracking systems, etc.  Supply voltage of 1.8V or 2.5V to 3.3V  Excellent total frequency stability as low as ±20 ppm  Low power consumption of 3.6 mA typical at 1.8V  LVCMOS/LVTTL compatible output  5-pin SOT23-5 package: 2.9mm x 2.8mm  RoHS and REACH compliant, Pb-free, Halogen-free and Antimony-free  For AEC-Q100 clock generators, refer to SiT2024 and SiT2025 Electrical Specifications Table 1. Electrical Characteristics[1, 2] Parameters Symbol Min. Typ. Max. Unit Condition Frequency Range Output Frequency Range f 1 – 110 MHz F_stab -20 – +20 ppm -25 – +25 ppm -30 – +30 ppm -50 – +50 ppm Refer to Table 14 for the exact list of supported frequencies list of supported frequencies Frequency Stability and Aging Frequency Stability Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and variations over operating temperature, rated power supply voltage and load (15 pF ± 10%). Operating Temperature Range Operating Temperature Range (ambient) T_use -40 – +105 °C Extended Industrial -40 – +125 °C Automotive Supply Voltage and Current Consumption Supply Voltage Current Consumption OE Disable Current Standby Current Vdd Idd I_od I_std 1.62 1.8 1.98 V 2.25 2.5 2.75 V 2.52 2.8 3.08 V 2.7 3.0 3.3 V 2.97 3.3 3.63 V 2.25 – 3.63 V – 3.8 4.5 mA No load condition, f = 20 MHz, Vdd = 2.8V, 3.0V or 3.3V – 3.6 4.2 mA No load condition, f = 20 MHz, Vdd = 2.5V – 3.4 4 mA No load condition, f = 20 MHz, Vdd = 1.8V – – 4.4 mA Vdd = 2.5V to 3.3V, OE = Low, output in high Z state. – – 4.1 mA Vdd = 1.8V, OE = Low, output in high Z state. – 2.6 8.5 A Vdd = 2.8V to 3.3V, ST = Low, Output is Weakly Pulled Down – 1.4 5.5 A Vdd = 2.5V, ST = Low, Output is Weakly Pulled Down 0.6 3.5 A Vdd = 1.8V, ST = Low, Output is Weakly Pulled Down – LVCMOS Output Characteristics Duty Cycle Rise/Fall Time DC 45 – 55 % Tr, Tf – 1.0 2.0 ns All Vdds Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80% – 1.3 2.5 ns Vdd =1.8V, 20% - 80% Vdd = 2.25V - 3.63V, 20% - 80% – 1.0 3 ns Output High Voltage VOH 90% – – Vdd IOH = -4 mA (Vdd = 3.0V or 3.3V) IOH = -3 mA (Vdd = 2.8V or 2.5V) IOH = -2 mA (Vdd = 1.8V) Output Low Voltage VOL – – 10% Vdd IOL = 4 mA (Vdd = 3.0V or 3.3V) IOL = 3 mA (Vdd = 2.8V or 2.5V) IOL = 2 mA (Vdd = 1.8V) SiTime Corporation Rev. 1.0 990 Almanor Avenue, Sunnyvale, CA 94085 (408) 328-4400 www.sitime.com Revised October 16, 2014 SiT2018 High Temp, Single-Chip, One-Output Clock Generator The Smart Timing Choice The Smart Timing Choice Table 1. Electrical Characteristics[1, 2] (continued) Parameters Symbol Min. Typ. Max. Unit Condition Input Characteristics Input High Voltage VIH 70% – – Vdd Input Low Voltage VIL – – 30% Vdd Pin 3, OE or ST Input Pull-up Impedence Z_in 50 87 150 k Pin 3, OE logic high or logic low, or ST logic high – – M Pin 3, ST logic low 2 Pin 3, OE or ST Startup and Resume Timing Startup Time T_start – – 5 ms Measured from the time Vdd reaches 90% of final value T_oe – – 130 ns T_resume – – 5 ms f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * clock periods Measured from the time ST pin crosses 50% threshold f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V Enable/Disable Time Resume Time Jitter RMS Period Jitter T_jitt – 1.6 2.5 ps – 1.9 3 ps f = 75 MHz, Vdd = 1.8V 12 20 ps f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V Peak-to-peak Period Jitter T_pk – – 14 25 ps f = 75 MHz, Vdd = 1.8V RMS Phase Jitter (random) T_phj – 0.5 0.8 ps f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz – 1.3 2 ps f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz Notes: 1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated. 2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at 25°C temperature. Table 2. Pin Description Pin Symbol 1 GND Power 2 NC No Connect 3 OE/ ST/NC OE/ST/NC NC No connect Output Enable H[4]: specified frequency output L: output is high impedance. Only output driver is disabled. Standby H or Open[4]: specified frequency output L: output is low (weak pull down). Device goes to sleep mode. Supply current reduces to I_std. No Connect 3 2 GND 1 Any voltage between 0 and Vdd or Open[4]: Specified frequency output. Pin 3 has no function. 4 VDD Power Power supply voltage[3] 5 OUT Output Oscillator output Notes: 3. A capacitor of value 0.1 µF or higher between Vdd and GND is required. 4. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven. If pin 3 needs to be left floating, use the NC option. Rev. 1.0 Top View Functionality Electrical ground[3] Page 2 of 12 4 5 VDD OUT Figure 1. Pin Assignments www.sitime.com SiT2018 High Temp, Single-Chip, One-Output Clock Generator The Smart Timing Choice The Smart Timing Choice N Table 3. Absolute Maximum Limits Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Min. Max. Unit Storage Temperature Parameter -65 150 °C Vdd -0.5 4 V Electrostatic Discharge – 2000 V Soldering Temperature (follow standard Pb free soldering guidelines) – 260 °C Junction Temperature[5] – 150 °C Note: 5. Exceeding this temperature for extended period of time may damage the device. Table 4. Thermal Consideration[6] JA, 4 Layer Board JC, Bottom 421 175 (°C/W) Package SOT23-5 (°C/W) Note: 6. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table. Table 5. Maximum Operating Junction Temperature[7] Max Operating Temperature (ambient) Maximum Operating Junction Temperature 105°C 115°C 125°C 135°C Note: 7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature. Table 6. Environmental Compliance Parameter Condition/Test Method Mechanical Shock MIL-STD-883F, Method 2002 Mechanical Vibration MIL-STD-883F, Method 2007 Temperature Cycle JESD22, Method A104 Solderability MIL-STD-883F, Method 2003 Moisture Sensitivity Level MSL1 @ 260°C Rev. 1.0 Page 3 of 12 www.sitime.com SiT2018 High Temp, Single-Chip, One-Output Clock Generator The Smart Timing Choice The Smart Timing Choice Test Circuit and Waveform[8] Vout Test Point Vdd Tr 5 15 pF (including probe and fixture capacitance) 4 1 2 Power Supply 0.1µF 3 Tf 80% Vdd 50% 20% Vdd High Pulse (TH) Low Pulse (TL) Vdd 1k Period OE/ST Function Figure 2. Test Circuit Figure 3. Output Waveform Note: 8. Duty Cycle is computed as Duty Cycle = TH/Period. Timing Diagrams 90% Vdd Vdd Vdd 50% Vdd Pin 4 Voltage T_start [9] ST Voltage No Glitch during start up T_resume CLK Output CLK Output T_start: Time to start from power-off T_resume: Time to resume from ST Figure 4. Startup Timing (OE/ST Mode) Figure 5. Standby Resume Timing (ST Mode Only) u Vdd Vdd 50% Vdd OE Voltage OE Voltage 50% Vdd T_oe T_oe CLK Output CLK Output HZ T_oe: Time to re-enable the clock output T_oe: Time to put the output in High Z mode Figure 6. OE Enable Timing (OE Mode Only) Figure 7. OE Disable Timing (OE Mode Only) Note: 9. SiT2018 has “no runt” pulses and “no glitch” output during startup or resume. Rev. 1.0 Page 4 of 12 www.sitime.com SiT2018 High Temp, Single-Chip, One-Output Clock Generator The Smart Timing Choice The Smart Timing Choice Performance Plots[10] D UT 1 D UT 5 D UT 9 1.8 V 2.5 V 2.8 V 3V D UT 2 D UT 6 D UT 10 D UT 3 D UT 7 D UT 4 D UT 8 25 3.3 V 20 6.0 15 Frequency (ppm) Idd (mA) 5.5 10 ) m p (p y c n e u q e r F 5.0 4.5 4.0 3.5 5 0 -5 -10 -15 -20 3.0 0 20 40 60 80 100 -25 -40 Frequency (MHz) 2.5 V 2.8 V 0 20 40 60 80 100 120 T em perature(°C) ( C) Temperature Figure 8. Idd vs Frequency 1.8 V -20 3.0 V Figure 9. Frequency vs Temperature 1.8 V 3.3 V 2.5 V 2.8 V 3.0 V 3.3 V 55 4.0 53 3.0 Duty cycle (%) RMS period jitter (ps) 54 3.5 2.5 2.0 1.5 1.0 52 51 50 49 48 47 0.5 46 0.0 0 20 40 60 80 45 100 0 20 40 Frequency (MHz) Figure 10. RMS Period Jitter vs Frequency 2.5 V 2.8 V 3.0 V 1.8 V 3.3 V 2.5 2.5 2.0 2.0 1.5 1.0 100 2.5 V 2.8 V 3.0 V 3.3 V 1.5 1.0 0.5 0.5 0.0 0.0 -40 -20 0 20 40 60 80 100 -40 120 Temperature (°C) -20 0 20 40 60 80 100 120 Temperature (°C) Figure 12. 20%-80% Rise Time vs Temperature Rev. 1.0 80 Figure 11. Duty Cycle vs Frequency Fall time (ns) Rise time (ns) 1.8 V 60 Frequency (MHz) Figure 13. 20%-80% Fall Time vs Temperature Page 5 of 12 www.sitime.com SiT2018 High Temp, Single-Chip, One-Output Clock Generator The Smart Timing Choice The Smart Timing Choice Performance Plots[10] 2.5 V 2.8 V 3.0 V 3.3 V 1.8 V 2.5 V 2.8 V 3.0 V 3.3 V 1 0.9 0.8 IPJ (ps) IPJ (ps) 1.8 V 2 1.9 1.8 1.7 )s 1.6 (p J  1.5 P I 1.4 1.3 1.2 1.1 1 )s 0.7 p  (J P I 0.6 0.5 0.4 0.3 10 30 50 70 90 110 10 Frequency (MHz) Frequency (MHz) 30 50 70 90 110 Frequency (MHz) Frequency (MHz) Figure 14. RMS Integrated Phase Jitter Random (12 kHz to 20 MHz) vs Frequency[11] Figure 15. RMS Integrated Phase Jitter Random (900 kHz to 7.5 MHz) vs Frequency[11] Notes: 10. All plots are measured with 15 pF load at room temperature, unless otherwise stated. 11. Phase noise plots are measured with Agilent E5052B signal source analyzer. Integration range is up to 5 MHz for carrier frequencies up to 40 MHz. Rev. 1.0 Page 6 of 12 www.sitime.com SiT2018 High Temp, Single-Chip, One-Output Clock Generator The Smart Timing Choice The Smart Timing Choice Programmable Drive Strength The SiT2018 includes a programmable drive strength feature to provide a simple, flexible tool to optimize the clock rise/fall time for specific applications. Benefits from the programmable drive strength feature are: The SiT2018 can support up to 60 pF in maximum capacitive loads with drive strength settings. Refer to the Rise/Tall Time Tables (Table 7 to 11) to determine the proper drive strength for the desired combination of output load vs. rise/fall time SiT2018 Drive Strength Selection • Improves system radiated electromagnetic interference (EMI) by slowing down the clock rise/fall time • Improves the downstream clock receiver’s (RX) jitter by decreasing (speeding up) the clock rise/fall time. • Ability to drive large capacitive loads while maintaining full swing with sharp edge rates. For more detailed information about rise/fall time control and drive strength selection, see the SiTime Application Notes section: http://www.sitime.com/support/application-notes. Tables 7 through 11 define the rise/fall time for a given capacitive load and supply voltage. EMI Reduction by Slowing Rise/Fall Time Figure 16 shows the harmonic power reduction as the rise/fall times are increased (slowed down). The rise/fall times are expressed as a ratio of the clock period. For the ratio of 0.05, the signal is very close to a square wave. For the ratio of 0.45, the rise/fall times are very close to near-triangular waveform. These results, for example, show that the 11th clock harmonic can be reduced by 35 dB if the rise/fall edge is increased from 5% of the period to 45% of the period. 4. The left-most column represents the part number code for the corresponding drive strength.   2. Select the capacitive load column that matches the application requirement (5 pF to 60 pF) 3. Under the capacitive load column, select the desired rise/fall times. 5. Add the drive strength code to the part number for ordering purposes. Calculating Maximum Frequency Based on the rise and fall time data given in Tables 7 through 11, the maximum frequency the oscillator can operate with guaranteed full swing of the output voltage over temperature can be calculated as the following: trise=0.05 trise=0.1 trise=0.15 trise=0.2 10 0 Harmonic amplitude (dB) 1. Select the table that matches the SiT2018 nominal supply voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V). M a x F re q u e n c y = trise=0.25 trise=0.3 trise=0.35 trise=0.4 trise=0.45 -10 -20 where Trf_20/80 is the typical value for 20%-80% rise/fall time. -30 Example 1 -40 -50 Calculate fMAX for the following condition: -60 -70 -80 1 5 x T rf_ 2 0 /8 0 1 3 5 7 9 11 Harm onic num ber Figure 16. Harmonic EMI reduction as a Function of Slower Rise/Fall Time Jitter Reduction with Faster Rise/Fall Time Power supply noise can be a source of jitter for the downstream chipset. One way to reduce this jitter is to speed up the rise/fall time of the input clock. Some chipsets may also require faster rise/fall time in order to reduce their sensitivity to this type of jitter. Refer to the Rise/Fall Time Tables (Table 7 to Table 11) to determine the proper drive strength. • Vdd = 1.8V (Table 7) • Capacitive Load: 30 pF • Desired Tr/f time = 3 ns (rise/fall time part number code = E) Part number for the above example: SiT2018AIES2-18E-66.666660 Drive strength code is inserted here. Default setting is “-” High Output Load Capability The rise/fall time of the input clock varies as a function of the actual capacitive load the clock drives. At any given drive strength, the rise/fall time becomes slower as the output load increases. As an example, for a 3.3V SiT2018 device with default drive strength setting, the typical rise/fall time is 1ns for 15 pF output load. The typical rise/fall time slows down to 2.6 ns when the output load increases to 45 pF. One can choose to speed up the rise/fall time to 1.83 ns by then increasing the drive strength setting on the SiT2018. Rev. 1.0 Page 7 of 12 www.sitime.com SiT2018 High Temp, Single-Chip, One-Output Clock Generator The Smart Timing Choice The Smart Timing Choice Rise/Fall Time (20% to 80%) vs CLOAD Tables Table 7. Vdd = 1.8V Rise/Fall Times for Specific CLOAD Table 8. Vdd = 2.5V Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Rise/Fall Time Typ (ns) Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF L A R  B T E U F or "‐": default 6.16 3.19 2.11 1.65 0.93 0.78 0.70 0.65 11.61 6.35 4.31 3.23 1.91 1.66 1.48 1.30 22.00 11.00 7.65 5.79 3.32 2.94 2.64 2.40 31.27 16.01 10.77 8.18 4.66 4.09 3.68 3.35 39.91 21.52 14.47 11.08 6.48 5.74 5.09 4.56 L A R  B T E or "‐": default U F  4.13 2.11 1.45 1.09 0.62 8.25 4.27 2.81 2.20 1.28 12.82 7.64 5.16 3.88 2.27 21.45 11.20 7.65 5.86 3.51 27.79 14.49 9.88 7.57 4.45 0.54 0.43 0.34 1.00 0.96 0.88 2.01 1.81 1.64 3.10 2.79 2.54 4.01 3.65 3.32 Table 9. Vdd = 2.8V Rise/Fall Times for Specific CLOAD Table 10. Vdd = 3.0V Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Rise/Fall Time Typ (ns) Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF L A R  B T 3.77 1.94 1.29 0.97 0.55 7.54 3.90 2.57 2.00 1.12 12.28 7.03 4.72 3.54 2.08 19.57 10.24 7.01 5.43 3.22 25.27 13.34 9.06 6.93 4.08 E or "‐": default U F 0.44 0.34 0.29 1.00 0.88 0.81 1.83 1.64 1.48 2.82 2.52 2.29 3.67 3.30 2.99 L A R  B T or "‐": default E U F 3.60 1.84 1.22 0.89 0.51 0.38 0.30 0.27 7.21 3.71 2.46 1.92 1.00 0.92 0.83 0.76 11.97 6.72 4.54 3.39 1.97 1.72 1.55 1.39 18.74 9.86 6.76 5.20 3.07 2.71 2.40 2.16 24.30 12.68 8.62 6.64 3.90 3.51 3.13 2.85 Table 11. Vdd = 3.3V Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF L A R  B 3.39 1.74 1.16 0.81 6.88 3.50 2.33 1.82 11.63 6.38 4.29 3.22 17.56 8.98 6.04 4.52 23.59 12.19 8.34 6.33 T or "‐": default E U F 0.46 0.33 0.28 0.25 1.00 0.87 0.79 0.72 1.86 1.64 1.46 1.31 2.60 2.30 2.05 1.83 3.84 3.35 2.93 2.61 Rev. 1.0 Page 8 of 12 www.sitime.com SiT2018 High Temp, Single-Chip, One-Output Clock Generator The Smart Timing Choice The Smart Timing Choice Pin 3 Configuration Options (OE, ST, or NC) Pin 3 of the SiT2018 can be factory-programmed to support three modes: Output Enable (OE), standby (ST) or No Connect (NC). In addition, the SiT2018 supports “no runt” pulses, and “no glitch” output during startup or resume as shown in the waveform captures in Figure 17 and Figure 18. Output Enable (OE) Mode In the OE mode, applying logic Low to the OE pin only disables the output driver and puts it in Hi-Z mode. The core of the device continues to operate normally. Power consumption is reduced due to the inactivity of the output. When the OE pin is pulled High, the output is typically enabled in