TDTTP4000W066C-KIT

User Guide TDTTP4000W066C_0V1: 4kW Bridge-less Totem-pole PFC Evaluation Board Overview This user guide describes the TDTTP4000W066C_0v1 4kW bridgeless totem-pole power factor correction (PFC) evaluation board. Very high efficiency single-phase AC-DC conversion is achieved with the TP65H035WSG4, a diode-free Gallium Nitride (GaN) FET bridge with low reverse-recovery charge. Using Transphorm GaN FETs in the fast-switching leg of the circuit and lowresistance MOSFETs in the slow-switching leg of the circuit results in improved performance and efficiency. For more information and complete design files, please visit transphormusa.com/tp4kit. The TDTTP4000W066C_0v1-KIT is for evaluation purposes only. The evaluation board is shown in Fig. 1. Figure 1. TDTTP4000W066B_0v1 4kW totem-pole PFC evaluation board Warning This evaluation board is intended to demonstrate GaN FET technology and is for demonstration purposes only and no guarantees are made for standards compliance. There are areas of this evaluation board that have exposed access to hazardous high voltage levels. Exercise caution to avoid contact with those voltages. Also note that the evaluation board may retain high voltage temporarily after input power has been removed. Exercise caution when handling. When testing converters on an evaluation board, ensure adequate cooling. Apply cooling air with a fan blowing across the converter or across a heat sink attached to the converter. Monitor the converter temperature to ensure it does not exceed the maximum rated per the datasheet specification. February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 1 ` TDTTP4000W066C_0V1 User Guide TDTTP4000W066C_0V1 input/output specifications Input Voltage: 85 Vac to 265 Vac, 47 Hz to 63 Hz Input Current: 18 A (rms) : (2000W at 115 Vac, 4000W at 230 Vac) 10% overload short time: 19.8A (rms) (2200W at 115 Vac, 4400W at 230 Vac) Ambient temperature: < 50 C Output Voltage: 387 Vdc +/- 5 Vdc PWM Frequency: 66 kHz Auxiliary Supply: 12Vdc for bias voltage Power dissipation in the GaN FET is limited by the maximum junction temperature. Refer to the TP650H50WSG4 datasheet Figure 2 shows the input and output connections. To reduce EMI noise, adding a ferrite core at the input and output cable is recommended. Figure 2. Input and output cable connections February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 2 TDTTP4000W066C_0V1 User Guide ` Circuit description for Bridge-Less Totem-Pole PFC based on GaN FET The Bridge-less totem-pole topology is shown in Fig 3 below. As shown in Fig 3(a), two GaN FETs and two diodes are used for the line rectification, while in Fig 3(b), the circuit is modified and the diodes are replaced by two low resistance silicon MOSFETs to eliminate diode drops and improve the efficiency. Further information and discussion on the performance and the characteristics of Bridge-less PFC circuit is provided in [1]. The large recovery charge (Qrr) of existing silicon MOSFETs makes CCM operation of a silicone totem-pole Bridge-less PFC impractical and reduces the total efficiency.. Figure 4(a) is a simplified schematic of a totem-pole PFC in continuous conduction mode (CCM) mode, focused on minimizing conduction losses. It comprises two fast-switching GaN FETs (Q1 and Q2) operating at a high pulse-width-modulation (PWM) frequency and two very low-resistance MOSFETs (S1 and S2) operating at a much slower line frequency (50Hz/60Hz). The primary current path includes one fast switch and one slow switch only, with no diode drop. The function of S1 and S2 is that of a synchronized rectifier as illustrated in Figures 4(b) and 4(c). During the positive AC cycle, S1 is on and S2 is off, forcing the AC neutral line tied to the negative terminal to the DC output. The opposite applies for the negative cycle. In either AC polarity, the two GaN FETs form a synchronized boost converter with one transistor acting as a master switch to allow energy intake by the boost inductor (LB), and another transistor as a slave switch to release energy to the DC output. The roles of the two GaN devices interchange when the polarity of the AC input changes; therefore, each transistor must be able to perform both master and slave functions. To avoid shoot-through a dead time is built in between two switching events, during February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 3 TDTTP4000W066C_0V1 User Guide ` which both transistors are momentarily off. To allow CCM operation, the body diode of the slave transistor must function as a flyback diode for the inductor current to flow during dead time. The diode current; however, must quickly reduce to zero and transition to the reverse blocking state once the master switch turns on. This is the critical process for a totem-pole PFC which, with the high Qrr of the body diode of high-voltage Si MOSFETs, results in abnormal spikes, instability, and associated high switching losses. The low Qrr of the GaN switches allows designers to overcome this barrier. As seen in Figure 5, inductive tests at 430V bus show healthy voltage waveforms up to inductor current exceeding 35A using either a high-side (Figure 5(a)) or low-side (Figure 5(b)) GaN transistor as a master switch. With a design goal of 4.4kW output power in CCM mode at 230VAC input, the required inductor current is 20A. This test confirms a successful totem-pole power block with enough current overhead. Fig 5. Hard-switched waveforms of a pair of GaN FET switches when setting a) high side as master and b) low side as master One issue inherent in the bridgeless totem-pole PFC is the operation mode transition at AC voltage zero-crossing. For instance, when the circuit operation mode changes from positive half-line to negative half-line at the zero-crossing, the duty ratio of the high-side GaN switch changes abruptly from almost 100% to 0% and the duty ratio of low-side GaN switch changes from 0% to 100%. Due to the slow reverse recovery of diodes (or body diode of a MOSFET), the voltage VD cannot jump from ground to VDC instantly; a current spike will be induced. To avoid the problem, a soft-start at every zero-crossing is implemented to gently reverse duty ratio (a soft-start time of a few switching cycles is enough). The TDTTP4000W066C evaluation board is designed to run in CCM and the larger inductance alleviates the current spike issue at zero-crossing. Dead time control The required form of the gate-drive signals is shown in Figure 5. The times marked A are the dead times when neither transistor is driven on. The dead time must be greater than zero to avoid shoot-through currents. The Si8230 gate drive chip ensures a minimum dead time based on the value of resistor R24, connected to the DT input. The dead time in ns is equal to the of 12k corresponds to 120ns. This will add to any dead time already present in the February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 4 TDTTP4000W066C_0V1 User Guide ` input signals. The on-board pulse generator circuit; for example, creates dead times of about 60ns (see Figure 6). The resulting dead time at the gate pins of Q1 and Q2 is about 120ns. Either shorting or removing R7 will reduce the dead time to 60ns. While a typical Si MOSFET has a maximum dV/dt rating of 50V/ns, the TP65H035WSG4 GaN FET will switch at dV/dt of 100V/ns or higher to achieve the lowest possible switching loss. At this level of operation, even the layout becomes a significant contributor to performance. As shown in Figure 8, the recommended layout keeps a minimum gate drive loop and keeps the traces between the switching nodes very short--with the shortest practical return trace to the power bus and ground. The power ground plane provides a large cross-sectional area to achieve an even ground potential throughout the circuit. The layout carefully separates the power ground and the IC (small signal) ground, only joining them at the source pin of the FET to avoid any possible ground loop. Note that the Transphorm GaN FETs in TO-247 packages have pinout configuration of G-S-D, instead of the traditional G-D-S of a MOSFET. The G-S-D configuration is designed with thorough consideration to minimize the gate source driving loop, reducing parasitic inductance and to separate the driving loop (gate source) and power loop (drain source) to minimize noise. All PCB layers of the TDTTP4000W066C_0V1 design are shown Figure 8(a-c) and available in the design files. Design details A detailed circuit schematic is shown in Figures 7 and 8, the PCB layers in Figure 9, and the parts list in Table 1 (also included in the design files). February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 5 ` TDTTP4000W066C_0V1 User Guide Fig 7 February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 6 ` TDTTP4000W066C_0V1 User Guide Fig 8 February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 7 TDTTP4000W066C_0V1 User Guide ` Table 1. TDTTP4000W066C_0V1 evaluation board bill of materials (BOM) TDTTP4000W066C_0V1  Qty  Value  Device  Parts  2    DIODE­DO­214AC  D3, D4  ES1J  1    GBJ2506  D2  GBJ2506­BP  4    LEDCHIP­LED0805  LED1, LED2, LED3,  LED4  SML­211UTT86   1    MA04­1  SV2  961104­6404­AR  1    PJ­002AH  J1  PJ­002AH  2    TEKTRONIX­PCB  TP7, TP8  131­4353­00  TP1, TP2, TP3, TP4,  TP5, TP6, TP10,  TP12, TP13, TP14  C2, C5, C8, C9, C15,  C16, C17, C18, C19,  C20, C21, C24, C27,  C30, C31, C32, C33,  C35, C37, C39, C42,  C44, C50, C52, C53,  C54, C55, C56, C60,  C73  Manufacturer PN  10     TESTPOINT­KEYSTONE5015  5015  30  .1u  C­EUC0603  2 0  R­US_R0603  R59, R71  1 0  R­US_R0805  R72  KTR25JZPF1104   C0603C104J3RACTU  RCS06030000Z0EA   RC0805JR­070RL  6 1.1M  R­US_R1210  R9, R11, R12, R14,  R29, R30  3 1.5u/275V  155MKP275KG  CX1, CX2, CX3  155MKP275KG   1 1N4148  DIODE­SOD123  D1  1N4148W­E3­18  1 1k  R­US_R0805  R6  ERJ­6ENF1001V  2 1n  C­EUC0805  C26, C28  CC0805KRX7R9BB102  TMK107B7105KA­T  6 1u  C­EUC0603  C13, C45, C57, C58,  C69, C80  4 1u  C­USC0603  C63, C64, C65, C66  TMK107B7105KA­T  1 2k  R­US_R0603  R34  RC0603FR­072KL   1 2.1k  R­US_R0805  R53  RC0805FR­072K1L   1 2.2M  R­US_R0805  R48  RMCF0805JT2M20  1 2.2u  C­EUC1206  C59  CL31B225KAHNNNE  1 2K  R­US_R0805  R46  ERJ­6ENF2001V  1 2PIN_9.53MM  2PIN_9.53MM  CN2  20020705­M021B01LF  1 2k  R­US_R0805  R38  ERJ­6ENF2001V  4 3.3K .1%  R­US_R0805  R25, R27, R35, R36  ERA­6AEB332V   1 3.3n  C­EUC0805  C1  C0805C332K5RACTU  1 3.9mH  CMC_42X27MM_SM  L1  T60405­R6128­X225  1 3PIN_9.53MM  3PIN_9.53MM  CN1   T70343500000G   1 4.7k  R­US_R0805  R52  RC0805FR­074K7L   2 4.7n  VY2_CAP_SAFETY  CY1, CY2  3 4.7u  C­EUC1206  C36, C43, C46  February 06, 2020 evk0010.1 B32021A3472M  CL31B475KBHNNNE   © 2020 Transphorm Inc. Subject to change without notice. 8 TDTTP4000W066C_0V1 User Guide ` 1 4m  RES_CSSH2728  R_CS  CSSH2728FT4L00   1 5.1k  R­US_R1206  R58  RC1206FR­075K1L   1 5k  R­US_R0805  R49  RC0805FR­075K1L  1 7.2mH  CMC_42X27MM  L4  1 7.5K  R­US_R0805  R13  ERJ­6ENF7501V  4 7.5k  R­US_R0805  R16, R17, R31, R32  RN73C2A7K5BTDF  1 7.32K  R­US_R0805  R19  RC0805FR­077K32L   2 10  R­US_R0805  R1, R3  ERJ­6GEYJ100V  ERJ­8ENF10R0V  T60405­R6128­X230  6 10  R­US_R1206  R22, R23, R40, R43,  R44, R55  1 10K  R­US_R0603  R39  RC0603FR­0710KL  ERJ­6ENF1002V  11  10k  R­US_R0805  R2, R4, R7, R8, R10,  R15, R37, R45, R47,  R50, R57  1 10k@25C  R­US_0204/5  NTC  B57703M103G40  3 10n  C­EUC1206  C14, C22, C23  SMK316B7103KF­T   2 10p  C­EUC0603  C78, C79  C0603C100K3GACTU   1 10u  C­EUC0805  C86  GRM21BR61E106KA73L   12063D106KAT2A  6 10u  C­EUC1206  C3, C4, C6, C10,  C34, C38  1 10uH  FILM­CAP­C4ATGB_5100  C48  C4ATGBW5100A3FJ   1 12k(65k for 8274)  R­US_R0805  R24  RC0805FR­0712KL   2 15  R­US_R1210  R28, R51  RMCF1210FT15R0   3 15k  R­US_R0805  R18, R21, R54  RC0805FR­0715KL  2 22  R­US_R0805  R42, R70  ERJ­6GEYJ220V  1 22n  C­EUC0805  C61  C2012C0G1V223J060AC   1 22n  ECQ­U2A474ML22N  CX4  PME271M522MR30  2 22u  C­EUC1206  C40, C41  CL31X226KAHN3NE  1 30A  SH32  F1  01020078H  RC1206FR­0737K4L   6 37.4k  R­US_R1206  R60, R61, R62, R63,  R64, R65  2 220  FB0603  FB1, FB2  MMZ1608B221  2 47p  C­EUC1206  C74, C75    CC1206JKNPOZBN470   1 74AUP2G14GW  74AUP2G14GW  U12    NC7WZ14P6X   1 74LVC1G14GW  74LVC1G14GW  U5  NC7SZ14M5X  1 74LVC1G17GW  74LVC1G17GW  IC4  SN74LVC1G17DBVR  1 100k  R­US_R0603  R69  DNI  2 100k  R­US_R0805  R26, R33  ERJ­6ENF1003V  1 100p  C­EUC0603  C25  06035A101FAT2A  4 100u/16v  ELE_CAP_D5MM_P2MM  C7, C29, C81, C85    UKL1C101KPDANA   1 100u/25V  CPOL­USE2.5­7  C12  ESK107M025AC3AA  1 165K  R­US_R0805  R20  ERJ­6ENF1653V  2 220p  C­EUC0805  C11, C51  CC0805KRX7R9BB221  4 470uF  ELE_CAP_D35MM_P10MM  C49, C62, C67, C72  ELXS451VSN471MA45SDatasheet February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 9 TDTTP4000W066C_0V1 User Guide ` 4 680  R­US_R0805  R75, R76, R77, R78  RC0805FR­07680RL   2 CMC_WURTH_744229  CMC_WURTH_744229  LCM1, LCM2  744229  2 DM­TOROID770711  DM­TOROID770711  L2, L3  CWS­1SN­12606  1 FUSE­SMM­10A  FUSE­SMM  F2   0463015.ER   1 G8P­1A4P­DC12  G8P­1A4P  K1  JTN1AS­PA­F­DC12V   1 HF­TOROID  HF­TOROID  L6  CWS­1SN­12554  1 HS­OMNI­41­75  HS­OMNI­41­75  HS1  OMNI­UNI­41­75   1 INA826R  INA826R  IC2  INA826AID  3 JUMPER_S1621­46R  JUMPER_S1621­46R  JP1, JP2, JP3  S1621­46R   1 LT1719  LT1719  U14  LT1719CS6#TRMPBF  1 MALE_CONN_HEADER_4PIN_2.54MM MALE_CONN_HEADER_4PIN_2.54MM J2  961104­6404­AR   1 MCP1501T­18E/CHY  MCP1501T­18E/CHY  IC3  MCP1501T­18E/CHY  2 MCP6001T­E/OT  MCP6001T­E/OT  U4, U16  MCP6001T­E/OT  1 MECF­30­01­L­DV­WT  MECF­30­01­L­DV­WT  CONN1  MECF­30­01­L­DV­WT  1 MIC5259­3.3YD5­TR  MIC5259­3.3YD5­TR  U2  MIC5259­3.3YD5­TR  1 MIC5271YM5­TR  MIC5271YM5­TR  U8  MIC5271YM5­TR  1 MS35_10015  MS35_10015  R5  MS32 10015­B  1  CAP200DG    CAP200DG   U13   CAP200DG   1 NX3008NBK  NX3008NBK  Q5  NX3008NBK,215  1 OPA188  OPA188  U1  OPA188AIDBVT  1 OPA2188  OPA2188  IC1  OPA2188AIDR  1 PDS1­S12­S12­M­TR  PDS1­S12­S12­M­TR  U11  PDS1­S12­S12­M­TR  1 PFC_4KW  PFC_4KW  L5  019­8598­00R  1 SI8230  SI8230  U7  SI8230BB­D­IS1  1 SI8233  SI8230  U6   SI8233BB­D­IS1    2 STY139N65M5  STY139N65M5  Q1, Q4  STY139N65M5  2 TP65H035G4WS  TP65H035G4WS  Q2, Q3  TP65H035WS  1 TPS60403  TPS60403  U10  TPS60403DBVR  1 5V DC­DC converter  V7805­500  U3  TR05S05  1 DSPIC33CK256MP506 DIGITAL  POWER  DSPIC33CK256MP506 DIGITAL POWER Conn1  MA330048  11  stand off (nylon 1/2)  stand off (nylon 1/2)  11  machine screw (ss 1/2)  machine screw (ss 1/2)  4 Thermal pad for Q2, Q3, Q1, Q4  Thermal pad for Q2, Q3, Q1, Q4  Thermal pad for Q2,  Q3, Q1, Q4  4169G  2 screws for FETs to HS (Q2, Q3)  screws for FETs to HS (Q2, Q3)  screws for FETs to  HS (Q2, Q3)  6/32  February 06, 2020 evk0010.1 stand off (nylon  1/2)  machine screw (ss  1/2)  1902C   9902  © 2020 Transphorm Inc. Subject to change without notice. 10 ` TDTTP4000W066C_0V1 User Guide For this evaluation board, the PFC circuit has been implemented on a 4-layer PCB. The GaN FET half-bridge is built with TP65H035WSG4 (0.035 ohm) devices by Transphorm, Inc. The slow Si switches are STY139N65M5 super junction MOSFETs with 0.017 ohm on-resistance. The inductor is made of a High Flux core with the inductance of 480 uH and a dc resistance of 0.025 Ohm, designed to operate at 66 kHz. A simple 0.5 A rated high/low side driver IC (Si8230) with 0/12 V as on/off states directly drives each GaN FETs. A dsPIC33CK256MP506 Digital Power PIM MA330048 handles the control algorithm. The voltage and current loop controls are similar to conventional boost PFC converter. The feedback signals are dc output voltage (VO), ac input potentials (VACP and VACN) and inductor current (IL). The input voltage polarity and RMS value are determined from VACP and VACN. The outer voltage loop output multiplied by |V AC| gives a sinusoidal current reference. The current loop gives the proper duty ratio for the boost circuit. The polarity determines how PWM signal is distributed to drive Q1 and Q2. A soft-start sequence with a duty ratio ramp is employed for a short period at each ac zero-crossing for better stability. (a) PCB top layer February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 11 ` TDTTP4000W066C_0V1 User Guide (b) PCB bottom layer February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 12 TDTTP4000W066C_0V1 User Guide ` (c) PCB inner layer 2 (ground plane) + inner layer 3 (power plane) Figure 9. PCB layers Using the board The board can be used for evaluation of Transphorm GaN 0.035 ohm FETs in a Bridge-less totem-pole PFC circuit. It is not a complete circuit, but rather a building block. Turn on Sequences: 1) Connect an Electronic / resistive load to the corresponding marking (CN2). The requirement for the resistive load: 2) Connect the 12 Vdc auxiliary supply to the demo-board (included in the demo-kit package). - Verify auxiliary LED is on. - Verify both FANS attached to heatsink are running 3) With HV power off, connect the high-voltage AC power input to the corresponding marking (CN1) on the PCB; February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 13 TDTTP4000W066C_0V1 User Guide ` -N and L (PE: potential ground) 4) Turn on the AC power input (85 Vac to 265 Vac; 50 60Hz) a. Minimum power load for turn-on sequence is 350W. Monitor CN2 output voltage with Vdc meter to verify 385V +/- 5V is generated. b. Electronic / resistive load can be increased while AC supply is ON and board is functional. Turn off sequences: 1) Switch off the high­voltage AC power input;   2) Power off dc bias.   3) Verify Input and Output voltage = 0.  Operational Waveforms Fig 10 below shows the converter start-up procedure: CH1 shows the DC input current; CH2 is the DC bus voltage waveform and CH3 is the voltage waveform of fast leg switching node. For the start-up, there are three phases to charge the DC bus to a reference voltage. In the beginning, the relay K1 is open, and DC bus capacitors are charged by input voltage through NTC and diode bridge. When the Vdc is over 100V, the relay K1 is closed to bypass the NTC, and the Vdc increase to the peak of the input voltage. After 100ms, the GaN FETs leg is engaged in voltage closed-loop control, in which the DC bus voltage reference slowly increases to the rated voltage 385V. The NTC and diode bridge are applied in this circuit to avoid high inrush current flow through the GaN FETs February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 14 TDTTP4000W066C_0V1 User Guide ` Fig 10. Start-up of the Bridge-less totem-pole PFC (CH1: Iin, Ch2: Vo, CH3: Vds) with 1.2kW load Fig 11. Waveform of the active switch version of the Bridge-less totem-pole PFC at low line, 3.5kW at high line; (a) CH1: input current Iin (10A/div) ; CH4: (a) Vgs of Q2 (5V/div), (b) Vds of Q2 (100V/div) February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 15 TDTTP4000W066C_0V1 User Guide ` Fig 12 below shows the turn on and turn off Vgs waveforms at iL = 23A. There is no voltage overshoot at turn-on. Turn-off voltage bump is caused by the Rg. The detailed description of the driver can be referred to application note AN0004 (Transphormusa.com). Fig 12 waveforms of Vgs of Q2 at iL = 23A. CH1: input current Iin (10A/div) ; CH4: (a) Vgs of Q2 (5V/div) Fig 13 below shows the Vds of Q2 at 3.5k. It can be seen that the voltage spike is 56V at iL = 20A. In this circuit, the RC snubber and Rg help to reduce voltage spikes. Fig 13. Waveforms of Vds of Q2 at iL = 20A. CH1: input current Iin (10A/div) ; CH4: (a) Vds (100V/div) Fig 14 below shows the transition between two half cycles. In Fig 14 (a), the AC line enters the negative half. Soft-start gradually increases voltage VD from 0V to 385V. While in Fig 12 (b), V D decreases from 385V to 0V. February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 16 TDTTP4000W066C_0V1 User Guide ` Fig 14 Zero-crossing transitional waveform (a) from negative to positive half-cycle (b) from positive to negative half-cycle. CH1: PW< Gate Signal for SD2; CH2: iL waveform; CH3: V D waveform. Probing As shown in Fig 15 below, in the demo board, there are two probing sockets for customers measuring Vgs and Vds of low-side Gan FET. By removing the jumpers and using a short wire to clamp the current probe, the PFC inductor can also be measured. February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 17 TDTTP4000W066C_0V1 User Guide ` Fig 15. Vgs and Vds of low side GaN FET measurement socket tips, and PFC inductor current measuring position. February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 18 ` TDTTP4000W066C_0V1 User Guide Efficiency Sweep and EMI For the efficiency measurement, the input/output voltage and current will be measured for the input/output power calculation with a power analyzer. Efficiency has been measured at 120 Vac or 230 Vac input and 400 Vdc output using the WT1800 precision power analyzer from Yokogawa. The efficiency results for this Totem Pole PFC board are shown in Fig.16. The extremely high efficiency of 99% at 230Vac input, and > 98% at 120V ac input is the highest among PFC designs with similar PWM frequency; this high efficiency will enable customers to reach peak system efficiency to meet and exceed Titanium standards. Figure 16. The efficiency results for Bridge-less Totem-pole PFC Evaluation Board. Conducted emissions have also been measured for this board using an LIN-115A LISN by Com-Power. The results compared to EN55022A limits are shown in Fig. 17. It should be noted that the EMI test was done by using the lab-use power supply for auxiliary 12V source. Do not use wall AC-DC adaptor for EMI test. February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 19 ` TDTTP4000W066C_0V1 User Guide Fig 17. Conducted emissions @ 115V, 1150W The THDi is measured using WT1800 at the condition of input THDv 3.8%. As shown in Fig 18 below, it meets the standard of IEC61000-3-12. THDi sweep (THDv 16A) Maximum Load Limit: The TDTTP4000W066C Bridge-less totem-pole PFC eval board is allowed to run overload in a short time. The rated input current for < 230Vac input is 18A, and the 10% overload current can be 19.8A. The input OCP will be triggered when the current is over 21A. February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 20 ` TDTTP4000W066C_0V1 User Guide WARNINGS: This demo board is intended to demonstrate GaN FET technology. While it provides the main features of a totem-pole PFC, it is not intended to be a finished product and does not have all the protection features found in commercial power supplies. Along with this explanation go a few warnings which should be kept in mind: 1. An isolated AC source should be used as input; an isolated lab bench grade power supply or the included AUX DC supply should also be used for the 12V DC power supply. Float the oscilloscope by using an isolated oscilloscope or by disabling the PE (Protective Earth) pin in the power plug. Float the current probe power supply (if any) by disabling the PE pin in the power plug. 2. Use a resistive load only. The Totem-pole PFC kit can work at zero load with burst mode. The output voltage will be swinging between 375V and 385V during burst mode. 3. The demo board is not fully tested at large load steps. DO NOT apply a very large step in the load (>2000W) when it is running. 4. DO NOT manually probe the waveforms when the demo is running. Set up probing before powering up the demo board. 5. The auxiliary Vdc supply must be 12 V. The demo board will not work under, for example, 10 V or over 15V Vdc. 6. DO NOT touch any part of the demo board when it is running. 7. When plugging the control cards into the socket, make sure the control cards are fully pushed down with a clicking sound. 8. If the demo circuit goes into protection mode it will work as a diode bridge by shutting down all PWM functions. Recycle the bias power supply to reset the DSP and exit protection mode. 9. DO NOT use a passive probe to measure control circuit signals and power circuit signals in the same time. GND1 and AGND are not the same ground. 10. To get clean Vgs of low side GaN FET, it is recommended not to measure the Vds at the same time. 11. It is not recommended using passive voltage probe for Vds, Vgs measurement and using differential voltage probe for Vin measure measurement at the same time unless the differential probe has very good dv/dt immunity. REFERENCE: [1]. Liang Zhou, Yi-Feng Wu and U -less Totem- - 16 May, 2013, pp.1017-1022. February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 21 ` TDTTP4000W066C_0V1 User Guide Bridge- Power Electronics, Vol. 23, No. 3, pp. 1381-1390, May 2008. February 06, 2020 evk0010.1 © 2020 Transphorm Inc. Subject to change without notice. 22