VR9FU1G6428JBHMBT

DDR4 NON-ECC SOUDIMM VR9FUxx64x8xxx The Viking DDR4 SOUDIMM memory module offers lower operating voltages, higher module densities and faster speed categories than the prior DDR3 generation. JEDEC DDR4 (JESD79-4) has been defined to provide higher performance, with improved reliability and reduced power, thereby representing a significant achievement relative to previous DRAM memory technologies. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 1 of 42 vikingtechnology.com REVISION HISTORY Revision A B C Release Date 4/29/15 5/13/15 10/27/2016 Description of Change Initial release Revise block diagram Revise logo and color scheme. Change company address. (10/27/2016) Add 16GB PN’s. Change VDD SPD can be from 2.2V to 3.6V (2/22/2017) Datasheet PS9FUxx64x8xxx Revision C Checked By (Full Name) Varadharajan Natarajan Chanhee Park 2/22/2017 Viking Technology Page 2 of 42 vikingtechnology.com Legal Information Legal Information Copyright© 2017 Sanmina Corporation. All rights reserved. The information in this document is proprietary and confidential to Sanmina Corporation. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Sanmina. Sanmina reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of Sanmina to provide notification of such revision or change. Sanmina provides this documentation without warranty, term or condition of any kind, either expressed or implied, including, but not limited to, expressed and implied warranties of merchantability, fitness for a particular purpose, and noninfringement. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. In no event will Sanmina be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. Sanmina may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. Sanmina, Viking Technology, Viking Modular Solutions, and the Viking logo are trademarks of Sanmina Corporation. Other company, product or service names mentioned herein may be trademarks or service marks of their respective owners. STATEMENT OF COMPLIANCE Viking Technology, Sanmina Corporation ("Viking") shall use commercially reasonable efforts to provide components, parts, materials, products and processes to Customer that do not contain: (i) lead, mercury, hexavalent chromium, polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE) above 0.1% by weight in homogeneous material or (ii) cadmium above 0.01% by weight of homogeneous material, except as provided in any exemption(s) from RoHS requirements (including the most current version of the "Annex" to Directive 2002/95/EC of 27 January, 2003), as codified in the specific laws of the EU member countries. Viking strives to obtain appropriate contractual protections from its suppliers in connection with the RoHS Directives. All printed circuit boards (PCBs) have a flammability rating of UL94V-0. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 3 of 42 vikingtechnology.com 260 pin Ordering Information and Module Configuration Viking Part Number Voltage Capacity Module Configuration 512Mx64 512Mx64 512Mx64 1Gx64 1Gx64 1Gx64 1Gx64 1Gx64 1Gx64 2Gx64 2Gx64 2Gx64 4Gx64 4Gx64 4Gx64 Device Configuration 512Mx8 (8) 512Mx8 (8) 512Mx8 (8) 512Mx8 (16) 512Mx8 (16) 512Mx8 (16) 1024Mx8 (8) 1024Mx8 (8) 1024Mx8 (8) 1024Mx8 (16) 1024Mx8 (16) 1024Mx8 (16) 2048Mx8 (16) 2048Mx8 (16) 2048Mx8 (16) Device Package Ranks Speed VR9FU126428HBGyz 1.2V 4GB 4Gb FBGA 1 DDR4-14900 VR9FU126428HBHyz 1.2V 4GB 4Gb FBGA 1 DDR4-17000 VR9FU126428HBJyz1 1.2V 4GB 4Gb FBGA 1 DDR4-19200 VR9FU1G6428HBGyz 1.2V 8GB 4Gb FBGA 2 DDR4-14900 VR9FU1G6428HBHyz 1.2V 8GB 4Gb FBGA 2 DDR4-17000 VR9FU1G6428HBJyz1 1.2V 8GB 4Gb FBGA 2 DDR4-19200 VR9FU1G6428JBGyz1 1.2V 8GB 8Gb FBGA 1 DDR4-14900 VR9FU1G6428JBHyz1 1.2V 8GB 8Gb FBGA 1 DDR4-17000 VR9FU1G6428JBJyz1 1.2V 8GB 8Gb FBGA 1 DDR4-19200 VR9FU2G6428JBGyz1 1.2V 16GB 8Gb FBGA 2 DDR4-14900 VR9FU2G6428JBHyz1 1.2V 16GB 8Gb FBGA 2 DDR4-17000 1 VR9FU2G6428JBJyz 1.2V 16GB 8Gb FBGA 2 DDR4-19200 VR9FU4G6428JEGyz1 1.2V 32GB 16Gb FBGA 2 DDR4-14900 VR9FU4G6428JEHyz1 1.2V 32GB 16Gb FBGA 2 DDR4-17000 VR9FU4G6428JEJyz1 1.2V 32GB 16Gb FBGA 2 DDR4-19200 Notes:  For part numbers containing a lowercase x, contact Viking for the full PN.  The lowercase letters y and z are wildcard characters that indicate DRAM vendor and die revisions and /or for customer specific locked BOMs. Refer to the Viking part number coversheet for details. Datasheet PS9FUxx64x8xxx Revision C CAS Latency CL13 (13-13-13) CL15 (15-15-15) CL17 (17-17-17) CL13 (13-13-13) CL15 (15-15-15) CL17 (17-17-17) CL13 (13-13-13) CL15 (15-15-15) CL17 (17-17-17) CL13 (13-13-13) CL15 (15-15-15) CL17 (17-17-17) CL13 (13-13-13) CL15 (15-15-15) CL17 (17-17-17) 2/22/2017 Viking Technology Page 4 of 42 vikingtechnology.com Features  JEDEC Standard Power Supply o VDD = VDDQ = 1.2V± 5% (1.14V-1.26V) o External VPP = 2.5 Volt +10%, -5% o VDDSPD = 2.2V to 3.6V Volts  260 pin Small Outline Dual-In-Line Memory Module  Edge finger connector ramp zone to reduce insertion force  Point-to-Point topology to reduce loading  Pseudo-open drain (POD12) DQ lines  Internally generated VrefDQ  On-chip CA Parity detection for the command/address bus  Programmable CAS Latency: 13, 15,17  Programmable CAS Write Latency (CWL).  Programmable Additive Latency (Posted CAS)  Per DRAM addressability is supported  Data Bus Inversion support for x8 devices  Selectable Fixed burst chop (BC4) of 4 and burst length (BL8) of 8 on-the-fly (OTF) via the mode register set (MRS)  8n prefetch with 2 or 4 selectable bank groups: 16 banks (4 bank groups x 4 banks per bank group)  Separate activation, read, write, refresh operations for each bank group  7 mode registers  Dynamic On-Die-Termination (ODT) and ODT Park for improved signal integrity.  Self Refresh and several Power Down Modes  DLL-off mode for power savings  System Level Timing Calibration Support via Write Leveling and Multi Purpose Register (MPR) Read Pattern  Serial Presence Detect with EEPROM  Two On-DIMM Thermal Sensors  Asynchronous Reset  Bidirectional Differentially Buffered Data Strobes(DQS)  SOUDIMM dimensions per JEDEC MO-310 maximum limits  RoHS Compliant DDR4 SPEED BIN Nomenclature Module Standard DDR4-14900 DDR4-17000 1 DDR4-19200 1 DDR4-21300 1 DDR4-25600 SDRAM Standard DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2667 DDR4-3200 Clock 933 MHz 1066 MHz 1200 MHz 1333 MHz 1600 MHz Notes: 1. Contact Viking for availability date DDR4 Timing Summary MT/s tCK (ns) CAS Latency (tCK) tRCD (ns) tRP (ns) tRAS (ns) tRC (ns) CL-tRCDtRP DDR4-1866 1.071 13 13.92 13.92 34 47.92 13-13-13 DDR4-2133 0.93 15 14.06 14.06 33 47.05 15-15-15 DDR4-2400 0.83 17 14.16 14.16 32 46.16 17-17-17 Notes:  CL = CAS Latency, tRCD = Activate –to-Command Time, tRP = Precharge Time. Refer to Speed Bin tables for details. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 5 of 42 vikingtechnology.com Addressing 4GB(1Rx8) 512Mx8 DRAM 8GB(1Rx8) 1024Mx8 DRAM 16GB(2Rx8) 1024Mx8 DRAM 4 4 4 BG Address BG0~BG1 BG0~BG1 BG0~BG1 Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1 Row Address A0~A14 64K:A0~A15 64K:A0~A15 Column Address A0~ A9 A0~ A9 A0~ A9 512B 512B 512B 4K 8K 8K # of Bank Groups Bank Address Page size Refresh Count Note:  Micron datasheet specified 512B / 1KB as page size with “Die revision dependant”.  In Hynix and Samsung Datasheet specfies 512B for x4 Device. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 6 of 42 vikingtechnology.com DDR4 260-pin SOUDIMM Pin Wiring Assignments/Configurations Pin# 1 2 3 4 5 6 7 Symbol VSS VSS DQ5 DQ4 VSS VSS DQ1 Pin# 45 46 47 48 49 50 51 Symbol DQ21 DQ20 VSS VSS DQ17 DQ16 VSS Pin# 89 90 91 92 93 94 95 Pin# 133 134 135 136 137 138 139 Symbol A1 EVENT_n VDD VDD CK0_t CK1_t CK0_c Pin# 177 178 179 180 181 182 183 Symbol DQS4_c DM4_n/DBI4_n DQS4_t VSS VSS DQ39 DQ38 Pin# 221 222 223 224 225 226 227 Symbol DQS6_t VSS VSS DQ54 DQ55 VSS VSS 96 97 98 99 100 101 102 103 104 105 106 107 108 Symbol VSS VSS CB1, NC CB0, NC VSS VSS DQS8_c DM8_n, DBI8_n, NC DQS8_t VSS VSS CB6, NC CB2, NC VSS VSS CB7, NC CB3, NC VSS VSS RESET_n 8 9 10 11 12 13 14 15 16 17 18 19 20 DQ0 VSS VSS DQS0_c DM0_n/DBI0_n DQS0_t VSS VSS DQ6 DQ7 VSS VSS DQ2 52 53 54 55 56 57 58 59 60 61 62 63 64 VSS DQS2_c DM2_n/DBI2_n DQS2_t VSS VSS DQ22 DQ23 VSS VSS DQ18 DQ19 VSS 140 141 142 143 144 145 146 147 148 149 150 151 152 CK1_c VDD VDD PARITY A0 BA1 A10_AP VDD VDD CS0_n BA0 WE_n/A14 RAS_n/A16 184 185 186 187 188 189 190 191 192 193 194 195 196 VSS VSS DQ35 DQ34 VSS VSS DQ45 DQ44 VSS VSS DQ41 DQ40 VSS 228 229 230 231 232 233 234 235 236 237 238 239 240 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 CKE0 CKE1 VDD VDD BG1 ACT_n BG0 ALERT_n VDD VDD A12 A11 A9 A7 VDD VDD A8 A5 A6 A4 VDD VDD A3 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 VDD VDD ODT0 A15/CAS_n CS1_n A13 VDD VDD ODT1 C0/CS2_n/NC VDD VREFCA C1/CS3_n/NC 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 VSS DQS5_c DM5_n/DBI5_n DQS5_t VSS VSS DQ46 DQ47 VSS VSS DQ42 DQ43 VSS VSS DQ52 DQ53 VSS VSS DQ49 DQ48 VSS VSS DQS6_c DM6_n, DBI6_n, NC 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 DQ50 DQ51 VSS VSS DQ60 DQ61 VSS VSS DQ57 DQ56 VSS VSS DQS7_c DM7_n, DBI7_n, NC DQS7_t VSS VSS DQ62 DQ63 VSS VSS DQ58 DQ59 VSS VSS SCL SDA VDDSPD SA0 VPP VTT VPP SA1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DQ3 VSS VSS DQ12 DQ13 VSS VSS DQ8 DQ9 VSS VSS DQS1_c, DM1_n/DBI1_n DQS1_t VSS VSS DQ15 DQ14 VSS VSS DQ10 DQ11 VSS 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 VSS DQ28 DQ29 VSS VSS DQ24 DQ25 VSS VSS DQS3_c DM3_n/DBI3_n DQS3_t VSS VSS DQ30 DQ31 VSS VSS DQ26 DQ27 VSS VSS CB5, NC SA2 VSS VSS DQ37 DQ36 VSS VSS DQ33 DQ32 VSS 44 VSS 88 CB4, NC 132 A2 176 VSS 220 Notes:  VPP is 2.5V DC  A15 needed for 4GBit DRAM, A16 needed for 8GBit DRAM, A17 needed for 16GBit DRAM  Only x8 and x16 DRAM support Data Mask (DM) and Data Bus Inversion (DBI). Only x8 DRAM support TDQS  DM & DBI functions are supported with dedicated one pin labeled as DM_n/DBI_n  The pin is bi-directional pin for DRAM. The DM_n/DBI _n pin is Active Low as DDR4 supports VDDQ reference termination.  DM & DBI functions are programmable through DRAM Mode Register (MR). The MR bit location is bit A11 in MR1 and bit A12:A10 in MR5 . Write operation: Either DM or DBI function can be enabled but both functions cannot be enabled simultaneously. When both DM and DBI functions are disabled, DRAM turns off its input receiver and does not expect any Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 7 of 42 vikingtechnology.com valid logic level. Read operation: Only DBI function applies. When DBI function is disabled, DRAM turns off its output driver and does not drive any valid logic level. DM & DBI functions are described in more detail on x8 based datasheets PIN FUNCTION DESCRIPTION Pin Name A0-A17' Register address input SCL BA0, BA1 Register bank select input SDA BG0, BG1 Register bank group select input SA0-SA2 RAS_n Register row address strobe input PAR Description I2C serial bus clock for SPD/TS and register I2C serial bus data line for SPD/TS and register I2C slave address select for SPD/TS and register Register parity input CAS_n3 Register column address strobe input VDD SDRAM core power supply VREFCA SDRAM command/address reference supply VSS Power supply return (ground) 2 4 WE_n CS0_n, CS1_n, CS2_n, CS3_n CKE0, CKE1 Description Pin Name Register write enable input DIMM Rank Select Lines input Register clock enable lines input ACT_n Register on-die termination control lines input Register input for activate input VDDSPD Serial SPDrTS positive power supply DQ0-DQ63 DIMM memory data bus ALERT_n Register ALERT_n output CB0-CB7 DIMM ECC check bits Data Buffer data strobes (positive line of differential pair) Data Buffer data strobes (negative line of differential pair) Vpp DRAM Activation Power Supply ODT0, ODT1 TDQS9_t-TDQS17_t TDQS9_c- TDQS17_c RESET_n EVENT_n CK0_t, CK1_t CK0_c, CK1_c Register clock input (positive line of differential pair) Register clocks input (negative line of differential pair) Vtt RFU Set Register and SDRAMs to a Known state SPD signals a thermal event has occurred. SDRAM I/O termination supply Reserved for future use Notes: 1. Address A17 is only valid for 16GBit DRAM 2. RAS_n is a multiplexed function with A16. (A16 needed for 8GBit DRAM) 3. CAS_n is a multiplexed function with A15. (A15 needed for 4GBit DRAM) 4. WE_n is a multiplexed function with A14 Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 8 of 42 vikingtechnology.com Input/Output Functional Descriptions Symbol Type CK_t, CK_c Input CKE0, (CKE1) Input CS0_n, (CS1_n) Input C0,C1,C2 Input ODT0, (ODT1) Input ACT_n Input RAS_n/A16, CAS_n/A15, WE_n/A14 Input DM_n/DBI_n/ TDQS_t, (DMU_n/DBIU_n), (DML_n/DBIL_n) Input/ Output BG0 - BG1 Input Function Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c. Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK_c, ODT and CKE, are disabled during powerdown. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection on systems with multiple Ranks. CS_n is considered part of the command code. Chip ID: Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of stacked component. Chip ID is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/TDQS_t,NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ, DQSU_c, DQSU_t, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM. Activation Command Input: ACT_n defines the Activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14. Command Inputs RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered. Those pins have multi function. For example, for activation with ACT_n Low, those are Addressing like A16,A15 and A14 but for non-activation command with ACT_n High, those are Command pins for Read, Write and other command defined in command truth table. Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is masked when DM_n is sampled LOW coincident with that input data during a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function by Mode Register A10,A11,A12 setting in MR5. For x8 device, the function of DM or TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifying whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only supported in x8. Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. x4/8 have BG0 and BG1 but x16 has only BG0. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 9 of 42 vikingtechnology.com Input/Output Functional Descriptions (cont.) Symbol Type Function BA0 - BA1 Input Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. Input Address Inputs: Provided the row address for ACTIVATE Commands and the column address for Read/Write commands th select one location out of the memory array in the respective bank. (A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions, see other rows. The address inputs also provide the op-code during Mode Register Set commands. A17 is only defined for the x4 configuration. A10 / AP Input Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC_n Input Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. RESET_n Input Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail to rail signal with DC high and low at 80% and 20% of V DD. DQ Input / Output Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific datasheets to determine which DQ is used. Input / Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t, and DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended. A0 - A17 DQS_t, DQS_c, DQSU_t, DQSU_c, DQSL_t, DQSL_c Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 10 of 42 vikingtechnology.com Input/Output Functional Descriptions (cont.) Symbol ALERT_n TEN Type Function Output Alert: It has multi functions such as CRC error flag, Command and Address Parity error flag. If there is error in CRC, then Alert_n goes LOW for the period time interval and goes back HIGH. IF there is error in Command Address Parity Check, then Alert_n goes LOW for relatively long period until on going DRAM internal recovery transaction to complete. Input Boundary Scan Mode Enable: Required on x16 devices and optional input on x4/x8 with densities equal to or greater than 8Gb. HIGH in this pin will enable boundary scan operation along with other pins. It is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD. NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.2 V +/- 0.06 V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.2 V +/- 0.06 V VSS Supply Ground Vpp Supply DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max) VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ calibration Note: The input only pins (BG0-BG-1, BA0-BA1, A0-A17, ACT_n, RAS_n,/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supply termination. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 11 of 42 vikingtechnology.com MECHANICAL OUTLINE PHYSICAL LAYOUT, SINGLE RANK, 260 pin Notes:  All dimensions in mm (inches)  Tolerance is +/- 0.0127, unless otherwise stated  Refer to JEDEC Standard Mechanical Outline MO-310 for other details Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 12 of 42 vikingtechnology.com PHYSICAL LAYOUT, DUAL RANK, 260 pin Notes:  All dimensions in mm (inches)  Tolerance is +/- 0.0127, unless otherwise stated  Refer to JEDEC Standard Mechanical Outline MO-310 for other details Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 13 of 42 vikingtechnology.com FUNCTIONAL BLOCK DIAGRAM Data and Strobe DQs, DM, DQS_t, DQS_c Data and Strobe DQs, DM, DQS_t, DQS_c Command/Address/Clock Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 14 of 42 vikingtechnology.com Notes:  The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output driver. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 15 of 42 vikingtechnology.com DQ Internal Vref Specifications Parameter Vref Max operating point Range 1 Vref Min operating point Range 1 Vref Max operating point Range 2 Vref Min operating point Range 2 Vref Stepsize Vref Set Tolerance Vref Step Time Vref VaIid tolerance Symbol Min Typ Max Unit NOTE Vref_max_R1 - - 92% VDDQ 1, 11 Vref_min_R1 60% - - VDDQ 1,11 Vref_max_R2 - - 77% VDDQ 1, 11 0.65% 0.00% 0.00% 0.00% 0.80% 1.63% 0.15% 150 60 0.15% VDDQ VDDQ VDDQ VDDQ ns ns VDDQ 1,11 2 3,4,6 3,5,7 9 8 10 Vref_min_R2 Vref_step Vref_set_tol 45% 0.50% -1 .625% -0.15% Vref_time-long Vref_time-Short Vref_val_tol -0.15% Notes: 1. JESD8-24 specifies Vref to be 70% of VDDQ. Vref DC voltage referenced to VDDQ_DC. VDDQ_DC is 1.2V 2. Vref stepsize increment/decrement range. Vref at DC level. 3. Vref_new = Vref_old+n*Vref_step; n=number of step; if increment use “+”; If decrement use “-” 4. The minimum value of Vref setting tolerance=Vref_new-1.625%*VDDQ. The maximum value of Vref setting tolerance=Vref_new+1.625%*VDDQ. For n>4 5. The maximum value of Vref setting tolerance=Vref_new-0.15%*VDDQ. The maximum value of Vref setting tolerance=Vref_new+0.15%*VDDQ. For n&4 tbd 6. Measured by recording the min and max values of the Vref output over the range, drawing a straight line between those points and comparing all other Vref output settings to that line 7. Measured by recording the min and max values of the Vref output across 4 consecutive steps(n=4), drawing a straight line between those points and comparing all other Vref output settings to that line 8. Time from MRS command to increment of decrement one step size for Vref 9. Time from MRS command to increment of decrement more than one step size up to full range of Vref 10. Only applicable for DRAM component level test/characterization purpose. Not applicable for normal mode of operation. Vref valid is to qualify the step times which will be characterized at the component level. 11. DRAM range1 or 2 set by MRS bit MR6,A6. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 16 of 42 vikingtechnology.com OVERVIEW OF DDR4 SOUDIMM MODULE OPERATION The DDR4 architecture is generally a point-to-point topology with a dedicated channel design. The highest system performance levels can be achieved with DDR4-2133 and beyond, when the system is configured as 1 SOUDIMM Per Channel (1DPC). DDR4 has more features than DDR3 with a pseudo-open drain (POD12) 1.2v I/O for the data channel, trained Vref, bank groups and write CRC. The POD12 interface only applies to the data channel. The address command channel behave like DDR3 using mid-point termination and mid-point Vref. The new bank group interleaving feature in DDR4 maximizes data transfer bandwidth. DDR4 DRAM use pseudo-open drain (POD12) 1.2v drivers with Vdd terminations on DQ lines to increase data rates; unlike DDR3 DRAM that uses stub-series terminated logic drivers, The DRAM addressing scheme in DDR4 is organized into bank groups, Side A and Side B. The host DDR4 memory controller interleaves (multiplexes) among the bank groups to achieve high data rates. DDR4 architecture is a 8n prefetch with bank groups, including the use of two or four selectable bank groups. This will permit the DDR4 memory devices to have separate activation, read, write or refresh operations simultaneously underway in each of the unique bank groups to improve overall memory efficiency and bandwidth, especially when small memory granularities are used. The data written to the SOUDIMM is read back the same way. However when writing to the internal registers with a "load mode" operation, a specific address is required. This requires the controller to know if the rank is mirrored or not. There is a bit assignment in the SPD that indicates whether the module has been designed with a mirrored feature or not. DDR4 offers CRC parity as an optional feature on address command and data; (Error command blocking when parity enabled and post CA parity. If the SOUDIMM does not support CRC, the values of 0x00 will fill the CRC table. The new CA parity feature on the command/address bus provides a low-cost method of verifying the integrity of command and address transfers over a link, for all operations. Some of the main attributes of DDR4 memory are: 1) Internally generated VrefDQ and Calibration. VrefDQ is supplied by the DRAM internally. VrefCA is supplied by the board. 2) The ACT_n activate pin replaces RAS#, CAS#, and WE# commands, 3) Alert_n for error checking 4) Bank group Interleaving 5) Improved training modes upon power-up 5) Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin 6) DQ bus geardown mode for 2667 Mhz data rates and beyond 7) External VPP at 2.5V (for wordline boost) 8) 1.2V VDD power with power-saving features that include MPSM Maximum Power Savings Mode, Low Power Auto Self Refresh, Temperature Controlled Refresh, Fine Granularity Refresh, and CMD/ADDT latency. DLL off mode. Important Note: Longer boot-up times may be experienced in certain situations due to controller initiated functions such as VrefDQ calibration, write leveling and other trainings for the SOUDIMM. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 17 of 42 vikingtechnology.com DDR4 MODE REGISTERS A12 A11 MR0 RFU MR1 Qoff TDQS MR2 Write CRC RFU MR3 MPR Read Format MR4 MR5 MR6 Write Preamble Read DBI Enable A10 Write Recovery and RTP A8 A7 DLL Reset Test Mode Write Leveling Rtt_NOM Rtt_WR RFU Write CMD Latency with CRC and DM Read Preamble Read Preamble Training Enable Self Refresh Abort Enable Write DBI Enable Data Mask Enable Parity Persiste nt Error tCCD_L and tDLLK Timing MR7 A9 RFU A6 A5 A4 CAS Latency CL RFU RFU Auto Self Refresh A3 A2 Burst Type CL Additive Latency CWL A1 Burst Length BL RFU Temp Sensor PerDRAM Addr Mode Gear down MPR Enable CS-to-Address Latency CAL RFU VrefDQ Monitor Enable Temp Refresh Mode Temp. Refresh Range Rtt_PARK ODT input in Power Down Panty Error Status CRC Error Clear VrefDQ Training enable VrefDQ Training Range DLL Enable Ron Fine Granularity Refresh RFU A0 RFU RFU MPR Page Max Power Down Enable RFU CMD Address Parity Latency VretDQ Training Value Manufacturing use only to program the RCD Notes:  Refer to JEDEC documentation for detail of the control/status bits Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 18 of 42 vikingtechnology.com DC OPERATING CONDITIONS AND CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Notes Voltage on any pin relative to GND Vin, Vout -0.3 ~ 1.5 V 1, Voltage on VDD supply relative to GND VDD -0.3 ~ 1.5 V 1,3 Voltage on VDDQ supply relative to GND VDDQ -0.3 ~ 1.5 V 1,3 Voltage on VPP supply relative to GND VPP -0.3 ~ 3.0 V 4 1,5 Module operating temperature (ambient) Topr 0 ~ 55 C 1,2 Storage temperature Tstg -55 ~ +100 C Notes: 1. Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51- 2 standard. 3. VDD and VDDQ must be within 300 mV of each other at all times and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREF may be equal to or less than 300 mV 4. VPP must be equal or greater than VDD/VDDQ at all times 5. Refer to JEDEC JC451 specification DRAM Component Operating Temperature Range Symbol Toper Parameter Rating Units Note Normal Operating Temperature Range 0 to 85 °C 1,2 Extended Temperature Range 85 to 95 °C 1,3 Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the o DRAM case temperature must be maintained between 0 - 85 C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual SelfRefresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto SelfRefresh mode (MR2 A6 = 1b and MR2 A7 = 0b). DDR4 SDRAMs support Auto Self-Refresh and in Extended Temperature Range and please refer to component datasheet and/or the DIMM SPD for tREFI requirements in the Extended Temperature Range tREFI by Device Density Parameter Average periodic refresh interval Symbol 2Gb 4Gb 8Gb 16Gb Units 0°C ≤ Tcase ≤ 85°C 7.8 7.8 7.8 7.8 μs 85°C ≤ Tcase ≤ 95°C 3.9 3.9 3.9 3.9 μs tREFI Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 19 of 42 vikingtechnology.com AC & DC Operating Conditions DC OPERATING CONDITIONS AND CHARACTERISTICS (POD12) Symbol VDD Rating Parameter Supply Voltage VDD: PC4:1.2V±5%, VPP Supply Voltage for Output. Values in () are at 70% of VDD 2.5V +10%, -5% VDDSPD @2.5V VDDQ Units Notes Min Typ Max 1.14 1.2 1.26 v 1,2,3 1.14 (0.798) 1.2 (0.84) 1.26 (0.882) v 1 2.375 2.5 2.75 v 3 2.2 - 3.6 v Notes: 1. JESD8-24 specifies Vref to be 70% of VDDQ. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. DC bandwidth is limited to 20MHz., 4. PODI2 1.2 V Pseudo Open Drain Interface has a VDDQ value of 1.2V but the reference voltage allows PODI2 to be used with other VDDQ values. POD12 signals have pull-up-only parallel input termination and have an asymmetric output drive impedance. For example, if the output drivers were using a 60 ohm pull-up drive impedance then the pull-down drivers would be expected to produce a 40 ohm pull-down drive impedance. PODI2 does not explicitly call for series termination resistors, so it is suitable for point-to-point as well as multi-drop stub environments which may require some additional termination. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 20 of 42 vikingtechnology.com DC CHARACTERISTICS, IDD CURRENTS IDD DEFINITIONS Symbol Parameter IDD0 One bank ACTIVATE-PRECHARGE current IPP0 IDD1 IDD2N IDD2NT IDD2P IDD2Q One bank ACTIVATE-PRECHARGE, Word Line Boost, IPP current One bank ACTIVATE-READ-PRECHARGE current Precharge standby current Precharge standby ODT current Precharge power-down current Precharge quiet standby current IDD3N IPP3N IDD3P IDD4R IDDQ4R IDD4W Active standby current Active standby IPP current Active power-down current Burst read current Burst read IDDQ current Burst write current IDD5B IPP5B IDD6N IDD6E IDD6R IDD6A Burst refresh current (1x REF) Burst refresh IPP current (1 x REF) Self refresh current: Normal temperature range (0°C to +85°C) Self refresh current: Extended temperature range (0°C to +95°C) Self refresh current: Reduced temperature range (0°C to +45°C) Auto self refresh current (25°C) IDD6A Auto self refresh current (45°C) IDD6A Auto self refresh current (75°C) IDD7 Bank interleave read current IPP7 Bank interleave read IPP current IDD8 Maximum power-down current Notes: 1) DDR4 IDD and IDDQ specs include the same DDR3 IDD and IDDQ specs with these exceptions: a. IDD2P0 and IDD2P1 are replaced with a single IDD2P. There’s no longer any difference in power for the DLL because of better DLL power management inside the DRAM device without any benefit for using slow exit. b. IDD6 is renamed IDD6N Self Refresh Current: Normal Temperature Range c. IDD6ET is renamed IDD6E Self-Refresh Current: Extended Temperature Range d. IDD6TC is renamed IDD6AAut0 Self-Refresh Current e. IDD8 is redefined from (optional) RESET Low Current to IDD8 Maximum Power Down Current, TBD 2) IDD values are an average (not peak) current drawn throughout the entire time that it takes to execute the set of conditions specified by JEDEC standards. 3) Consult with Viking for tools to help specify the Total Design Power (TDP) Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 21 of 42 vikingtechnology.com IDD6 Specification Symbol IDD6N IDD6E IDD6R IDD6A Temperature Range o 0 - 85 C o 0 - 95 C o 0 - 45 C o 0 C ~ Ta Tb ~ Ty Tz ~ TOPERmax Value 22 33 10 9 10 16 Unit mA mA mA mA mA mA Notes 3,4 4,5,6 4,6,9 4,6,7,8 4,6,7,8 4,6,7,8 Notes: 1. Some IDD currents are higher for x16 organization due to larger page-size architecture. 2. Max. values for IDD currents considering worst case conditions of process, temperature and voltage. 3. Applicable for MR2 settings A6=0 and A7=0. 4. Supplier data sheets include a max value for IDD6. 5. Applicable for MR2 settings A6=0 and A7=1. IDD6ET is only specified for devices which support the Extended Temperature Range feature. 6. Refer to the supplier data sheet for the value specification method (e.g. max, typical) for IDD6ET and IDD6TC 7. Applicable for MR2 settings A6=1 and A7=0. IDD6TC is only specified for devices which support the Auto Self Refresh feature. 8. The number of discrete temperature ranges supported and the associated Ta - Tz values are supplier/design specific. Temperature ranges are specified for all supported values of TOPER. Refer to supplier data sheet for more information. 9. Applicable for MR2 settings TBD. IDD6R is verified by design and characterization, and may not be subject to production test. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 22 of 42 vikingtechnology.com IDD CURRENTS, SINGLE RANK, 4Gbit Symbol DDR4-1866 DDR4-2133 DDR4-2400 Units IDD0 IPP0 IDD1 IDD2N IDD2NT IDD2P IDD2Q IDD3N IPP3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IPP5B IDD6N IDD6E IDD6R IDD6A (25°C) IDD6A (45°C) IDD6A (75°C) IDD7 IPP7 IDD8 464 32 504 352 400 240 312 488 24 352 1120 256 1248 1520 176 160 216 80 72 80 128 1280 80 144 480 32 520 368 432 240 312 504 24 352 1200 288 1408 1520 176 160 216 80 72 80 128 1480 96 144 512 32 544 400 464 256 328 536 24 352 1280 320 1568 1536 176 160 216 80 72 80 128 1680 112 144 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Notes: 1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following options or requirements referred to in this material. 2. Values as per Micron Datasheet Revision “A”. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 23 of 42 vikingtechnology.com IDD CURRENTS, 2 RANK, 4Gbit Symbol 1 IDD0 IPP01 IDD11 IDD2N2 IDD2NT1 IDD2P2 IDD2Q2 IDD3N2 IPP3N2 IDD3P2 IDD4R1 IDDQ4R1 IDD4W1 IDD5B1 IPP5B1 IDD6N2 IDD6E2 IDD6R2 IDD6A2 (25°C) IDD6A2 (45°C) IDD6A2 (75°C) IDD71 IPP71 IDD82 DDR4-1866 DDR4-2133 DDR4-2400 Units 704 272 744 704 640 480 624 976 48 704 1360 496 1488 1760 416 320 432 160 144 160 256 1520 320 288 720 272 760 736 672 480 624 1008 48 704 1440 528 1648 1760 416 320 432 160 144 160 256 1720 336 288 768 288 800 800 720 512 656 1072 48 704 1536 576 1824 1792 432 320 432 160 144 160 256 1936 368 288 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Notes: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N. 2. All ranks in this IDD/PP condition. 3. Values as per Micron Datasheet Revision “A. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 24 of 42 vikingtechnology.com IDD CURRENTS, SINGLE RANK, 8Gbit Symbol IDD0 IDD0A IDD1 IDD1A IDD2N IDD2NA IDD2NT IDD2NL IDD2NG IDD2ND IDD2N_par IDD2P IDD2Q IDD3N IDD3NA IDD3P IDD4R IDD4RA IDD4RB IDD4W IDD4WA IDD4WB IDD4WC IDD4W_par IDD5B IDD5F2 IDD5F4 IDD6N IDD6E IDD7 IDD8 Notes: 1. 2. DDR4-2133 15-15-15 1.2V DDR4-2400 17-17-17 1.2V 280 296 400 416 176 200 200 176 160 184 128 160 288 296 312 424 448 184 208 208 136 184 168 192 128 168 288 304 304 168 824 856 840 672 704 752 592 736 1752 1232 1024 184 272 1360 88 176 904 944 928 720 760 720 640 792 1776 1240 1040 184 272 1384 88 120 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following options or requirements referred to in this material. Values as per Samsung Datasheet Revision “D”. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 25 of 42 vikingtechnology.com IDD CURRENTS, DUAL RANK, 8Gbit Symbol 1 IDD0 1 IDD0A 1 IDD1 1 IDD1A 2 IDD2N 1 IDD2NA 1 IDD2NT 1 IDD2NL 1 IDD2NG 1 IDD2ND 1 IDD2N_par 2 IDD2P 2 IDD2Q 2 IDD3N 2 IDD3NA 2 IDD3P 1 IDD4R 1 IDD4RA 1 IDD4RB 1 IDD4W 1 IDD4WA 1 IDD4WB 1 IDD4WC 1 IDD4W_par 1 IDD5B 1 IDD5F2 1 IDD5F4 2 IDD6N 2 IDD6E 1 IDD7 2 IDD8 DDR4-2133 15-15-15 1.2V DDR4-2400 17-17-17 1.2V 408 424 528 544 352 328 328 248 304 288 312 256 424 440 552 576 368 336 336 264 312 296 320 256 mA mA mA mA mA mA mA mA mA mA mA mA 320 576 336 576 608 608 336 952 984 968 800 832 880 720 864 1880 1360 1152 368 544 1488 176 352 1032 1072 1056 848 888 848 768 920 1904 1368 1168 368 544 1512 176 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Units Notes: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N. 2. All ranks in this IDD/PP condition. 3. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following options or requirements referred to in this material. 4. Values as per Samsung Datasheet Revision “D”. . Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 26 of 42 vikingtechnology.com IDD CURRENTS, DUAL RANK, 16Gbit DDR4-2133 15-15-15 1.2V Symbol 1 IDD0 1 IDD0A 1 IDD1 1 IDD1A 2 IDD2N 1 IDD2NA 1 IDD2NT 1 IDD2NL 1 IDD2NG 1 IDD2ND 1 IDD2N_par 2 IDD2P 2 IDD2Q 2 IDD3N 2 IDD3NA 2 IDD3P 1 IDD4R 1 IDD4RA 1 IDD4RB 1 IDD4W 1 IDD4WA 1 IDD4WB 1 IDD4WC 1 IDD4W_par 1 IDD5B 1 IDD5F2 1 IDD5F4 2 IDD6N 2 IDD6E 1 IDD7 2 IDD8 DDR4-2400 17-17-17 1.2V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Notes: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N. 2. All ranks in this IDD/PP condition. 3. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following options or requirements referred to in this material. 4. Values as per Samsung Datasheet Revision “D”. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 27 of 42 vikingtechnology.com Input/Output Capacitance Symbol Parameter DDR4-1600, 1867, 2133 DDR4-2400,2667 DDR4-3200 Min Max Min Max Min Max Units Note CIO Input/output capacitance 0.7 1.4 0.7 1.3 TBD TBD pF CDIO Input/output capacitance delta -0.1 0.1 -0.1 0.1 TBD TBD pF 1,2,3 1,2,3,1 1 CDDQS CCK Input/output capacitance delta DQS and DQS# Input capacitance, CK and CK# 0.2 0.05 0.8 0.2 0.05 0.8 TBD TBD TBD TBD pF pF 1,2,3,5 1,3 CDCK Input capacitance delta CK and CK# 0.05 TBD TBD pF 1,3,4 CI CDI_CTRL CDl_ADD_CMD CALERT CZQ Input capacitance(CTRL, ADD, CMD pins only) Input capacitance delta(All CTRL pins only) Input capacitance delta(All ADD/CMD pins only) lnput/output capacitance of ALERT Input/output capacitance of ZQ 0.05 0.2 0.8 0.2 0.7 TBD TBD pF 1,3,6 -0.1 0.1 -0.1 0.1 TBD TBD pF 1,3,7,8 -0.1 0.1 -0.1 0.1 TBD TBD pF 1,2,9, 10 0.5 0.5 1.5 1.5 0.5 0.5 1.5 1.5 TBD TBD TBD TBD pF pF 1,3 1,3,12 Notes: 1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is validated by de-embedding the package L & C parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all other signal pins floating. Measurement procedure tbd. 2. DQ, DM, DQS_T, DQS_C, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading matches DQ and DQS 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here. 4. Absolute value CK_T-CK_C 5. Absolute value of CIO(DQS_T)-CIO(DQS_C) 6. CI applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0-BG1, RAS_n, CAS_n, WE_n. 7. CDI CTRL applies to ODT, CS_n and CKE 8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C)) 9. CDI_ADD_ CMD applies to, A0-A17, BA0-BA1, BG0-BG1, RAS_n, CAS_n, WE_n. 10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C)) 11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_C)) 12. Maximum external load capacitance on ZQ pin: tbd pF DC and AC Specifications for the SMBus Interface The specifications for the SMBus follow JEDEC standards. Datasheet PS9FUxx64x8xxx Revision C 2/22/2017 Viking Technology Page 28 of 42 vikingtechnology.com Speed Bins by Speed Grade DDR4-1600 Speed Bins and Operating Conditions Speed Bin DDR4-1600 CL-nRCD-nRP 11-11-11 Parameter Symbol Min Unit NOTE Max 14 Internal read command to first data tAA 13.75 5,12 (13.50) 18 ns Internal read command to first data with read DBI enabled tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns ACT to internal read or write delay time tRCD 13.75 5,12 (13.50) - ns PRE command period tRP 13.75 5,12 (13.50) - ns ACT to PRE command period tRAS 35 9 x tREFI ns ACT to ACT or REF command period tRC 48.75 5,12 (48.50) - ns Normal Read DBI CL = 9 CL = 11 5 (Optional) tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 11 CL = 13 tCK(AVG) 1.25 CL = 12 CL = 14 tCK(AVG) 1.25 CWL = 9 CWL = 9,11 ns 1,2,3,4,11 ,14 ns 1,2,3,4,11 ns 1,2,3,4