VP9MR8G7224JLLSB

DDR4 (PC4) ECC RDIMM VP9MRxx72x4xxx Viking’s DDR4 RDIMM memory module offers lower operating voltages, higher module densities and faster speed categories than prior generation DDR3 memory. JEDEC DDR4 (JESD79-4) specification provides higher performance with improved reliability and reduced power, thereby representing a significant achievement relative to previous DRAM memory technologies. Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 1 of 46 Vikingtechnology.com REVISION HISTORY Revision X1 X2 Release Date 9/9/14 2/3/15 A B 4/2/15 5/28/15 C 9/22/15 D 5/12/16 E 3/16/17 F G H 5/2/17 7/11/17 8/2/17 Description of Change Preliminary Revise thickness to JEDEC spec. Add Idd values Initial release Update Block diagram , IDD values, IDC review update Update Single Rank Block diagram using 18 DRAM's and Dual Rank Block diagram using 36 DRAM's Add 4Gb based PN’s to module config and Idd values table per Samsung datasheet Add VP9MR4G7224JBK. Change logo and format. Add 2666 speed bin and timing Add 2666 PN’s and speed bin and timing Add VP9MR8G7224JLLSB change PN from xxxSB to xxxyz Datasheet PS9MRxx72x4xxx_VP Revision H Checked By (Full Name) IDC (9-9-14) IDC (9-11-14) IDC (3-16-15) IDC (5-28-15) IDC (9-16-15) IDC (5-16-16) 8/02/17 Viking Technology Page 2 of 46 Vikingtechnology.com Legal Information Legal Information Copyright© 2017 Sanmina Corporation. All rights reserved. The information in this document is proprietary and confidential to Sanmina Corporation. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Sanmina. Sanmina reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of Sanmina to provide notification of such revision or change. Sanmina provides this documentation without warranty, term or condition of any kind, either expressed or implied, including, but not limited to, expressed and implied warranties of merchantability, fitness for a particular purpose, and noninfringement. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. In no event will Sanmina be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. Sanmina may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. Sanmina, Viking Technology, Viking Modular Solutions, and the Viking logo are trademarks of Sanmina Corporation. Other company, product or service names mentioned herein may be trademarks or service marks of their respective owners. STATEMENT OF COMPLIANCE Viking Technology, Sanmina Corporation ("Viking") shall use commercially reasonable efforts to provide components, parts, materials, products and processes to Customer that do not contain: (i) lead, mercury, hexavalent chromium, polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE) above 0.1% by weight in homogeneous material or (ii) cadmium above 0.01% by weight of homogeneous material, except as provided in any exemption(s) from RoHS requirements (including the most current version of the "Annex" to Directive 2002/95/EC of 27 January, 2003), as codified in the specific laws of the EU member countries. Viking strives to obtain appropriate contractual protections from its suppliers in connection with the RoHS Directives. All printed circuit boards (PCBs) have a flammability rating of UL94V-0. Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 3 of 46 Vikingtechnology.com Ordering Information and Module Configuration 8GB Module Configuration 1Gx72 Device Configuration 1024Mx4 (18) 1.2V 8GB 1Gx72 1024Mx4 (18) VP9MR1G7224HBKyz 1.2V 8GB 1Gx72 1024Mx4 (18) VP9MR2G7224HBHyz 1.2V 16GB 2Gx72 1024Mx4 (36) VP9MR2G7224HBJyz 1.2V 16GB 2Gx72 1024Mx4 (36) VP9MR2G7224HBKyz 1.2V 16GB 2Gx72 1024Mx4 (36) VP9MR2G7224JBHyz 1.2V 16GB 2Gx72 2048Mx4 (18) VP9MR2G7224JBJyz 1.2V 16GB 2Gx72 2048Mx4 (18) VP9MR2G7224JBKyz 1.2V 16GB 2Gx72 2048Mx4 (18) VP9MR4G7224JBHyz 1.2V 32GB 4Gx72 2048Mx4 (36) VP9MR4G7224JBJyz 1.2V 32GB 4Gx72 2048Mx4 (36) VP9MR4G7224JBKyz 1.2V 32GB 4Gx72 2048Mx4 (36) Viking Part Number Voltage Capacity VP9MR1G7224HBHyz 1.2V VP9MR1G7224HBJyz Device Package 4Gb FBGA 4Gb FBGA 4Gb FBGA 4Gb FBGA 4Gb FBGA 4Gb FBGA 8Gb FBGA 8Gb FBGA 8Gb FBGA 8Gb FBGA 8Gb FBGA 8Gb FBGA 2H TSV DIMM Rank 1 PC4-17000 CL15 (15-15-15) 1 PC4-19200 CL17 (17-17-17) 1 PC4-21300 CL19 (19-19-19) 2 PC4-17000 CL15 (15-15-15) 2 PC4-19200 CL17 (17-17-17) 2 PC4-21300 CL19 (19-19-19) 1 PC4-17000 CL15 (15-15-15) 1 PC4-19200 CL17 (17-17-17) 1 PC4-21300 CL19 (19-19-19) 2 PC4-17000 CL15 (15-15-15) 2 PC4-19000 CL17 (17-17-17) 2 PC4-21300 CL19 (19-19-19) Speed CAS Latency VP9MR8G7224JLLyz 1.2V 64GB 8Gx72 (4Gx4)x36 2 PC4-21300 CL19 (19-19-19) Notes:  The lowercase letters y and z are wildcard characters that indicate DRAM vendor and die revisions and /or for customer specific locked BOMs. Refer to the Viking part number coversheet for details. Contact Viking for availability date Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 4 of 46 Vikingtechnology.com Features  JEDEC Standard Power Supply o PC4: VDD = VDDQ = 1.2V± 5% (1.14V-1.26V) o External VPP = 2.5 Volt +10%, -5% o VDDSPD = 2.5V± 10% (2.25-2.75V)  288 pin Dual-In-Line Memory Module  Edge finger connector ramp zone to reduce insertion force  Point-to-Point topology to reduce loading  Pseudo-open drain (POD12) DQ lines  Write DQ CRC (Cyclic Redundancy Check)  Internally generated VrefDQ  ECC recovery from command and parity errors  On-chip CA Parity detection for the command/address bus  Programmable CAS Latency: 11,12,13,14,15,17  Programmable CAS Write Latency (CWL).  Programmable Additive Latency (Posted CAS)  Per DRAM addressability is supported  One load for address/command signals using a Registered Clock Driver (RCD)  Selectable Fixed burst chop (BC4) of 4 and burst length (BL8) of 8 on-the-fly (OTF) via the mode register set (MRS)  8n prefetch with 2 or 4 selectable bank groups: 16 banks (4 bank groups x 4 banks per bank group)  Separate activation, read, write, refresh operations for each bank group  7 mode registers  Dynamic On-Die-Termination (ODT) and ODT Park for improved signal integrity.  Self Refresh and several Power Down Modes  DLL-off mode for power savings  ZQ pin Self Calibration for output driver and ODT  System Level Timing Calibration Support via Write Leveling and Multi Purpose Register (MPR) Read Pattern  Serial Presence Detect with EEPROM  On-DIMM Thermal Sensor  Asynchronous Reset  Bidirectional Differentially Buffered Data Strobes(DQS)  RDIMM dimensions within JEDEC MO-309 maximum limits  RoHS Compliant DDR4 SPEED BIN Nomenclature Module Standard SDRAM Standard PC4-17000 DDR4-2133 1 PC4-19200 DDR4-2400 1 PC4-21300 DDR4-2667 1 PC4-25600 DDR4-3200 Notes: 1. Contact Viking for availability date Clock 1066 MHz 1200 MHz 1333 MHz 1600 MHz DDR4 Timing Summary MT/s tCK (ns) CAS Latency (tCK) tRCD (ns) tRP (ns) tRAS (ns) tRC (ns) CL-tRCDtRP DDR4-1866 1.071 13 13.92 13.92 34 47.92 13-13-13 DDR4-2133 0.93 15 14.06 14.06 33 47.05 15-15-15 DDR4-2400 0.83 17 14.16 14.16 32 46.16 17-17-17 DDR4-2666 0.75 22 14.25 14.25 32 46.25 19-19-19 Notes:  CL = CAS Latency, tRCD = Activate –to-Command Time, tRP = Precharge Time. Refer to Speed Bin tables for details Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 5 of 46 Vikingtechnology.com Addressing 16GB(1Rx4) 2048Mbx4 DRAM 32GB(2Rx4) 2048Mbx4 DRAM 4 4 BG Address BG0~BG1 BG0~BG1 Bank Address in a BG BA0~BA1 BA0~BA1 128K:A0~A16 128K:A0~A16 A0~ A9 A0~ A9 512B 512B # of Bank Groups Bank Address Row Address Column Address Page size Note:  Micron datasheet specified 512B / 1KB as page size with “Die revision dependant”.  In Hynix and Samsung Datasheet specifies 512B for x4 Device. Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 6 of 46 Vikingtechnology.com DDR4 288-pin RDIMM Pin Wiring Assignments/Configurations Pin# Description Pin# Description Pin# Description Pin# Description Pin# Description Pin# Description 1 12V NC 145 12V NC 52 DQS17_c 196 DQS8_c 102 DQ38 246 VSS 2 VSS 146 VREFCA 53 VSS 197 DQS8_t 103 VSS 247 DQ39 3 DQ4 147 VSS 54 CB6 198 VSS 104 DQ34 248 VSS 4 VSS 148 DQ5 55 VSS 199 CB7 105 VSS 249 DQ35 5 DQ0 149 VSS 56 CB2 200 VSS 106 DQ44 250 VSS 6 VSS 150 DQ1 57 VSS 201 CB3 107 VSS 251 DQ45 7 DQS9_t 151 VSS 58 RESET_n 202 VSS 108 DQ40 252 VSS 8 DQS9_c 152 DQS0_c 59 VDD 203 CKE1 109 VSS 253 DQ41 9 VSS 153 DQS0_t 60 CKE0 204 VDD 110 DQS14_t 254 VSS 10 DQ6 154 VSS 61 VDD 205 RFU 111 DQS14_c 255 DQS5_c 11 VSS 155 DQ7 62 ACT_n 206 VDD 112 VSS 256 DQS5_t 12 DQ2 156 VSS 63 BG0 207 BG1 113 DQ46 257 VSS 13 VSS 157 DQ3 64 VDD 208 ALERT_n 114 VSS 258 DQ47 14 DQ12 158 VSS 65 A12/BC_n 209 VDD 115 DQ42 259 VSS 15 VSS 159 DQ13 66 A9 210 A11 116 VSS 260 DQ43 16 DQ8 160 VSS 67 VDD 211 A7 117 DQ52 261 VSS 17 VSS 161 DQ9 68 A8 212 VDD 118 VSS 262 DQ53 18 DQS10_t 162 VSS 69 A6 213 A5 119 DQ48 263 VSS 19 DQS10_c 163 DQS1_c 70 VDD 214 A4 120 VSS 264 DQ49 20 VSS 164 DQS1_t 71 A3 215 VDD 121 DQS15_t 265 VSS 21 DQ14 165 VSS 72 A1 216 A2 122 DQS15_c 266 DQS6_c 22 VSS 166 DQ15 73 VDD 217 VDD 123 VSS 267 DQS6_t 23 DQ10 167 VSS 74 CK0_t 218 CK1_t 124 DQ54 268 VSS 24 VSS 168 DQ11 75 CK0_c 219 CK1_c 125 VSS 269 DQ55 25 DQ20 169 VSS 76 VDD 220 VDD 126 DQ50 270 VSS 26 VSS 170 DQ21 77 VTT 221 VTT 127 VSS 271 DQ51 27 DQ16 171 VSS 78 EVENT_n 222 PARITY 128 DQ60 272 VSS 28 VSS 172 DQ17 79 A0 223 VDD 129 VSS 273 DQ61 29 DQS11_t 173 VSS 80 VDD 224 BA1 130 DQ56 274 VSS 30 DQS11_c 174 DQS2_c 81 BA0 225 A10/AP 131 VSS 275 DQ57 31 VSS 175 DQS2_t 82 RAS_n/A16 226 VDD 132 DQS16_t 276 VSS 32 DQ22 176 VSS 83 VDD 227 RFU 133 DQS16_c 277 DQS7_c 33 VSS 177 DQ23 84 S0_n 228 WE_n/A14 134 VSS 278 DQS7_t 34 DQ18 178 VSS 85 VDD 229 VDD 135 DQ62 279 VSS 35 VSS 179 DQ19 86 CAS_n/A15 230 NC 136 VSS 280 DQ63 36 DQ28 180 VSS 87 ODT0 231 VDD 137 DQ58 281 VSS Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 7 of 46 Vikingtechnology.com Pin# Description Pin# Description Pin# Description Pin# Description Pin# Description Pin# Description 37 VSS 181 DQ29 88 VDD 232 A13 138 VSS 282 DQ59 38 DQ24 182 VSS 89 S1_n 233 VDD 139 SA0 283 VSS 39 VSS 183 DQ25 90 VDD 234 A17 NC 140 SA1 284 VDDSPD 40 DQS12_t 184 VSS 91 ODT1 235 C[2] NC 141 SCL 285 SDA 41 DQS12_c 185 DQS3_c 92 VDD 236 VDD 142 VPP 286 VPP 42 VSS 186 DQS3_t 93 S2_n C[0] 237 S3_n C[1] 143 VPP 287 VPP 43 DQ30 187 VSS 94 VSS 238 SA2 144 RFU 288 VPP 44 VSS 188 DQ31 95 DQ36 239 VSS 45 DQ26 189 VSS 96 VSS 240 DQ37 46 VSS 190 DQ27 97 DQ32 241 VSS 47 CB4 191 VSS 98 VSS 242 DQ33 48 VSS 192 CB5 NC 99 DQS13_t 243 VSS 49 CB0 193 VSS 100 DQS13_c 244 DQS4_c 50 VSS 194 CB1 101 VSS 245 DQS4_t 51 DQS17_t 195 VSS Notes:  Pin 230 is defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pin 230 is defined as SAVE_n (ADR) for NVDIMMs.  A15 needed for 4GBit DRAM, A16 needed for 8GBit DRAM, A17 needed for 16GBit DRAM  DDR4 pin-out include the following additional pins beyond DDR3: Vpp, ACT_n, A17, BG0, BG1, Alert_n.  The following DDR3 pins are no longer required for DDR4: BC#, BA2, VREFDQ  Address A17 is only valid for 16GBit DRAM  RAS_n is a multiplexed function with A16. (A16 needed for 8GBit DRAM)  CAS_n is a multiplexed function with A15. (A15 needed for 4GBit DRAM)  WE_n is a multiplexed function with A14 Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 8 of 46 Vikingtechnology.com PIN FUNCTION DESCRIPTION PIN NAME DESCRIPTION PIN NAME A0 - A17' Register address input SCL BA0, BA1 Register bank select input SDA BG0, BG1 Register bank group select input SA0-SA2 Register row address strobe input Register column address strobe input Register write enable input PAR DESCRIPTION I2C serial bus clock for SPD/TS and register I2C serial bus data line for SPD/TS and register I2C slave address select for SPD/TS and register Register parity input VDD SDRAM core power supply 2 RAS_n 3 CAS_n 4 WE_n CS0_n, CS1_n, CS2_n, CS3_n DIMM Rank Select Lines input CKE0, CKE1 Register clock enable lines input VREFCA SDRAM command/address reference supply ODT0, ODT1 Register on-die termination control lines input VSS Power supply return (ground) ACT_n Register input for activate input VDDSPD DQ0 - DQ63 CB0 - CB7 DIMM memory data bus DIMM ECC check bits Data Buffer data strobes (positive line of differential pair) Data Buffer data strobes (negative line of differential pair) ALERT_n Vpp DQS9_t-DQS17_t DQS9_cDQS17_c RESET_n EVENT_n CK0_t, CK1_t CK0_c, CK1_c Register clock input (positive line of differential pair) Register clocks input (negative line of differential pair) Serial Presence Detect positive power supply Register ALERT_n output DRAM Activation power supply Set Register and SDRAMs to a known state SPD signals a thermal event has occurred. Vtt SDRAM I/O termination supply RFU Reserved for future use Notes: 1. Address A17 is only valid for 16GBit DRAM 2. RAS_n is a multiplexed function with A16. (A16 needed for 8GBit DRAM) 3. CAS_n is a multiplexed function with A15. (A15 needed for 4GBit DRAM) 4. WE_n is a multiplexed function with A14 Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 9 of 46 Vikingtechnology.com Input/Output Functional Descriptions SYMBOL TYPE CK_t, CK_c Input CKE0, (CKE1) Input CS0_n, (CS1_n) Input C0, C1, C2 Input ODT0, (ODT1) Input ACT_n Input RAS_n/A16, CAS_n/A15, WE_n/A14 Input BG0 - BG1 Input BA0 - BA1 Input A0 - A17 Input FUNCTION Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c. Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection on systems with multiple Ranks. CS_n is considered part of the command code. Chip ID: Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of stacked component. Chip ID is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM. Activation Command Input: ACT_n defines the Activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14. Command Inputs RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered. Those pins have multi function. For example, for activation with ACT_n Low, those are Addressing like A16,A15 and A14 but for non-activation command with ACT_n High, those are Command pins for Read, Write and other command defined in command truth table. Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. x4 have BG0 and BG1. Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. Address Inputs: Provided the row address for ACTIVATE Commands and the column address for Read/Write commands th select one location out of the memory array in the respective bank. (A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions, see other rows. The address inputs also provide the op-code during Mode Register Set commands. A17 is only defined for the x4 configuration. Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 10 of 46 Vikingtechnology.com SYMBOL TYPE A10 / AP Input A12 / BC_n Input RESET_n Input DQ Input / Output CB Input / Output Check Bit Input/ Output: Bi-directional ECC portion of data bus for x72 configurations Input / Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS_t and DQSL_t, are paired with differential signals DQS_c and DQSL_c respectively, to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended. DQS_t, DQS_c, DQSL_t, DQSL_c PAR Input ALERT_n Output NC FUNCTION Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD. Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific datasheets to determine which DQ is used. Command and Address Parity Input: DDR4 Supports Even Parity check in DRAMs with MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A0. Input parity should maintain at the rising edge of the clock and at the same time with command & address with CS_n LOW. Alert: It has multi functions such as CRC error flag, Command and Address Parity error flag. If there is error in CRC, then Alert_n goes LOW for the period time interval and goes back HIGH. IF there is error in Command Address Parity Check, then Alert_n goes LOW for relatively long period until on going DRAM internal recovery transaction to complete. No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.2 V +/- 0.06 V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.2 V +/- 0.06 V VSS Supply Ground Vpp Supply DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max) VREFCA Supply Reference voltage for CA Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 11 of 46 Vikingtechnology.com SYMBOL TYPE FUNCTION ZQ Supply Reference Pin for ZQ calibration Notes: 1. The input only pins (BG0-BG-1, BA0-BA1, A0-A17, ACT_n, RAS_n,/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supply termination. Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 12 of 46 Vikingtechnology.com MECHANICAL OUTLINE PHYSICAL LAYOUT, SINGLE RANK, 288 pin 4.1mm Notes:  All dimensions in mm  Refer to JEDEC Standard Mechanical Outline MO-309 for other details  DDR4 PCB is higher and thicker then DDR3 and the gold finger pins may have a ramp zone for easy insertion into DIMM  Sockets Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 13 of 46 Vikingtechnology.com PHYSICAL LAYOUT, DUAL RANK 288 pin 4.1mm Notes:  All dimensions in mm (inches)  Refer to JEDEC Standard Mechanical Outline MO-309 for other details  DDR4 PCB is higher and thicker then DDR3 and the gold finger pins may have a ramp zone for easy insertion into DIMM Sockets Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 14 of 46 Vikingtechnology.com Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 15 of 46 Vikingtechnology.com FUNCTIONAL BLOCK DIAGRAM DRAM DRAM DRAM DRAM DRAM DRAM B-side Address/ Command DDR4 RCD B-side A-side Vtt DRAM Control DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM Vtt DRAM DRAM DRAM BLOCK DIAGRAM, SINGLE RANK Vtt Data Clock Control Address/ Command DDR4 HOST MEMORY INTERFACE BLOCK DIAGRAM, DUAL RANK DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM Rank 1 Vtt B-side A-side DRAM DRAM DRAM DRAM DRAM DRAM B-side Address/ Command DDR4 RCD DRAM Control DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM Vtt DRAM DRAM DRAM Rank 0 Vtt Vtt Data Clock Control Address/ Command DDR4 HOST MEMORY INTERFACE Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 16 of 46 Vikingtechnology.com QRST_n QVFEFCA ERROR_IN_n To and From DRAMs QACKE[1:0] QBCKE[1:0] QAODT[1:0] QBODT[1:0] QBCS[1:0] QACS[1:0] QBCS[3:2] or QBC[1:0] QACS[3:2] or QAC[1:0] QBC2 QAC2 To A-side DRAMs QA *CA QB *CA DDR4 Registered Clock Driver (RCD) QAACT_n QAPAR Y1_t,Y1_c QBACT_n To B-side DRAMs QBPAR Y0_t,Y0_c Y2_t,Y2_c Y3_t,Y3_c QBVREFCA SMBus SDA,SCL,SA[2:0], VDDSPD BCK_t, BCK_c . BCOM [3:0] BFUNC BODT ZQCAL To DQ Buffers ALERT_n DRST_n VREFCA CK_t, CK_n DPAR DACT_n D *CA DC2 DCS[3:0] DODT[1:0] *CA: A[17:0], BA[1:0], BG[1:0] A14=WE_n, A15=CAS_n, A16=RAS_n DCKE[1:0] BCKE DDR4 RDIMM Connector Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 17 of 46 Vikingtechnology.com (Device 0 - 35, for 2 ranks) SPD and THERMAL SENSOR Notes:  Unless otherwise noted, resistor values are 15 Ω ±5%.  See the Net Structure diagrams for all resistors associated with the command, address and control bus.  ZQ resistors are 240 Ω ±1%. For all other resistor values, refer to the appropriate wiring diagram.  Refer to EE1004-v and TSE2004av specifications for details. Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 18 of 46 Vikingtechnology.com DQ and DQS MAPPING BYTE Group 0 1 2 3 4 5 6 7 8 0 DQ0 DQ8 DQ16 DQ24 DQ32 DQ40 DQ48 DQ56 CB0 1 DQ1 DQ9 DQ17 DQ25 DQ33 DQ41 DQ49 DQ57 CB1 2 DQ2 DQ10 DQ18 DQ26 DQ34 DQ42 DQ50 DQ58 CB2 DQ 3 4 DQ3 DQ4 DQ11 DQ12 DQ19 DQ20 DQ27 DQ28 DQ35 DQ36 DQ43 DQ44 DQ51 DQ52 DQ59 DQ60 CB3 CB4 5 DQ5 DQ13 DQ21 DQ29 DQ37 DQ45 DQ53 DQ61 CB5 6 DQ6 DQ14 DQ22 DQ30 DQ38 DQ46 DQ54 DQ62 CB6 7 DQ7 DQ15 DQ23 DQ31 DQ39 DQ47 DQ55 DQ63 CB7 DQS DQS0_t DQS1_t DQS2_t DQS3_t DQS4_t DQS5_t DQS6_t DQS7_t DQS8_t DQS0_c DQS1_c DQS2_c DQS3_c DQS4_c DQS5_c DQS6_c DQS7_c DQS8_c DQS9_t DQS10_t DQS11_t DQS12_t DQS13_t DQS14_t DQS15_t DQS16_t DQS17_t DQS9_c DQS10_c DQS11_c DQS12_c DQS13_c DQS14_c DQS15_c DQS16_c DQS17_c DQ Internal Vref Specifications PARAMETER Vref Max operating point Range 1 Vref Min operating point Range 1 Vref Max operating point Range 2 Vref Min operating point Range 2 Vref Stepsize Vref Set Tolerance Vref Step Time Vref VaIid tolerance SYMBOL Min Vref_max_R1 Vref_min_R1 60% Typ Max UNIT NOTES - 92% VDDQ 1, 11 VDDQ 1,11 77% VDDQ 1, 11 0.80% 1.63% 0.15% 150 60 0.15% VDDQ VDDQ VDDQ VDDQ ns ns VDDQ 1,11 2 3,4,6 3,5,7 9 8 10 - Vref_max_R2 - Vref_min_R2 Vref_step Vref_set_tol 0.65% 0.00% 0.00% 0.00% 45% 0.50% -1 .625% -0.15% Vref_time-long Vref_time-Short Vref_val_tol -0.15% Notes: 1. JESD8-24 specifies Vref to be 70% of VDDQ. Vref DC voltage referenced to VDDQ_DC. VDDQ_DC is 1.2V 2. Vref stepsize increment/decrement range. Vref at DC level. 3. Vref_new = Vref_old+n*Vref_step; n=number of step; if increment use “+”; If decrement use “-” 4. The minimum value of Vref setting tolerance=Vref_new-1.625%*VDDQ. The maximum value of Vref setting tolerance=Vref_new+1.625%*VDDQ. For n>4 5. The maximum value of Vref setting tolerance=Vref_new-0.15%*VDDQ. The maximum value of Vref setting tolerance=Vref_new+0.15%*VDDQ. 6. Measured by recording the min and max values of the Vref output over the range, drawing a straight line between those points and comparing all other Vref output settings to that line 7. Measured by recording the min and max values of the Vref output across 4 consecutive steps(n=4), drawing a straight line between those points and comparing all other Vref output settings to that line 8. Time from MRS command to increment of decrement one step size for Vref 9. Time from MRS command to increment of decrement more than one step size up to full range of Vref 10. Only applicable for DRAM component level test/characterization purpose. Not applicable for normal mode of operation. Vref valid is to qualify the step times which will be characterized at the component level. 11. DRAM range1 or 2 set by MRS bit MR6, A6. Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 19 of 46 Vikingtechnology.com OVERVIEW OF DDR4 RDIMM MODULE OPERATION The DDR4 architecture is generally a point-to-point topology with a dedicated channel design. The highest system performance levels can be achieved when the system is configured with 1 DIMM Per Channel (1DPC). DDR4 has more features than DDR3 with a pseudo-open drain (POD12) 1.2v I/O for the data channel, trained Vref, bank groups and write CRC (Cyclic Redundancy Check). The POD12 interface only applies to the data channel. The address command channel behave like DDR3 using mid-point termination and mid-point Vref. The new bank group interleaving feature in DDR4 maximizes data transfer bandwidth. The DDR4 RDIMM has a Registered Clock Driver (RCD) on the address, command and control lines which are center terminated as they were in DDR3. The RCD supports both RDIMM and LRDIMM modes and the default is RDIMM mode. Mode register MR7 (Manufacturing use only to program the RCD) configures the DDR4 RCD using multi-step mode register programming. MR Mode Register Read via MPR Multi-Purpose Register contains the control word bits that select the working mode. DDR4 DRAM use pseudo-open drain (POD12) 1.2v drivers with Vdd terminations on DQ lines to increase data rates; unlike DDR3 DRAM that uses stub-series terminated logic drivers, The DRAM addressing scheme in DDR4 is organized into bank groups, Side A and Side B. The host DDR4 memory controller interleaves (multiplexes) among the bank groups to achieve high data rates. DDR4 architecture is a 8n prefetch with bank groups, including the use of two or four selectable bank groups. This will permit the DDR4 memory devices to have separate activation, read, write or refresh operations simultaneously underway in each of the unique bank groups to improve overall memory efficiency and bandwidth, especially when small memory granularities are used. The data written to the DIMM is read back the same way. However when writing to the internal registers with a "load mode" operation, a specific address is required. This requires the controller to know if the rank is mirrored or not. There is a bit assignment in the SPD that indicates whether the module has been designed with a mirrored feature or not. DDR4 offers ECC recovery from command and parity errors to prevent the host system from crashing. The use of CRC parity is an optional feature on address command and data; (Error command blocking when parity enabled and post CA parity. If the DIMM does not support CRC, the values of 0x00 will fill the CRC table. The new CA parity feature on the command/address bus provides a low-cost method of verifying the integrity of command and address transfers over a link, for all operations. Some of the main attributes of DDR4 memory are: 1) The ACT_n activate pin replaces RAS#, CAS#, and WE# commands 2) PAR and Alert_n for error checking 3) Bank group Interleaving 4) Improved training modes upon power-up 5) Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin 6) DQ bus geardown mode for 2667Mhz data rates and beyond 7) External VPP at 2.5V (for wordline boost) 8) 1.2V VDD power with power-saving features that include MPSM Maximum Power Savings Mode, Low Power Auto Self Refresh, Temperature Controlled Refresh, Fine Granularity Refresh, CMD/ADDT latency and DLL off mode 9) Internally generated VrefDQ and Calibration.  VrefDQ is supplied by the DRAM internally  VrefCA is supplied by the board Important Note: Longer boot-up times may be experienced in certain situations for controller initiated functions such as VrefDQ calibration, write leveling and other trainings for the DIMM. Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 20 of 46 Vikingtechnology.com DDR4 offers certain performance features that are shown in the following table: DDR4 Performance Features Command reordering at queue entry AND queue exit What It Improves Reduced impact from high-priority commands maximizes memory bandwidth and throughput, especially difficult traffic scenarios. Highpriority commands go straight to the head of the command queue when they’re received, but controller can delay the command’s exit from the queue until the target DDR4 memory page and bank are ready to accept that command. High-priority commands can enter the queue at head-of-queue position Latency for high-priority commands Rank grouping and splitting Bandwidth for multi-rank systems Bank split multiple transactions Bandwidth for high-speed DRAM Read/write grouping improvements Bandwidth for all DRAM Data buffers moved to ports parallel write data offload System bandwidth on narrow transfers. re-orderable write data bandwidth, Multiple core read data FlFOs Bandwidth if the system bus is stalled Programmable activate look-ahead distance Latency for high-priority commands when autoprecharge is used More DRAM banks (16 on each die) More pages can be opened at the same time. And lower latency Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 21 of 46 Vikingtechnology.com DDR4 MODE REGISTERS A12 A11 MR0 RFU MR1 Qoff TDQS MR2 Write CRC RFU MR3 A10 A9 Write Recovery and RTP MPR Read Format A8 A7 DLL Reset Test Mode Write Leveling Rtt_NOM Rtt_WR RFU Write CMD Latency with CRC and DM A6 A5 A4 CAS Latency CL RFU RFU Auto Self Refresh Fine Granularity Refresh Temp Refresh Mode Temp. Refresh Range CRC Error Clear CS-to-Address Latency CAL RFU MR5 Read DBI Enable Write DBI Enable Data Mask Enable Parity Persistent Error Rtt_PARK ODT input in Power Down Panty Error Status MR7 VrefDQ Training enable RFU MPR Enable MR4 VrefDQ Training Range DLL Enable Ron Gear down VrefDQ Monitor Enable A0 Burst Length BL PerDRAM Addr Mode Self Refresh Abort Enable RFU A1 Temp Sensor Read Preamble Training Enable RFU CL CWL Read Preamble tCCD_L and tDLLK Timing A2 Additive Latency Write Preamble MR6 A3 Burst Type RFU MPR Page Max Power Down Enable VretDQ Training Value Manufacturing use only to program the RCD 8/02/17 Viking Technology Page 22 of 46 Vikingtechnology.com RFU CMD Address Parity Latency Notes: 1. Refer to JEDEC documentation for detail of the control/status bits. Datasheet PS9MRxx72x4xxx_VP Revision H RFU DC OPERATING CONDITIONS AND CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL VALUE UNIT NOTES Voltage on any pin relative to GND Voltage on VDD supply relative to GND Voltage on VDDQ supply relative to GND Voltage on VPP supply relative to GND Module operating temperature (ambient) Storage temperature Vin, Vout VDD VDDQ VPP Topr Tstg -0.3 ~ 1.5 -0.3 ~ 1.5 -0.3 ~ 1.5 -0.3 ~ 3.0 0 ~ 55 -55 ~ +100 V V V V C C 1, 1,3 1,3 4 1,5 1,2 Notes: 1. Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51- 2 standard. 3. VDD and VDDQ must be within 300 mV of each other at all times and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREF may be equal to or less than 300 mV. 4. VPP must be equal or greater than VDD/VDDQ at all times. 5. Refer to JEDEC JC451 specification. DRAM Component Operating Temperature Range SYMBOL Toper PARAMETER RATING UNITS NOTES Normal Operating Temperature Range 0 to 85 °C 1,2 Extended Temperature Range 85 to 95 °C 1,3 Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85°C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 °C and 95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual SelfRefresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). DDR4 SDRAM’s support Auto Self-Refresh and in Extended Temperature Range and please refer to component datasheet and/or the DIMM SPD for tREFI requirements in the Extended Temperature Range tREFI by Device Density PARAMETER Average periodic refresh interval SYMBOL 2Gb 4Gb 8Gb 16Gb UNITS 0°C ≤ Tcase ≤ 85°C 7.8 7.8 7.8 7.8 μs 85°C ≤ Tcase ≤ 95°C 3.9 3.9 3.9 3.9 μs tREFI Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 23 of 46 Vikingtechnology.com AC & DC Operating Conditions DC OPERATING CONDITIONS AND CHARACTERISTICS (POD12) SYMBOL VPP Supply Voltage VDD: PG4:1.2V±5%, PG4L: 1.05 (TBD) Supply Voltage for Output. Values in () are at 70% of VDD 2.5V +10%, -5% VDDSPD 2.5V± 10% VDD VDDQ RATING PARAMETER UNITS NOTES Min Typ Max 1.14 1.2 1.26 v 1,2,3 1.14 (0.798) 1.2 (0.84) 1.26 (0.882) v 1 2.375 2.5 2.75 v 3 2.25 2.5 2.75 v Notes:  PODI2 1.2 V Pseudo Open Drain Interface has a VDDQ value of 1.2V but the reference voltage allows PODI2 to be used with other VDDQ values. POD12 signals have pull-up-only parallel input termination and have an asymmetric output drive impedance. For example, if the output drivers were using a 60 ohm pull-up drive impedance then the pull-down drivers would be expected to produce a 40 ohm pull-down drive impedance. PODI2 does not explicitly call for series termination resistors, so it is suitable for point-to-point as well as multi-drop stub environments which may require some additional termination. 1. JESD8-24 specifies Vref to be 70% of VDDQ. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. DC bandwidth is limited to 20MHz. Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 24 of 46 Vikingtechnology.com DC CHARACTERISTICS, IDD CURRENTS IDD DEFINITIONS SYMBOL DDR4 IDD, IDDQ, and IPP Specs IDD0A Operating One Bank Active-Precharge Current (AL=CL-1) IPP0 Operating One Bank Active-Precharge IPP Current IDD1A Operating One Bank Active-Read-Precharge Current (AL=CL-1) IPP1 Operating One Bank Active-Read-Precharge IPP Current IDD2NA Precharge Standby Current (AL=CL-1) IPP2N Precharge Standby IPP Current IDD2NL Precharge Standby Current with CAL enabled IDD2NG Precharge Standby Current with Gear Down mode enabled IDD2ND Precharge Standby Current with DLL disabled IDD2N_par Precharge Standby Current with CA parity enabled IPP2P Precharge Power-Down IPP Current IDD3NA Active Standby Current (AL=CL-1) IPP3N Active Standby IPP Current IPP3P Active Power-Down IPP Current IDD4RA Operating Burst Read Current (AL=CL-1) IDD4RB Operating Burst Read Current with Read DBI IPP4R Operating Burst Read IPP Current IDDQ4RB (Optional) Operating Burst Read IDDQ Current with Read DBI IDD4WA Operating Burst Write Current (AL=CL-1) IDD4WB Operating Burst Write Current with Write DBI IDD4WC Operating Burst Write Current with Write CRC IDD4W_par Operating Burst Write Current with CA Parity IPP4W Operating Burst Write IPP Current IPP5B Burst Refresh Write IPP Current (1x REF) IDD5F2 Burst Refresh Current (2x REF) IPP5F2 Burst Refresh Write IPP Current (2x REF) IDD5F4 Burst Refresh Current (4x REF) IPP5F4 Burst Refresh Write IPP Current (4x REF) IPP6N Self Refresh IPP Current: Normal Temperature Range IPP6E Self Refresh IPP Current: Extended Temperature Range lDD6R Self-Refresh Current: Reduced Temperature Range IPP6R Self Refresh IPP Current: Reduced Temperature Range IPP6A Auto Self-Refresh IPP Current IPP7 Operating bank Interleave Read IPP Current IPP8 Maximum Power Down IPP Current Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 25 of 46 Vikingtechnology.com Notes: 1) DDR4 IDD and IDDQ specs include the same DDR3 IDD and IDDQ specs with these exceptions: a. IDD2P0 and IDD2P1 are replaced with a single IDD2P. There’s no longer any difference in power for the DLL because of better DLL power management inside the DRAM device without any benefit for using slow exit. b. IDD6 is renamed IDD6N Self Refresh Current: Normal Temperature Range c. IDD6ET is renamed IDD6E Self-Refresh Current: Extended Temperature Range d. IDD6TC is renamed IDD6AAut0 Self-Refresh Current e. IDD8 is redefined from (optional) RESET Low Current to IDD8 Maximum Power Down Current, TBD 2) IDD values are an average (not peak) current drawn throughout the entire time that it takes to execute the set of conditions specified by JEDEC standards. 3) Consult with Viking for tools to help specify the Total Design Power (TDP) IDD6 Specification Symbol IDD6N IDD6E IDD6R IDD6A Temperature Range o 0 - 85 C o 0 - 95 C o 0 - 45 C o 0 C ~ Ta Tb ~ Ty Tz ~ TOPERmax Value 22 33 10 9 10 16 Unit mA mA mA mA mA mA Notes 3,4 4,5,6 4,6,9 4,6,7,8 4,6,7,8 4,6,7,8 Notes: 1. Some IDD currents are higher for x16 organization due to larger page-size architecture. 2. Max. values for IDD currents considering worst case conditions of process, temperature and voltage. 3. Applicable for MR2 settings A6=0 and A7=0. 4. Supplier data sheets include a max value for IDD6. 5. Applicable for MR2 settings A6=0 and A7=1. IDD6ET is only specified for devices which support the Extended Temperature Range feature. 6. Refer to the supplier data sheet for the value specification method (e.g. max, typical) for IDD6ET and IDD6TC 7. Applicable for MR2 settings A6=1 and A7=0. IDD6TC is only specified for devices which support the Auto Self Refresh feature. 8. The number of discrete temperature ranges supported and the associated Ta - Tz values are supplier/design specific. Temperature ranges are specified for all supported values of TOPER. Refer to supplier data sheet for more information. 9. Applicable for MR2 settings TBD. IDD6R is verified by design and characterization, and may not be subject to production test. Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 26 of 46 Vikingtechnology.com IDD CURRENTS (8Gbit based) 16GB, Single Rank Symbol 32GB, Dual Rank DDR4-2133 DDR4-2400 DDR4-2133 DDR4-2400 15-15-15 17-17-17 15-15-15 17-17-17 1.2V 1.2V 1.2V 1.2V IDD IPP IDD IPP IDD IPP IDD Units IPP IDD0 905 72 953 72 1356 126 1438 126 mA IDD0A 929 72 999 72 1379 126 1485 126 mA IDD1 1186 72 1246 72 1667 126 1772 126 mA IDD1A 1223 72 1292 72 1704 126 1819 126 mA IDD2N 698 54 749 54 1189 108 1276 108 mA IDD2NA 747 54 806 54 1247 108 1349 108 mA IDD2NT 732 54 793 54 1216 108 1323 108 mA IDD2NL 613 54 656 54 979 108 1049 108 mA IDD2NG 702 54 754 54 1156 108 1244 108 mA IDD2ND 674 54 722 54 1100 108 1180 108 mA IDD2N_par 735 54 785 54 1221 108 1307 108 mA IDD2P 460 54 492 54 598 108 652 108 mA IDD2Q 675 54 723 54 1103 108 1182 108 mA IDD3N 856 54 928 54 1461 108 1591 108 mA IDD3NA 895 54 972 54 1537 108 1678 108 mA IDD3P 537 54 586 54 748 108 840 108 mA IDD4R 1860 54 2041 54 2341 108 2568 108 mA IDD4RA 1919 54 2110 54 2400 108 2637 108 mA IDD4RB 1882 54 2067 54 2363 108 2593 108 mA IDD4W 1771 54 1959 54 2252 108 2486 108 mA IDD4WA 1836 54 2031 54 2317 108 2557 108 mA IDD4WB 1771 54 1960 54 2252 108 2486 108 mA IDD4WC 1730 54 1852 54 2210 108 2379 108 mA IDD4W_par 1917 54 2132 54 2397 108 2658 108 mA IDD5B 3706 324 3782 324 4187 378 4308 378 mA IDD5F2 2750 270 2818 270 3231 324 3344 324 mA IDD5F4 2381 252 2445 252 2862 306 2971 306 mA Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 27 of 46 Vikingtechnology.com 16GB, Single Rank 32GB, Dual Rank DDR4-2133 DDR4-2400 DDR4-2133 DDR4-2400 15-15-15 17-17-17 15-15-15 17-17-17 1.2V 1.2V 1.2V 1.2V Symbol IDD IPP IDD IPP IDD IPP IDD Units IPP IDD6N 374 72 404 72 734 144 796 144 mA IDD6E 562 90 596 90 1108 180 1178 180 mA IDD6R 282 63 308 63 550 126 603 126 mA IDD6A 364 72 388 72 714 144 763 144 mA IDD7 3297 144 3648 153 3778 198 4175 207 mA IDD8 160 54 181 54 317 108 360 108 mA Notes: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N. 2. All ranks in this IDD/PP condition. 3. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following options or requirements referred to in this material. 4. Values as per Samsung Datasheet DS_DDR4_8Gb_Bdie_RegisteredDIMM_Rev15-0 IDD CURRENTS (4Gbit based) 8GB, Single Rank 16GB, Dual Rank DDR4-2133 DDR4-2400 DDR4-2133 DDR4-2400 15-15-15 17-17-17 15-15-15 17-17-17 1.2V 1.2V 1.2V 1.2V Symbol IDD IPP IDD IPP IDD IPP IDD Units IPP IDD0 879 72 893 72 748 63 763 63 mA IDD0A 900 72 926 72 759 63 780 63 mA IDD1 1135 54 1153 54 941 54 955 54 mA IDD1A 1177 54 1201 54 962 54 980 54 mA IDD2N 658 54 676 54 638 54 655 54 mA IDD2NA 660 54 678 54 640 54 657 54 mA IDD2NT 688 54 715 54 668 54 695 54 mA IDD2NL 586 54 603 54 568 54 584 54 mA IDD2NG 662 54 680 54 641 54 659 54 mA IDD2ND 631 54 645 54 611 54 625 54 mA IDD2N_par 669 54 686 54 649 54 665 54 mA IDD2P 442 54 450 54 426 54 435 54 mA Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 28 of 46 Vikingtechnology.com 8GB, Single Rank 16GB, Dual Rank DDR4-2133 DDR4-2400 DDR4-2133 DDR4-2400 15-15-15 17-17-17 15-15-15 17-17-17 1.2V 1.2V 1.2V 1.2V Symbol IDD IPP IDD IPP IDD IPP IDD Units IPP IDD2Q 638 54 653 54 617 54 632 54 mA IDD3N 828 54 849 54 786 54 806 54 mA IDD3NA 830 54 850 54 789 54 808 54 mA IDD3P 532 54 541 54 505 54 514 54 mA IDD4R 1673 54 1769 54 1293 54 1353 54 mA IDD4RA 1735 54 1841 54 1322 54 1391 54 mA IDD4RB 1695 54 1793 54 1306 54 1370 54 mA IDD4W 1610 54 1719 54 1182 54 1246 54 mA IDD4WA 1676 54 1795 54 1215 54 1283 54 mA IDD4WB 1610 54 1719 54 1181 54 1246 54 mA IDD4WC 1526 54 1591 54 1139 54 1179 54 mA IDD4W_par 1720 54 1856 54 1237 54 1316 54 mA IDD5B 3660 324 3683 324 2183 189 2204 189 mA IDD5F2 3111 270 3132 270 1909 162 1929 162 mA IDD5F4 2430 198 2456 198 1570 126 1592 126 mA IDD6N 301 72 300 72 286 72 281 72 mA IDD6E 427 72 427 72 410 72 405 72 mA IDD6R 237 72 236 72 224 72 218 72 mA IDD6A 291 72 290 72 277 72 272 72 mA IDD7 3379 162 3702 162 1763 108 1782 108 mA IDD8 142 36 141 36 129 36 124 36 mA Notes: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N. 2. All ranks in this IDD/PP condition. 3. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following options or requirements referred to in this material. 4. Values as per Samsung Datasheet DS_DDR4_4Gb_Edie_RegisteredDIMM_Rev11-0 Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 29 of 46 Vikingtechnology.com Input/Output Capacitance SYMBOL CIO CDIO CDDQS CCK CDCK CI CDI_CTRL CDl_ADD_CMD CALERT CZQ PARAMETER Input/output capacitance Input/output capacitance delta Input/output capacitance delta DQS and DQS# Input capacitance, CK and CK# Input capacitance delta CK and CK# Input capacitance(CTRL, ADD, CMD pins only) Input capacitance delta(All CTRL pins only) Input capacitance delta(All ADD/CMD pins only) lnput/output capacitance of ALERT Input/output capacitance of ZQ DDR4-1600 DDR4-1867 DDR4-2133 Min Max 0.7 1.4 Min 0.7 Max 1.3 Min TBD -0.1 0.1 -0.1 0.1 - 0.05 - 0.2 0.8 - DDR4-2400 DDR4-2667 DDR4-3200 UNIT NOTES Max TBD pF 1,3 TBD TBD pF 1,3,11 0.05 TBD TBD pF 1, 3,5 0.2 0.8 TBD TBD pF 1,3 0.05 - 0.05 TBD TBD pF 1,3,4 0.2 0.8 0.2 0.7 TBD TBD pF 1,3,6 -0.1 0.1 -0.1 0.1 TBD TBD pF 1,3,7,8 -0.1 0.1 -0.1 0.1 TBD TBD pF 1, 9, 10 0.5 1.5 0.5 1.5 TBD TBD pF 1,3 0.5 1.5 0.5 1.5 TBD TBD pF 1,3,12 Notes: 1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is validated by de-embedding the package L & C parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all other signal pins floating. 2. RFU 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here. 4. Absolute value CK_T-CK_C 5. Absolute value of CIO(DQS_T)-CIO(DQS_C) 6. CI applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0-BG1, RAS_n, CAS_n, WE_n. 7. CDI CTRL applies to ODT, CS_n and CKE 8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C)) 9. CDI_ADD_ CMD applies to, A0-A17, BA0-BA1, BG0-BG1, RAS_n, CAS_n, WE_n. 10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C)) 11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_C)) 12. Maximum external load capacitance on ZQ pin Datasheet PS9MRxx72x4xxx_VP Revision H 8/02/17 Viking Technology Page 30 of 46 Vikingtechnology.com DC and AC Specifications for the SMBus Interface The specifications for the SMBus follow JEDEC standards. Speed Bins by Speed Grade DDR4-1600 Speed Bins and Operating Conditions Speed Bin CL-nRCD-nRP Parameter Symbol DDR4-1600 11-11-11 Min Max 14 13.75 18 5,12 (13.50) UNIT Internal read command to first data tAA Internal read command to first data with read DBI enabled tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns ACT to internal read or write delay time tRCD 13.75 5,12 (13.50) - ns PRE command period tRP 13.75 5,12 (13.50) - ns ACT to PRE command period tRAS 35 9 x tREFI ns ACT to ACT or REF command period tRC 48.75 5,12 (48.50) - ns CWL = 9 CWL = 9,11 Normal Read DBI CL = 9 CL = 11 5 (Optional) tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 11 CL = 13 tCK(AVG) 1.25 CL = 12 CL = 14 tCK(AVG) 1.25 NOTES ns Reserved ns 1,2,3,4,11 ,14 1.6 ns 1,2,3,4,11 Reserved ns 1,2,3,4