VSFN253T20YCFWSM

NVMe PCIe SSD 2.5” SSD Manual NVMe PCIe SSD is a non-volatile, solid-state storage device delivering uncompromising performance, reliability and ruggedness for environmentally challenging applications. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 1 of 66 Revision History Date Revision 3/13/2017 A 4/10/2017 B 3/26/18 C Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Description Initial Release revised to new format from PSFN22xxxxWxxx_PM963_B. Add enterprise features. Update performance. Revise height to 14.8mm Revise for 1725a by updating mechanical dimensions and performance. Revised all DC and AC characteristics, PBW, power, LBA, and environmental. Add UEFI EXPANSION ROM and VPD structure. Remove SPOR. Add Hot plug. Revised Supported Command Set. Remove SR-IOV info Checked By 3/26/2018 Viking Technology Page 2 of 66 Legal Information Legal Information Copyright© 2018 Sanmina Corporation. All rights reserved. The information in this document is proprietary and confidential to Sanmina Corporation. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Sanmina. Sanmina reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of Sanmina to provide notification of such revision or change. Sanmina provides this documentation without warranty, term or condition of any kind, either expressed or implied, including, but not limited to, expressed and implied warranties of merchantability, fitness for a particular purpose, and noninfringement. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. In no event will Sanmina be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. Sanmina may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. Sanmina, Viking Technology, Viking Modular Solutions, and Element logo are trademarks of Sanmina Corporation. Other company, product or service names mentioned herein may be trademarks or service marks of their respective owners. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 3 of 66 Ordering Information: 2.5 inch PCIe SSD Solid-State Drive Part Numbers Interface VSFN25800GYCZWSE PCIe/NVMe VSFN251T60YCZWSE PCIe/NVMe VSFN253T20YCFWSM PCIe/NVMe VSFN256T40YCGWSM PCIe/NVMe Application Enterprise PM1725a Enterprise PM1725a Enterprise PM1725a Enterprise PM1725a Useable Capacity 1 (GB) Port Temperature Range 800 GB Dual (0 to +70'c) 1600 GB Dual (0 to +70'c) 3200 GB Dual (0 to +70'c) 6400 GB Dual (0 to +70'c) NAND Samsung TLC, V3 VNAND Samsung TLC V3 VNAND Samsung TLC V3 VNAND Samsung TLC V3 VNAND Notes: 1. Usable capacity based on a level of over-provisioning applied to wear leveling, bad sectors, index tables etc. 2. SSD’s ship unformatted from the factory unless otherwise requested. 3. 1 GB = 1,000,000,000 Byte 4. One Sector = 512 Byte. 5. SFF-8639 combo (SATA, SAS, PCIe) standard connector . Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 4 of 66 Product Picture(s) Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 5 of 66 Table of Contents 1 INTRODUCTION 12 1.1 Features 12 1.2 PCIE Interface 13 2 PRODUCT SPECIFICATIONS 14 2.1 Capacity and LBA count 14 2.2 Performance 15 2.3 Timing / Latency 15 2.4 Quality of Service (QoS) 16 2.5 Electrical Characteristics 2.5.1 Absolute Maximum Ratings 2.5.2 Supply Voltage 2.5.3 Power Consumption 16 16 17 17 2.6 Environmental Conditions 2.6.1 Temperature and Altitude 2.6.2 Shock and Vibration 2.6.3 Electromagnetic Immunity 18 18 18 19 2.7 19 Reliability 2.8 Data Security 2.8.1 Power Loss Protection 19 19 2.9 Hot Plug Support 2.9.1 Power Loss Protection 2.9.2 Inrush Current Protection 20 20 20 2.10 Enterprise Class Storage Features 2.10.1 Dual Port Capability 2.10.2 SR-IOV support 2.10.3 Multi-namespace support 2.10.4 Remote Health Monitoring 3 MECHANICAL INFORMATION Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 21 21 Error! Bookmark not defined. 22 22 23 3/26/2018 Viking Technology Page 6 of 66 3.1 Dimensions 23 3.2 2.5 inch SSD Weight 26 4 4.1 5 PIN AND SIGNAL DESCRIPTIONS Signal and Power Description Tables PCIE AND NVM EXPRESS REGISTERS 26 26 28 5.1 PCI Express Registers 5.1.1 PCI Register Summary 5.1.2 PCI Header Registers 5.1.3 PCI Power Management Registers 5.1.4 Message Signaled Interrupt Registers 5.1.5 MSI-X Registers 5.1.6 PCI Express Capability Registers 5.1.7 Advanced Error Reporting Registers 5.1.8 Device Serial Number Capability Register 5.1.9 Power Budgeting Extended Capability 5.1.10 Latency Tolerance Reporting Capability Registers 5.1.11 L1 Substates Capability Registers 28 28 28 32 33 34 36 40 46 46 47 47 5.2 NVM Express Registers 5.2.1 Register Summary 5.2.2 Controller Registers 48 48 49 6 52 SUPPORTED COMMAND SET 6.1 Admin Command Set 6.1.1 Identify Command 52 53 6.2 NVM Express I/O Command Set 59 6.3 SMART/Health Information 61 7 7.1 8 SFF-8639 SMBUS RESOURCES Vital Product Data (VPD) Structure UEFI EXPANSION ROM 62 62 65 8.1 Basic Information 8.1.1 General Features 65 65 8.2 65 Supported Operating Systems Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 7 of 66 9 10 PRODUCT COMPLIANCE REFERENCES Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 66 66 3/26/2018 Viking Technology Page 8 of 66 Table of Tables Table 2-1: Maximum Sustained Read and Write Bandwidth ____________________________ 15 Table 2-2: Maximum Random Read and Write Input/Output Operations per Second (IOPS) ___ 15 Table 2-3: Timing Specifications _________________________________________________ 15 Table 2-4: Quality of Service (QoS) _______________________________________________ 16 Table 2-5: Operating Voltage IOPS Consistency _____________________________________ 16 Table 2-6: Operating Voltage ____________________________________________________ 17 Table 2-7: Typical Power Consumption at 12V ______________________________________ 17 Table 2-8: Temperature and Altitude Related Specifications ____________________________ 18 Table 2-9: Shock and Vibration Specifications _______________________________________ 18 Table 2-10: Reliability Specifications ______________________________________________ 19 Table 3-1: Physical Dimensions __________________________________________________ 23 Table 3-2: 2.5 inch SSD weight __________________________________________________ 26 Table 4-1: 2.5 inch PCIE Connector Pinouts ________________________________________ 26 Table 5-1: PCI Register Summary ________________________________________________ 28 Table 5-2: PCI Header Register Summary __________________________________________ 28 Table 5-3: Identifier Register ____________________________________________________ 29 Table 5-4: Command Register ___________________________________________________ 29 Table 5-5: Device Status Register ________________________________________________ 30 Table 5-6: Revision ID Register __________________________________________________ 30 Table 5-7: Class Code Register __________________________________________________ 30 Table 5-8: Cache Line Size Register ______________________________________________ 30 Table 5-9: Master Latency Timer Register __________________________________________ 30 Table 5-10: Header Type Register ________________________________________________ 30 Table 5-11: Built-in Self Test Register _____________________________________________ 31 Table 5-12: Memory Register Base Address Lower 32-bits (BAR0) Register _______________ 31 Table 5-13: Memory Register Base Address Upper 32-bits (BAR1) Register _______________ 31 Table 5-14: Index/Data Pair Register Base Address (BAR2) Register ____________________ 31 Table 5-15: BAR3 Register ______________________________________________________ 31 Table 5-16: Vendor Specific BAR4 Register ________________________________________ 31 Table 5-17: Vendor Specific BAR5 Register ________________________________________ 31 Table 5-18: Subsystem Identifier Register __________________________________________ 31 Table 5-19: Expansion ROM Register _____________________________________________ 32 Table 5-20: Capabilities Pointer Register ___________________________________________ 32 Table 5-21: Interrupt Information Register __________________________________________ 32 Table 5-22: Minimum Grant Register ______________________________________________ 32 Table 5-23: Maximum Latency Register ____________________________________________ 32 Table 5-24: PCI Power Management Capability Register Summary ______________________ 32 Table 5-25: PCI Power Management Capability ID Register ____________________________ 32 Table 5-26: PCI Power Management Capability Register ______________________________ 33 Table 5-27: PCI Power Management Control and Status Register _______________________ 33 Table 5-28: Message Signaled Interrupt Capability Register Summary ___________________ 33 Table 5-29: Message Signaled Interrupt Capability ID Register _________________________ 33 Table 5-30: Message Signaled Interrupt Control Register ______________________________ 34 Table 5-31: Message Signaled Interrupt Lower Address Register ________________________ 34 Table 5-32: Message Signaled Interrupt Upper Address Register ________________________ 34 Table 5-33: Message Signaled Interrupt Message Data Register ________________________ 34 Table 5-34: Message Signaled Interrupt Masked Bits Register __________________________ 34 Table 5-35: Message Signaled Interrupt Pending Bits Register _________________________ 34 Table 5-36: MSI-X Capability Register Summary _____________________________________ 34 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 9 of 66 Table 5-37: MSI-X Identifier Register ______________________________________________ 35 Table 5-38: MSI-X Control Register _______________________________________________ 35 Table 5-39: MSI-X Table Offset Register ___________________________________________ 35 Table 5-40: MSI-X Pending Bit Array Offset Register _________________________________ 35 Table 5-41: PCI Express Capability Register Summary________________________________ 36 Table 5-42: PCI Express Capability ID Register _____________________________________ 36 Table 5-43: PCI Express Capabilities Register ______________________________________ 36 Table 5-44: PCI Express Device Capabilities Register ________________________________ 36 Table 5-45: PCI Express Device Control Register ____________________________________ 37 Table 5-46: PCI Express Device Status Register _____________________________________ 37 Table 5-47: PCI Express Device Link Capabilities Register ____________________________ 37 Table 5-48: PCI Express Device Link Control Register ________________________________ 38 Table 5-49: PCI Express Device Link Status Register _________________________________ 38 Table 5-50: PCI Express Device Capabilities 2 Register _______________________________ 38 Table 5-51: PCI Express Device Control 2 Register __________________________________ 39 Table 5-52: PCI Express Device Status 2 Register ___________________________________ 39 Table 5-53: PCI Express Link Capabilities 2 Register _________________________________ 39 Table 5-54: PCI Express Link Control 2 Register _____________________________________ 39 Table 5-55: PCI Express Link Status 2 Register _____________________________________ 40 Table 5-56: Advanced Error Reporting Capability Register Summary _____________________ 40 Table 5-57: AER Capability ID Register ____________________________________________ 40 Table 5-58: AER Uncorrectable Error Status Register _________________________________ 41 Table 5-59: AER Uncorrectable Error Mask Register _________________________________ 41 Table 5-60: AER Uncorrectable Error Severity Register _______________________________ 42 Table 5-61: AER Correctable Error Status Register ___________________________________ 42 Table 5-62: AER Correctable Error Mask Register ___________________________________ 42 Table 5-63: AER Capabilities and Control Register ___________________________________ 43 Table 5-64: AER Header Log Register _____________________________________________ 43 Table 5-65: AER TLP Prefix Log Register __________________________________________ 43 Table 5-66: Secondary PCI Express Capability Register Summary ______________________ 44 Table 5-67: Secondary PCI Express Capability ID Register ____________________________ 44 Table 5-68: PCI Express Link Control 3 Register ____________________________________ 45 Table 5-69: PCI Express Lane Error Status Register __________________________________ 45 Table 5-70: PCI Express Lane 0 Equalization Register ________________________________ 45 Table 5-71: PCI Express Lane 1 Equalization Register _______________________________ 45 Table 5-72: PCI Express Lane 2 Equalization Register ________________________________ 45 Table 5-73: PCI Express Lane 3 Equalization Register ________________________________ 45 Table 5-74: Device Serial Number Capability Register Header _________________________ 46 Table 5-75: Serial Number Register Header (offset 0x4/0x8) ___________________________ 46 Table 5-76: Power Budgeting Extended Capability Header _____________________________ 46 Table 5-77: Data Register ______________________________________________________ 46 Table 5-78: Power Budget Capability Register ______________________________________ 46 Table 5-79: LTR Extended Capability Header _______________________________________ 47 Table 5-80: LTR Max Snoop latency Register _______________________________________ 47 Table 5-81: LTR Max No Snoop latency Register ____________________________________ 47 Table 5-82: L1 Substates Extended Capability Header ________________________________ 47 Table 5-83: L1 Substates Capability Register _______________________________________ 47 Table 5-84: L1 Substates Control1 Register ________________________________________ 48 Table 5-85: L1 Substates Control2 Register ________________________________________ 48 Table 5-86: Register Summary __________________________________________________ 48 Table 5-87: Controller Capabilities ________________________________________________ 49 Table 5-88: Version ___________________________________________________________ 49 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 10 of 66 Table 5-89: Interrupt Mask Set __________________________________________________ 49 Table 5-90: Interrupt Mask Clear _________________________________________________ 50 Table 5-91: Controller Configuration ______________________________________________ 50 Table 5-92: Controller Status____________________________________________________ 50 Table 5-93: Admin Queue Attributes ______________________________________________ 51 Table 5-94: Admin Submission Queue Base Address _________________________________ 51 Table 5-95: Admin Completion Queue Base Address _________________________________ 51 Table 5-96: Submission Queue Tail y Doorbell ______________________________________ 51 Table 5-97: Completion Queue Head y Doorbell _____________________________________ 51 Table 6-1: Opcode for Admin Commands __________________________________________ 52 Table 6-2: Identify Controller Data Structure ________________________________________ 53 Table 6-3: Identify Power State Descriptor Data Structure _____________________________ 56 Table 6-4: Identify Namespace Data Structure ______________________________________ 56 Table 6-5: LBA Format 0 Data Structure ___________________________________________ 59 Table 6-5: LBA Format 1 Data Structure ___________________________________________ 59 Table 6-5: LBA Format 2 Data Structure ___________________________________________ 59 Table 6-5: LBA Format 3 Data Structure ___________________________________________ 59 Table 6-6: Opcode for NVM Express I/O Commands _________________________________ 59 Table 6-7: SMART/Health Information Log _________________________________________ 61 Table 6-7: Vital Product Data (VPD) Structure _______________________________________ 62 Table 7-1: B00 to B15 __________________________________________________________ 64 Table 7-1: Supported Operating Systems __________________________________________ 65 Table 8-1: Product Compliance Certifications _______________________________________ 66 Table of Figures Figure 2-1: SSD usage in SR-IOV environments ______________ Error! Bookmark not defined. Figure 3-1: SDD Dimensions ____________________________________________________ 23 Figure 3-2: SDD Dimensions, Side View ___________________________________________ 24 Figure 3-3: Dimension Details for 2.5 inch connector _________________________________ 25 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 11 of 66 1 Introduction Viking’s 2.5 inch SSD presents outstanding performance with instant responsiveness to the host system, by applying the Peripheral Component Interconnect Express (PCIe) 3.0 interface standard, as well as highly efficient Non-Volatile Memory Express (NVMe) Protocol. The Viking’s 2.5 inch SSD delivers wide bandwidth of up to 3300 MB/s for sequential read speed and up to 2950 MB/s for sequential write speed under 23W of power. With the help of Toggle 2.0 NAND Flash interface, the Viking’s 2.5 inch SSD delivers random performance of up to 800K IOPS for random 4KB read and up to 160K IOPS for random 128KB write in the sustained state. By combining the enhanced reliability of NAND Flash memory silicon with NAND Flash management technologies, the Viking’s 2.5 inch SSD delivers the extended endurance suitable for enterprise applications, in 2.5 inch form factor. In addition, the Viking’s 2.5 inch SSD supports Power Loss Protection that can guarantee that data issued by the host system are written to the storage media without any loss in the event of sudden power off or sudden power failure. Inrush current handler can protect the internal components from the electrical and physical damages. 1.1 Features The SSD delivers the following features:  Native-PCIe SSD for enterprise application  LPDDR3 DRAM Buffer Memory  PCI Express Gen3: Dual port X4 lanes  Compliant with PCI Express Base Specification Rev. 3.0  Compliant with NVM Express Specification Rev.1.1a  Enhanced Power-Loss Data Protection  End-to-End Data Protection  Support SSD Enhanced S.M.A.R.T. Feature Set  Static and Dynamic Wear Leveling  RoHS / Halogen-Free Compliant Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 12 of 66 1.2 PCIE Interface    PCI Express Gen3: Compliant with PCI Express Base Specification Rev. 3.0 Compliant with NVM Express Specification Rev.1.1a For a list of supported commands and other specifics, please see Chapter 5. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 13 of 66 2 Product Specifications 2.1 Capacity and LBA count User Capacity (GB) Max LBA Count 800GB 1.6TB 3.2TB 6.4TB 1,562,824,367 3,125,627,567 6,251,233,967 12,502,446,767 Notes: 1. Per www.idema.org, LBA1-03 spec. The max. LBA shown in Table represents the total user addressable sectors in LBA mode and calculated by IDEMA rule. LBA counts = (97,696,368) + (1,953,504 * (Advertised Capacity in GBytes – 50)) 2. Gigabyte (GB) = 1,000,000,000 Bytes, 1 Sector = 512Bytes 3. Capacity shown in Tablerepresents the total usable capacity of the SSD which may be less than the total physical capacity. A certain area in physical capacity, not in the area shown to the user, might be used for the purpose of NAND flash management. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 14 of 66 2.2 Performance Table 2-1: Maximum Sustained Read and Write Bandwidth Access Type Sequential Read, 256K, MB/s Sequential Write, 256K, MB/s 800 GB Up to 3300 Up to 1000 1600 GB Up to 3300 Up to 2200 3200 GB Up to 3300 Up to 3000 6400 GB Up to 3300 Up to 3300 Notes: 1. Based on PCI Express Gen3 x4, Random performance measured using FIO 2.1.3 in Linux RHEL 6.5(Kernel 2.6.32) with queue depth 32 by 4 workers and Sequential performance with queue depth 32 by 1 worker. Actual performance may vary depending on use conditions and environment. 2. Refer to Application Note AN0006 for Viking SSD Benchmarking Methodology. Table 2-2: Maximum Random Read and Write Input/Output Operations per Second (IOPS) Access Type Read, 4K, IOPS Write, 4K, IOPS Read, 8K, IOPS Write, 8K, IOPS 800 GB Up to 700K Up to 70K Up to 390K Up to 36K 1600 GB Up to 750K Up to 130K Up to 430K Up to 70K 3200 GB Up to 800K Up to 160K Up to 430K Up to 95K 6400 GB Up to 800K Up to 160K Up to 430K Up to 95K Notes: 1. Based on PCI Express Gen3 x4, Random performance measured using FIO 2.1.3 in Linux RHEL 6.5(Kernel 2.6.32) with queue depth 32 by 4 workers and Sequential performance with queue depth 32 by 1 worker. Actual performance may vary depending on use conditions and environment. 2. Refer to Application Note AN0006 for Viking SSD Benchmarking Methodology 2.3 Timing / Latency Table 2-3: Timing Specifications Type (Queue Depth = 1) Random Read/Write Latency Sequential Read/Write Latency Power On Ready (POR), Drive Ready Time, 3840 GB 800, 1600, 3200, 6400 GB 90/30 µs 115/125 µs 2 sec Notes: 1. The random latency is measured by using FIO 2.1.3 in Linux RHEL 6.5(Kernel 2.6.32) and 4KB transfer size with queue depth 1 by 1 worker 2. The sequential latency is measured by using FIO 2.1.3 in Linux RHEL 6.5(Kernel 2.6.32) and 4KB transfer size with queue depth 1 by 1 worker Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 15 of 66 2.4 Quality of Service (QoS) Table 2-4: Quality of Service (QoS) Quality of Service (99%) Unit 800GB 1.6TB 3.2TB 6.4TB Read(4KB)(QD=1) us 160 160 170 170 Write(4KB)(QD=1) us 80 80 90 100 Read(4KB)(QD=128) us 500 420 420 420 Write(4KB)(QD=128) Quality of Service (99.99%) us 3500 2500 2500 2500 Unit 800GB 1.6TB 3.2TB 6.4TB Read(4KB)(QD=1) us 180 180 300 300 Write(4KB)(QD=1) us 150 250 500 500 Read(4KB)(QD=128) us 780 550 570 570 Write(4KB)(QD=128) us 7300 4000 4000 4000 Notes: 1. QoS is measured using Fio 2.1.3 (99 and 99.99%) in Linux RHEL 6.5 (Kernel 2.6.32) with queue depth 1, 32 on 4KB random read and write. 2. QoS is measured as the maximum round-trip time taken for 99 and 99.99% of commands to host . Table 2-5: Operating Voltage IOPS Consistency 1, 2 IOPS Consistency Unit 800GB 1.6TB 3.2TB 6.4TB Random Read (4 KB) % 98 94 98 88 Random Write (4 KB) % 90 88 92 98 Random Read (8 KB) % 98 90 90 90 Random Write (8 KB) % 90 90 90 90 NOTE: 1) IOPS consistency measured using FIO with queue depth 128. 2) IOPS Consistency (%) = (IOPS in the 99.9% slowest 1-second interval)/(average IOPS during the test). 2.5 Electrical Characteristics 2.5.1 Absolute Maximum Ratings Values shown are stress ratings only. Functional operation outside normal operating values is not implied. Extended exposure to absolute maximum ratings may affect reliability. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 16 of 66 2.5.2 Supply Voltage The operating voltage is 12V Table 2-6: Operating Voltage Description 800GB/1.6/3.2/6.4TB Operating Voltage 800GB/1.6/3.2/6.4TB 12V 2 10% 50ms/1ms 12V Rise time (Max/Min) 12V Fall time (Max/Min) 4 5s/1ms 300 mV pp 10Hz – 100 KHz 50 mV pp 100KHz – 20 MHz 12V Noise level 3 10% 3.3Vaux 3.3Vaux Rise time (Max/Min) 3.3Vaux Fall time 4 (Max/Min) 50ms/1ms 5s/1ms 300 mV pp 10Hz – 100 KHz 50 mV pp 100KHz – 20 MHz 3.3Vaux Noise level Notes: 1) The components inside SSD were designed to endure the range of voltage fluctuations, which might be induced by the host system. 2) For 12V operating voltage, the minimum allowable is 10.8V and the maximum 13.2V. 2.5.3 Power Consumption The SSD is implemented in standardized 2.5-inch form factor and gets primary 12V power as well as auxiliary 3.3V (3.3Vaux) power through the indicated pins (#P13~15 for 12V and #E3 for 3.3Vaux in SFF-8639 connector plug) from the host system. Table 2-7: Typical Power Consumption at 12V Power Mode 2 Active 3 Idle Off 800GB 1.6TB 3.2TB 6.4TB Read 16W 16W 16W 17W Write 15W 21W 21W 21W 7.5W 7.5W 7.5W 0W 7.5W Notes: 1) Power consumption was measured in the 12V power pins (#P13~#P15) of the connector plug in SSD. The active and idle power is defined as the highest averaged power value, which is the maximum RMS average value over 100 ms duration. 2) The measurement condition for active power is assumed for 100% sequential read or write. 3) The idle state is defined as the state that the host system can issue any commands into SSD at any time. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 17 of 66 Inrush Current 800GB/1.6/3.2/6.4TB 1 at 12V 1.8A Notes: 1) The measurement value of inrush current is also compatible with the standard specification of “Enterprise SSD Form Factor Version 1.0a” released by SSD Form Factor Working Group 2.6 Environmental Conditions 2.6.1 Temperature and Altitude Table 2-8: Temperature and Altitude Related Specifications Conditions Commercial 1 Temperature- Case Humidity (noncondensing) Operating 0 to 70°C Shipping -40 to 85°C Storage -40 to 85°C - 5 to 95% 5 to 95% Notes: 1. Tc is measured at the surface of NAND Flash package 2.6.2 Shock and Vibration SSD products are tested in accordance with environmental specification for shock and vibration. Table 2-9: Shock and Vibration Specifications 800GB/1.6/3.2/6.4TB 1 Shock 2 Vibration Non-operating Non-operating 1,500G 20 Gpeak (10~2,000Hz, Sweep sine) NOTE: 1) Shock specifications assume that SSD shall be mounted with screws when input vibration is applied. Vibration may be applied in 3 axes (x, y and z) with a half sine waveform of 0.5ms duration in non-operating condition. 2) Vibration specifications assume that SSD shall be mounted with screws when input vibration is applied. The input vibration may be applied in 3 axes (x, y and z) and lasts during 15 minutes per axis. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 18 of 66 2.6.3 Electromagnetic Immunity 2.5 inch is an embedded product for host systems and is designed not to impair with system functionality or hinder system EMI/FCC compliance. 2.7 Reliability Table 2-10: Reliability Specifications Parameter Uncorrectable Bit Error Rate (UBER) MTBF Description 1 sector per 10 bits read 2,000,000 hours Read Endurance Write Endurance (Petabytes Written) Drive Write per day 17 Unlimited 800GB 1600GB 3200GB 6400GB 7.3 PBW 14.6 PBW 29.2 TBW 58.4 TBW Data retention 5 DWPD over 5 years > 90 days at NAND expiration Notes: 1. The reliability specification follows JEDEC standards JESD218A and JESD219A 2. TBW=(GB capacity x DWPD x 365 x years)/1000 2.8 Data Security 2.8.1 Power Loss Protection By using internal back-up power technology, the Viking SSD supports power loss protection feature to guarantee the reliability of data requested by the host system. When power is unpredictably lost, the SSD can detect automatically this abnormal situation and transfer all user data and meta-data cached in DRAM into the Flash media during any SSD operations. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 19 of 66 2.9 Hot Plug Support 2.9.1 Power Loss Protection By using internal back-up power technology, the Samsung SSD supports power loss protection (PLP) feature to guarantee the reliability of data requested by the host system. When power is unpredictably lost, SSD can detect automatically this abnormal situation and transfer all user data and meta-data cached in DRAM into the Flash media during any SSD operations. 2.9.2 Inrush Current Protection When the SSD plugs in the backplane of host system, the significant amount of current is induced through 12V power rail. The SSD has protection circuitry including a set of resisters and capacitors to alleviate the impact by inrush current through 12V power. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 20 of 66 2.10 Enterprise Class Storage Features 2.10.1 Dual Port Capability IT and data center managers need features that can provide access to storage data without interruptions. Viking has taken this need into consideration by including a key feature that provides access by smartly using dualport PCIe® (PCI Express®) SSDs to get the most out of highperformance enterprise applications. Viking has enabled this feature which provides the ability to create two fault domains and increases availability, providing non-interrupt service for accessing storage data. Even if a failure occurs in one of the paths to a port, preventing access along that path, the device is still accessible using the second port. The SSD provides virtually non-stop service with this dual-port feature support. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 21 of 66 2.10.2 Multi-namespace support The SSD supports multiple namespaces, where a single SSD can be partitioned into multiple hardware partitions. A namespace can be assigned to multiple hosts or dedicated to a single host. The SSD supports up to 32 multiple namespaces. 2.10.3 Remote Health Monitoring This SSD provides a remote health-monitoring feature by an SSD Toolkit. The SSD Toolkit is a Samsung proprietary software designed to help users with easy-to-use SSD management and diagnostic features for server and data center usage. The CLI (command line interface) tool currently supports NVMe SSDs and supports Linux®. The Samsung version of the SSD Toolkit is available from the Samsung SSD website at http://www.samsung.com/global/business/semiconductor/minisite/SSD/global/html/ support/server_downloads.html Remote health monitoring features include: • Health monitoring: Provides vital drive status information and supports users to update firmware, measure drive performance, initialize drives, calculate drive lifetime and more. • Remote health monitoring for FA (failure analysis): Provides a smart way for resolving field issues by the remote health monitoring feature. This way of issue handling reduces turnaround time compared to the traditional way of handling the issue, such as dispatching an engineer, and provides quicker resolution. The customer can get the initial resolution in two steps: first by running the SSD Toolkit and second by sending the debug information back to the factory and getting the resolution effectively. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 22 of 66 3 Mechanical Information 3.1 Dimensions Table 3-1: Physical Dimensions Height / Thickness Width Length Dimensions 15.00+0.00, -0.50 69.85±0.25 100.20±0.25 Units mm mm mm Figure 3-1: SDD Dimensions Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 23 of 66 15.00+0.00, -0.50 mm Figure 3-2: SDD Dimensions, Side View Notes: 1. All dimensions are in millimeter. General tolerance is ± 0.15. Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 24 of 66 Note: SFF-8639 combo (SATA, SAS, PCIe) standard connector Figure 3-3: Dimension Details for 2.5 inch connector Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 25 of 66 3.2 2.5 inch SSD Weight Table 3-2: 2.5 inch SSD weight Weight Unit of measure Up to 170g Grams 4 Pin and Signal Descriptions 4.1 Signal and Power Description Tables Table 4-1: 2.5 inch PCIE Connector Pinouts Pin # Assignment Description Pin # Assignment S1 Not Used Float E7 RefClk0+ S2 Not Used E8 RefClk0- Description PCIe Reference Clock + (primary port A) PCIe Reference Clock - (primary port A) S3 Not Used E9 GND Ground S4 Not Used E10 PETp0 PCIe Transmit+ (lane 0) S5 Not Used E11 PETn0 PCIe Transmit- (lane 0) S6 Not Used E12 GND Ground S7 Not Used E13 PERn0 PCIe Receive- (lane 0) E1 REFCLK1+ E14 PERp0 PCIe Receive+ (lane 0) E2 REFCLK1- E15 GND Ground E3 3.3V AUX Ground PCIe Reference Clock + (dual port, port B) PCIe Reference Clock - (dual port, port B) Auxiliary Power (for SMBus access) E16 Not Used E4 ePERST1# PCIe Reset (dual port, port B) S8 Not Used E5 ePERST0# PCIe Reset (primary port A) S9 Not Used E6 Not Used S10 Not Used P1 Not Used S11 Not Used P2 Not Used S12 Not Used P3 Not Used S13 Not Used P4 IfDet # Interface Detect S14 Not Used P5 GND Ground S15 Not Used P6 GND Ground S16 GND Ground P7 Not Used S17 PETp1 PCIe Transmit+ (lane 1) P8 Not Used S18 PETn1 PCIe Transmit- (lane 1) P9 Not Used S19 GND Ground P10 PRSNT # S20 PERn1 PCIe Receive- (lane 1) Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Ground Presence Ground Ground Ground 3/26/2018 Viking Technology Page 26 of 66 Pin # Assignment Description Pin # Assignment Description P11 Activity Drive Active S21 PERp1 PCIe Receive+ (lane 1) P12 GND Ground S22 GND Ground P13 12 V Primary Power S23 PETp2 PCIe Transmit+ (lane 2) P14 12 V Primary Power S24 PETn2 PCIe Transmit- (lane 2) P15 12 V Primary Power S25 GND Ground S26 PERn2 PCIe Receive- (lane 2) S27 PERp2 PCIe Receive+ (lane 2) S28 GND Ground E17 PETp3 PCIe Transmit+ (lane 3) E18 PETn3 PCIe Transmit- (lane 3) E19 GND Ground E20 PERn3 PCIe Receive- (lane 3) E21 PERp3 PCIe Receive+ (lane 3) E22 GND Ground E23 SMClk SMBus Clock E24 SMDat SMBus Data E25 DualPortEn# Dual Port PCIe enable Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 27 of 66 5 PCIe and NVM Express Registers 5.1 PCI Express Registers 5.1.1 PCI Register Summary Table 5-1: PCI Register Summary Start Address End Address Name Type 00h 3Fh PCI Header PCI Capability 40h 47h PCI Power Management Capability PCI Capability 50h 67h MSI Capability PCI Capability 70h A3h PCI Express Capability PCI Capability B0h BBh MSI-X Capability PCI Capability 100h 12Bh Advanced Error Reporting Capability PCI Capability D0h D4h VPD Capability PCI Capability 148h 157h Device Serial No Capability PCI Capability 158h 167h Power Budgeting Capability PCI Capability 168h 17Bh Secondary PCI Express Header PCI Capability 188h 18Fh Latency Tolerance Reporting (LTR) PCI Capability 190h 19Fh L1 Substates Capability Register PCI Capability 5.1.2 PCI Header Registers Table 5-2: PCI Header Register Summary Start Address End Address Symbol Description 00h 03h ID Identifiers 04h 05h CMD Command Register 06h 07h STS Device Status 08h 08h RID Revision ID 09h 0Bh CC Class Codes 0Ch 0Ch CLS Cache Line Size 0Dh 0Dh MLT Master Latency Timer 0Eh 0Eh HTYPE Header Type 0Fh 0Fh BIST Built in Self Test Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 28 of 66 Start Address End Address Symbol Description 10h 13h MLBAR (BAR0) Memory Register Base Address (lower 32-bit) 14h 17h MUBAR (BAR1) Memory Register Base Address (upper 32-bit) 18h 1Bh IDBAR (BAR2) Index/Data Pair Register Base Address 1Ch 1Fh BAR3 Reserved 20h 23h BAR4 Reserved 24h 27h BAR5 Reserved 28h 2Bh CCPTR CardBus CIS Pointer 2Ch 2Fh SS Subsystem Identifiers 30h 33h EROM Expansion ROM Base Address 34h 34h CAP Capabilities Pointer 35h 3Bh R Reserved 3Ch 3Dh INTR Interrupt Information 3Eh 3Eh MGNT Minimum Grant 3Fh 3Fh MLAT Maximum Latency Table 5-3: Identifier Register Bits 31:16 0:15 Type RO RO Default Value A802h 144Dh Description Device ID Vendor ID Default Value 0 0 0 0 0 0 0 0 0 0 0 0 Description Reserved Interrupt Disable Fast Back-to-Back Enable (N/A) SERR# Enable (N/A) Zero value Parity Error Response Enable VGA Palette Snooping Enable (N/A) Memory Write and Invalidate Enable (N/A) Special Cycle Enable (N/A) Bus Master Enable Memory Space Enable I/O Space Enable Table 5-4: Command Register Bits 15:11 10 9 8 7 6 5 4 3 2 1 0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RO RW RO RW RO RW RO RO RO RW RW RW 3/26/2018 Viking Technology Page 29 of 66 Table 5-5: Device Status Register Bits 15 14 13 12 11 10:9 8 7 6 5 4 3 2:0 Type RW1C RW1C RW1C RW1C RW1C RO RW1C RO RO RO RO RO RO Default Value 0 0 0 0 0 0 0 0 0 0 1 0 0 Description Detected Parity Error N/A Received Master Abort Received Target Abort Signaled Target Abort N/A Master Data Parity Error Detected N/A Reserved N/A Capabilities List INTx Status Reserved Table 5-6: Revision ID Register Bits Type 7:00 RO Default Value 1 Description Controller Hardware Revision ID Table 5-7: Class Code Register Bits Type 23:16 15:08 7:00 RO RO RO Default Value 1h 8h 2h Description Base Class Code Sub Class Code Programming Interface Table 5-8: Cache Line Size Register Bits 7:0 Type RW Default Value 0h Description N/A Table 5-9: Master Latency Timer Register Bits Type Default Value Description 7:00 RO 0 N/A Table 5-10: Header Type Register Bits Type Default Value Description 7:00 RO 0 N/A Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com 3/26/2018 Viking Technology Page 30 of 66 Table 5-11: Built-in Self Test Register Bits Type Default Value Description 7:00 RO 0 N/A Table 5-12: Memory Register Base Address Lower 32-bits (BAR0) Register Bits 31:04 3 2:1 0 Type RW RO RO RO Default Value 0 0 2 0 Description Base Address Pre-Fetchable Address Type (64-bit) Memory Space Indicator (MEMSI) Table 5-13: Memory Register Base Address Upper 32-bits (BAR1) Register Bits 31:0 Type RO Default Value 0 Description Base Address Table 5-14: Index/Data Pair Register Base Address (BAR2) Register Bits 31:0 Type RO Default Value 0 Description Base Address Default Value 0 Description Base Address Table 5-15: BAR3 Register Bits 31:0 Type RO Table 5-16: Vendor Specific BAR4 Register Bits 31:0 Type RO Default Value 0 Description Base Address Table 5-17: Vendor Specific BAR5 Register Bits 31:0 Type RO Default Value 0 Description Base Address Table 5-18: Subsystem Identifier Register Bits 31:16 15:0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RO RO Default Value A801 144D Description Subsystem ID Subsystem Vendor ID 3/26/2018 Viking Technology Page 31 of 66 Table 5-19: Expansion ROM Register Bits 31:11 10:1 0 Type RW RO RW Default Value 0 0 0 Description Expansion ROM Base Address Reserved Expansion ROM Enable/Disable Table 5-20: Capabilities Pointer Register Bits Type Default Value 7:0 RO 40h Description Capability Pointer (Points to PCI Power Management Capability Offset) Table 5-21: Interrupt Information Register Bits 15:8 7:0 Type RO RW Default Value 01 FF Description Interrupt Pin Interrupt Line Table 5-22: Minimum Grant Register Bits 31:0 Type RO Default Value 0 Description Base Address Table 5-23: Maximum Latency Register Bits 31:0 Type RO Default Value 0 Description Base Address 5.1.3 PCI Power Management Registers Table 5-24: PCI Power Management Capability Register Summary Start Address 40h 41h 42h 44h 46h 47h End Address 40h 41h 43h 45h 46h 47h Symbol PID Next cap ptr PMC PMCS PMCSR_BSE Data Description PCI Power Management Capability ID Next cap ptr PC Power Management Capabilities PCI Power Management Control and Status PMCSR_BSE Bridge Extensions Data Table 5-25: PCI Power Management Capability ID Register Bits 15:08 7:00 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RO RO Default Value 50h 1h Description Next Capability Capability ID 3/26/2018 Viking Technology Page 32 of 66 Table 5-26: PCI Power Management Capability Register Bits 15:11 10 9 8:6 5 4 3 2:0 Type RO RO RO RO RO RO RO RO Default Value 0 0 0 0 0 0 0 3h Description N/A D2 Support D1 Support N/A Device Specific Initialization Reserved PME Clock Version (Support for revision 1.2) Table 5-27: PCI Power Management Control and Status Register Bits 31:24 23 22 21:16 15 14:13 12:09 8 7:04 3 2 1:00 Type RO RO RO RsvdP RW1CS RO RO RWS RsvdP RO RsvdP RW Default Value 0 0 0 0 0 0 0 0 0 1 0 0 Description data register Bus power/Clock enable B2, B3 support Reserved PME Status N/A N/A PME Enable Reserved No Soft Reset Reserved Power State 5.1.4 Message Signaled Interrupt Registers Table 5-28: Message Signaled Interrupt Capability Register Summary Start Address 50h 52h End Address 51h 53h Symbol MID MC 54h 57h MA 58h 5Ch 60h 64h 5Bh 5Dh 63h 67h MUA MD MMASK MPEND Description Message Signaled Interrupt Capability ID Message Signaled Interrupt Message Control Message Signaled Interrupt Message Address Message Signaled Interrupt Upper Address Message Signaled Interrupt Message Data Message Signaled Interrupt Mask Bits Message Signaled Interrupt Pending Bits Table 5-29: Message Signaled Interrupt Capability ID Register Bits 15:08 7:0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RO RO Default Value 70h 05h Description Next Capability Capability ID 3/26/2018 Viking Technology Page 33 of 66 Table 5-30: Message Signaled Interrupt Control Register Bits 15:9 8 7 6:4 3:1 0 Type RsvdP RO RO RW RO RW Default Value 0 0 1h 0h 3h 0h Description Reserved Per Vector Masking Capable 64-bit Address Capable Multiple Message Enable Multiple Message Capable MSI Enable Table 5-31: Message Signaled Interrupt Lower Address Register Bits 31:2 1:0 Type RW RO Default Value 0 0 Description Address Reserved Table 5-32: Message Signaled Interrupt Upper Address Register Bits 31:0 Type RW Default Value 0 Description Upper Address Table 5-33: Message Signaled Interrupt Message Data Register Bits 16:31 0:15 Type RsvdP RO Default Value 0 0 Description Reserved Data Table 5-34: Message Signaled Interrupt Masked Bits Register Bits 31:0 Type RW Default Value 0 Description Mask Bits Table 5-35: Message Signaled Interrupt Pending Bits Register Bits 31:0 Type RO Default Value 0 Description Pending Bits 5.1.5 MSI-X Registers Table 5-36: MSI-X Capability Register Summary Start Address B0h B2h B4h B8h Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com End Address B1h B3h B7h BBh Symbol MXID MXC MTAB MPBA Description MSI-X Capability ID MSI-X Message Control MSI-X Table Offset and Table BIR MSI-X PBA Offset and PBA BIR 3/26/2018 Viking Technology Page 34 of 66 Table 5-37: MSI-X Identifier Register Bits 15:8 7:0 Type RO RO Default Value 00h 11h Description Next Capability Capability ID Table 5-38: MSI-X Control Register Bits 15 14 13:11 10:0 Type RW RW RsvdP RO Default Value 0 0 0 08h Description MSI-X Enable Function Mask Reserved Table Size Table 5-39: MSI-X Table Offset Register Bits 31:3 2:0 Type RO RO Default Value 300h 0 Description Table Offset Table BIR Table 5-40: MSI-X Pending Bit Array Offset Register Bits 31:3 2:0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RO RO Default Value 200h 0 Description Pending Bit Array Offset Pending Bit Array BIR 3/26/2018 Viking Technology Page 35 of 66 5.1.6 PCI Express Capability Registers Table 5-41: PCI Express Capability Register Summary Start Address 70h 72h 74h 78h 7Ah 7Ch 80h 82h 94h 98h 9Ah 9Ch A0h A2h End Address 71h 73h 77h 79h 7Bh 7Fh 81h 83h 97h 99h 9Bh 9Fh A1h A3h Symbol PXID PXCAP PXDCAP PXDC PXDS PXLCAP PXLC PXLS PXDCAP2 PXDC2 PXDS2 PXLCAP2 PXLC2 PXLS2 Description PCI Express Capability ID PCI Express Capabilities PCI Express Device Capabilities PCI Express Device Control PCI Express Device Status PCI Express Link Capabilities PCI Express Link Control PCI Express Link Status PCI Express Device Capabilities 2 PCI Express Device Control 2 PCI Express Device Status 2 PCI Express Link Capabilities 2 PCI Express Link Control 2 PCI Express Link Status 2 Table 5-42: PCI Express Capability ID Register Bits 15:8 7:0 Type RO RO Default Value B0h 10h Description Next Pointer (MSI-X Capability) Capability ID Table 5-43: PCI Express Capabilities Register Bits 15:14 13:9 8 7:4 3:0 Type RsvdP RO HwInit RO RO Default Value 0 0 0 0 2h Description Reserved Interrupt Message Number N/A Device/Port Type Capability Version Table 5-44: PCI Express Device Capabilities Register Bits 31:29 28 27:26 25:18 17:16 15 14:12 11:9 8:6 5 4:3 Type RsvdP RO RO RO RO RO RO RO RO RO RO Default Value 0 1 0 0 0 1 0 7h 7h 0 0 2:0 RO 0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Description Reserved Function Level Reset Capability Captured Slot Power Limit Scale Captured Slot Power Limit Value Reserved Role-based Error Reporting Reserved Endpoint L1 Acceptable Latency Endpoint L0 Acceptable Latency Extended Tag Field Supported Phantom Functions Supported Max Payload Size Supported (128 byte payload) 3/26/2018 Viking Technology Page 36 of 66 Table 5-45: PCI Express Device Control Register Bits 15 14:12 11 10 9 8 7:5 4 3 2 1 0 Type RW RW RW RWS RW RW RW RW RW RW RW RW Default Value 0 2h 1 0 0 0 0 1 0 0 0 0 Description Initiate Function Level Reset Max Read Request Size Enable No Snoop Aux Power PM Enable (N/A) Phantom Functions Enable (N/A) Extended Tag Enable Max Payload Size Enable Relaxed Ordering (N/A) Unsupported Request Reporting Enable Fatal Error Reporting Enable Non-Fatal Error Reporting Enable Correctable Error Reporting Enable Table 5-46: PCI Express Device Status Register Bits 15:06 5 4 3 2 1 0 Type RsvdP RO RO RW1C RW1C RW1C RW1C Default Value 0 0 1 0 0 0 0 Description Reserved Transactions Pending Aux Power Detected Unsupported Request Detected Fatal Error Detected Non-Fatal Error Detected Correctable Error Detected Table 5-47: PCI Express Device Link Capabilities Register Bits 31:24 23 22 21 Type HwInit RsvdP HwInit RO Default Value 0 (Port 0) 0 1h 0 20 RO 0 19 18 17:15 14:12 11:10 9:4 3:0 RO RO RO RO RO RO RO 0 1 6 6h 0 4h (x4 link) 3h Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Description Port Number Reserved ASPM Optionality Compliance Link Bandwidth Notification Capability (N/A) Data Link Layer Link Active Reporting Capable (N/A) Surprise Down Error Reporting Capable (N/A) Clock Power Management L1 Exit Latency L0s Exit Latency Active State Power Management Support Maximum Link Width Supported Link Speeds 3/26/2018 Viking Technology Page 37 of 66 Table 5-48: PCI Express Device Link Control Register Bits 15:12 11 10 9 8 7 6 5 4 3 2 1:00 Type RsvdP RsvdP RsvdP RsvdP RW RW RW RsvdP RsvdP Root Ports (RO) End Points & Bridges (RW) Switch Ports (RO) RsvdP RW1C Default Value 0 0 0 0 0 0 0 0 0 0 Description Reserved Link Autonomous Bandwidth Interrupt Enable Link Bandwidth Management Interrupt Enable Hardware Autonomous Width Disable Enable Clock Power Management (N/A) Extended Sync Common Clock Configuration Retrain Link Link Disable Read Completion Boundary (N/A) 0 0 Reserved Active State Power Management Control Table 5-49: PCI Express Device Link Status Register Bits 15 14 13 12 Type RW1C RW1C RO HwInit Default Value 0h 0 0 1 11 RO 0 10 9:4 3:0 RO RO RO 0 4h 3h Description Link Autonomous Bandwidth Status Link Bandwidth Management Status Data Link Layer Link Active Slot Clock Configuration Link Training (1: Link training in progress;0: No link training in progress) (Non-standard) Reserved Negotiated Link Width Current Link Speed Table 5-50: PCI Express Device Capabilities 2 Register Bits 31:24 23:22 21 20 19:18 17:14 13:12 11 10 9 8 7 6 5 4 Type RsvdP HwInit HwInit RO HwInit RO RO RO HwInit RO RO RO RO RO RO Default Value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 3:0 HwInit 0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Description Reserved Max End-End TLP Prefixes (N/A) End-End TLP Prefix Supported (N/A) Extended Format Field Supported (N/A) OBFF Supported (N/A) Reserved TPH Completer Supported (N/A) Latency Tolerance Reporting Supported (N/A) No RO-enabled PR-PR Passing (N/A) 128-bit CAS Completer Supported (N/A) 64-bit Atomic Op Completer Supported (N/A) 32-bit Atomic Op Completer Supported (N/A) Atomic Op Routing Supported (N/A) ARI Forwarding Supported (N/A) Completion Timeout Disable Supported Completion Timeout Ranges Supported (50us to 200ms) 3/26/2018 Viking Technology Page 38 of 66 Table 5-51: PCI Express Device Control 2 Register Bits 15 14:13 12:11 Type RsvdP RW/RsvdP RsvdP Default Value 0 0 0 10 RW/RsvdP 0 9 8 7 6 5 4 RW RW RW RW RW RW 0 0 0 0 0 0 3:0 RW 0 Description End-to-end TLP Prefix Blocking (N/A) OBFF Enable (N/A) Reserved Latency Tolerance Reporting Mechanism Enable (N/A) IDO Completion Enable IDO Request Enable AtomicOp Egress Blocking AtomicOp Requester Enable ARI Forwarding Enable Completion Timeout Disable Completion Timeout Value (0h - 50 ȝs; 1h - 100 ȝs; 2h - 2 ms; 5h - 50 ms; 6h - 200 ms; others reserved ) Table 5-52: PCI Express Device Status 2 Register Bits 15:0 Type RsvdZ Default Value 0 Description Reserved Table 5-53: PCI Express Link Capabilities 2 Register Bits 31:9 8 Type RsvdP RO Default Value 0 0 7:1 RO 7h Description Reserved Cross-Link Supported (N/A) Supported Link Speeds 001b: 2.5 GT/s (Gen 1) 010b: 5.0 GT/s (Gen 2) 100b: 8 GT/s (Gen 3) 0 RsvdP 0 Reserved Table 5-54: PCI Express Link Control 2 Register Bits 15:12 11 10 9:7 6 5 4 Type RWS/RsvdP RWS/RsvdP RWS/RsvdP RWS/RsvdP HwInit RWS/RsvdP RWS/RsvdP Default Value 0 0 0 0 0 0 0 3:0 RWS/RsvdP 3h Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Description Compliance De-emphasis Compliance SOS Enter Modified Compliance Transmit Margin Select De-Emphasis Hardware Autonomous Speed Disable Enter Compliance Target Link Speed 1h: 2.5 GT/s (Gen 1) 2h: 5.0 GT/s (Gen 2) 3h: 8 GT/s (Gen 3) 3/26/2018 Viking Technology Page 39 of 66 Table 5-55: PCI Express Link Status 2 Register Bits 15:6 5 4 3 2 1 0 Type RsvdP RW1CS ROS ROS ROS ROS RO Default Value 0 0 0 0 0 0 1 Description Reserved Link Equalization Request Equalization Phase 3 Successful Equalization Phase 2 Successful Equalization Phase 1 Successful Equalization Complete Current De-Emphasis 5.1.7 Advanced Error Reporting Registers Table 5-56: Advanced Error Reporting Capability Register Summary Start Address 100h 104h 108h 10Ch 110h 114h 118h 11Ch End Address 103h 107h 10Bh 10Fh 113h 117h 11Bh 12Bh Symbol AERID AERUCES AERUCEM AERUCESEV AERCES AERCEM AERCC AERHL Description AER Capability ID AER Uncorrectable Error Status AER Uncorrectable Error Mask AER Uncorrectable Error Severity AER Correctable Error Status AER Correctable Error Mask AER Advanced Error Capabilities and Control AER Header Log Table 5-57: AER Capability ID Register Bits Type Default Value 31:20:00 RO 148h 19:16 15:00 RO RO 2h 1h Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Description Next Pointer (Points to Secondary PCI Express Extended Capability Header Offset) Capability Version Capability ID 3/26/2018 Viking Technology Page 40 of 66 Table 5-58: AER Uncorrectable Error Status Register Bits 31:26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11:6 5 4 3:1 0 Type RsvdZ RsvdZ RsvdZ RsvdZ RW1CS RsvdZ RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RsvdZ RsvdZ RW1CS RsvdP Undefined Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Reserved TLP Prefix Blocked Error Status (N/A) Atomic Op Egress Blocked Status (N/A) Reserved Uncorrectable Internal Error Status Reserved Unsupported Request Error Status ECRC Error Status Malformed TLP Status Receiver Overflow Status (N/A) Unexpected Completion Status Completer Abort Status Completion Timeout Status Flow Control Protocol Error Status (N/A) Poisoned TLP Status Reserved Reserved Data Link Protocol Error Status Reserved Undefined Table 5-59: AER Uncorrectable Error Mask Register Bits 31:26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11:6 5 4 3:1 0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RsvdZ RsvdZ RsvdZ RsvdZ RWS RsvdZ RWS RWS RWS RWS RWS RWS RWS RWS RWS RsvdP RsvdZ RWS RsvdP Undefined Default Value 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Reserved TLP Prefix Blocked Error Mask (N/A) Atomic Op Egress Blocked Mask (N/A) MC Blocked TLP Mask (N/A) Uncorrectable Internal Error Mask ACS Violation Mask (N/A) Unsupported Request Error Mask ECRC Error Mask Malformed TLP Mask Receiver Overflow Mask (N/A) Unexpected Completion Mask Completer Abort Mask Completion Timeout Mask Flow Control Protocol Error Mask (N/A) Poisoned TLP Mask Reserved Reserved Data Link Protocol Error Mask Reserved Undefined 3/26/2018 Viking Technology Page 41 of 66 Table 5-60: AER Uncorrectable Error Severity Register Bits 31:26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11:6 5 4 3:1 0 Type RsvdP RsvdP RsvdP RsvdP RWS RsvdP RWS RWS RWS RWS RWS RWS RWS RWS RWS RsvdP RsvdP RWS RsvdP Undefined Default Value 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 1 0 0 Description Reserved TLP Prefix Blocked Error Mask (N/A) Atomic Op Egress Blocked Mask (N/A) Reserved Uncorrectable Internal Error Mask Reserved Unsupported Request Error Mask ECRC Error Mask Malformed TLP Mask Receiver Overflow Mask (N/A) Unexpected Completion Mask Completer Abort Mask Completion Timeout Mask Flow Control Protocol Error Mask (N/A) Poisoned TLP Mask Reserved Reserved Data Link Protocol Error Mask Reserved Undefined Table 5-61: AER Correctable Error Status Register Bits 31:16 15 14 13 12 11:9 8 7 6 5:1 0 Type RsvdZ RsvdZ RW1CS RW1CS RW1CS RsvdZ RW1CS RW1CS RW1CS RsvdZ RW1CS Default Value 0 0 0 0 0 0 0 0 0 0 0 Description Reserved Reserved Corrected Internal Error Status (N/A) Advisory Non-Fatal Error Status Replay Timer Timeout Status Reserved Replay Number Rollover Status Bad DLLP Status Bad TLP Status Reserved Received Error Status Table 5-62: AER Correctable Error Mask Register Bits 31:16 15 14 13 12 11:9 8 7 6 5:1 0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RsvdP RsvdP RWS RWS RWS RsvdP RWS RWS RWS RsvdP RW Default Value 0 0 1 1 0 0 0 0 0 0 0 Description Reserved Reserved Corrected Internal Error Mask (N/A) Advisory Non-Fatal Error Mask Replay Timer Timeout Mask Reserved Replay Number Rollover Mask Bad DLLP Mask Bad TLP Mask Reserved Received Error Mask 3/26/2018 Viking Technology Page 42 of 66 Table 5-63: AER Capabilities and Control Register Bits 31:12 11 10 9 8 7 6 5 4:0 Type RsvdP RsvdP RsvdP RsvdP RWS RO RWS RO ROS Default Value 0 0 0 0 0 1 0 1 0 Description Reserved TLP Prefix Log Present (N/A) Reserved Reserved ECRC Check Enable ECRC Check Capable ECRC Generation Enable ECRC Generation Capable First Error Pointer Table 5-64: AER Header Log Register Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Header Byte 3 Header Byte 2 Header Byte 1 Header Byte 0 Header Byte 7 Header Byte 6 Header Byte 5 Header Byte 4 Header Byte 11 Header Byte 10 Header Byte 9 Header Byte 8 Header Byte 15 Header Byte 14 Header Byte 13 Header Byte 12 Table 5-65: AER TLP Prefix Log Register Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description First TLP Prefix Log Byte 3 (N/A) First TLP Prefix Log Byte 2 (N/A) First TLP Prefix Log Byte 1 (N/A) First TLP Prefix Log Byte 0 (N/A) Second TLP Prefix Log Byte 7 (N/A) Second TLP Prefix Log Byte 6 (N/A) Second TLP Prefix Log Byte 5 (N/A) Second TLP Prefix Log Byte 4 (N/A) Third TLP Prefix Log Byte 11 (N/A) Third TLP Prefix Log Byte 10 (N/A) Third TLP Prefix Log Byte 9 (N/A) Third TLP Prefix Log Byte 8 (N/A) Fourth TLP Prefix Log Byte 15 (N/A) Fourth TLP Prefix Log Byte 14 (N/A) Fourth TLP Prefix Log Byte 13 (N/A) Fourth TLP Prefix Log Byte 12 (N/A) 3/26/2018 Viking Technology Page 43 of 66 Table 5-66: Secondary PCI Express Capability Register Summary Start Address 168h 16Ch 170h 174h 176h 178h 17Ah End Address 16Bh 16Fh 173h 175h 177h 179h 17Bh Symbol SPXID PXLC3 PXLE PXL0EC PXL1EC PXL2EC PXL3EC Description Secondary PCI Express Capability PCI Express Link Control 3 PCI Express Lane Error Status PCI Express Lane 0 Equalization Control PCI Express Lane 1 Equalization Control PCI Express Lane 2 Equalization Control PCI Express Lane 3 Equalization Control Table 5-67: Secondary PCI Express Capability ID Register Bits 31:20 19:16 Type RO RO Default Value 188h 1h 15:0 RO 0019h Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Description Next Pointer (Viking Vendor Specific Capability) Capability Version Capability ID (Secondary PCI Express Extended capability) 3/26/2018 Viking Technology Page 44 of 66 Table 5-68: PCI Express Link Control 3 Register Bits 31:2 Type Rsvdp Default Value 0 1 Rsvdp 0 0 Rsvdp 0 Description Reserved Link Equalization Request Interrupt Enable (N/A) Perform Equalization (N/A) Table 5-69: PCI Express Lane Error Status Register Bits 31:4 3:0 Type Rsvdp RW1CS Default Value 0 0 Description Reserved Lane Error Status Bits Table 5-70: PCI Express Lane 0 Equalization Register Bits 15 14:12 11:8 7 6:4 3:0 Type RsvdP HwInit/RO HwInit/RO RsvdP HwInit/RsvdP HwInit/RsvdP Default Value 0 7h Fh 0 0 0 Description Reserved Upstream Port Receiver Preset Hint Upstream Port Transmitter Preset Reserved Downstream Port Receiver Preset Hint (N/A) Downstream Port Transmitter Preset (N/A) Table 5-71: PCI Express Lane 1 Equalization Register Bits 15 14:12 11:8 7 6:4 3:0 Type RsvdP HwInit/RO HwInit/RO RsvdP HwInit/RsvdP HwInit/RsvdP Default Value 0 7h Fh 0 0 0 Description Reserved Upstream Port Receiver Preset Hint Upstream Port Transmitter Preset Reserved Downstream Port Receiver Preset Hint (N/A) Downstream Port Transmitter Preset (N/A) Table 5-72: PCI Express Lane 2 Equalization Register Bits 15 14:12 11:8 7 6:4 3:0 Type RsvdP HwInit/RO HwInit/RO RsvdP HwInit/RsvdP HwInit/RsvdP Default Value 0 7h Fh 0 0 0 Description Reserved Upstream Port Receiver Preset Hint Upstream Port Transmitter Preset Reserved Downstream Port Receiver Preset Hint (N/A) Downstream Port Transmitter Preset (N/A) Table 5-73: PCI Express Lane 3 Equalization Register Bits 15 14:12 11:8 7 6:4 3:0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RsvdP HwInit/RO HwInit/RO RsvdP HwInit/RsvdP HwInit/RsvdP Default Value 0 7h Fh 0 0 0 Description Reserved Upstream Port Receiver Preset Hint Upstream Port Transmitter Preset Reserved Downstream Port Receiver Preset Hint (N/A) Downstream Port Transmitter Preset (N/A) 3/26/2018 Viking Technology Page 45 of 66 5.1.8 Device Serial Number Capability Register Table 5-74: Device Serial Number Capability Register Header Bits 31:20 19:16 15:0 Type RO RO RO Default Value 158h 1h 3h Description Next Capability Offset Capability Version PCI Express Extended Capability ID Table 5-75: Serial Number Register Header (offset 0x4/0x8) Bits 31:0 Type RO Default Value parameter Description Serial Number register (1st dword) 5.1.9 Power Budgeting Extended Capability Table 5-76: Power Budgeting Extended Capability Header Bits 31:20 19:16 15:0 Type RO RO RO Default Value 168h 1h 4h Description Next Capability Offset Capability Version PCI Express Extended Capability ID Default Value 0 0 0 0 0 0 0 Description Reserved Power Rail Type PM State PM Sub State Data Scale Base Power Table 5-77: Data Register Bits 31:21 20:18 17:15 14:13 12:10 9:8 7:0 Type RsvdP RO RO RO RO RO RO Table 5-78: Power Budget Capability Register Bits 7:1 0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RsvdP HwInit Default Value 0 0 Description Reserved System Allocated 3/26/2018 Viking Technology Page 46 of 66 5.1.10 Latency Tolerance Reporting Capability Registers Table 5-79: LTR Extended Capability Header Bits 31:20 19:16 15:0 Type RO RO RO Default Value 188h 1h 18h Description Next Capability Offset Capability Version PCI Express Extended Capability ID Table 5-80: LTR Max Snoop latency Register Bits 15:13 12:10 9:0 Type RsvdP RW RW Default Value 0 0 0 Description Reserved Max Snoop latency Scale Max Snoop latency Value Table 5-81: LTR Max No Snoop latency Register Bits 15:13 12:10 9:0 Type RsvdP RW RW Default Value 0 0 0 Description Reserved Max No Snoop latency Scale Max No Snoop latency Value 5.1.11 L1 Substates Capability Registers Table 5-82: L1 Substates Extended Capability Header Bits 31:20 19:16 15:0 Type RO RO RO Default Value 0 1h 1Eh Description Next Capability Offset Capability Version PCI Express Extended Capability ID Table 5-83: L1 Substates Capability Register Bits 31:24 23:19 18 17:16 15:8 7:5 4 3 2 1 0 Manual PSFN25xxxxYxxx Revision C www.vikingtechnology.com Type RsvdP HwInit RsvdP HwInit HwInit RsvdP HwInit HwInit HwInit HwInit HwInit Default Value 0 5h 0 0 Ah 0 0 0 0 0 0 Description Reserved Port Power on value Reserved Port T_Power_on scale Port Common_mode_restore_time Reserved L1 PM Substates Supported ASPM PM L1.1 Supported ASPM PM L1.2 Supported PCI PM L1.1 Supported PCI PM L1.2 Supported 3/26/2018 Viking Technology Page 47 of 66 Table 5-84: L1 Substates Control1 Register Bits 31:29 28:26 25:16 15:8 7:4 3 2 1 0 Type RW RsvdP RW RsvdP RsvdP RW RW RW RW Default Value 0 0 0 0 0 0 0 0 0 Description LTR L1.2 Threshold Scale Reserved LTR L1.2 Threshold value Common_mode_restore_time Reserved ASPM PM L1.1 Supported ASPM PM L1.2 Supported PCI PM L1.1 Supported PCI PM L1.2 Supported Table 5-85: L1 Substates Control2 Register Bits 31:8 7:3 2 1:0 5.2 Type RsvdP RW RsvdP RW Default Value 0 5 0 0 Description Reserved T_POWER_ON Value Reserved T_POWER_ON Scale NVM Express Registers 5.2.1 Register Summary Table 5-86: Register Summary Start Address 00h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 30h 38h F00h 1000h 1000h + (1 * (4