VR7PA127258GBDMKT

DDR3 72bit Registered SODIMM VR7PAxx7258xxx MODULE CONFIGURATIONS Module Device Configuration Configuration VR7PA287258FBZ 1GB 128Mx72 128Mx8 (9) VR7PA287258FBA 1GB 128Mx72 128Mx8 (9) VR7PA287258FBD 1GB 128Mx72 128Mx8 (9) VR7PA287258FBF 1GB 128Mx72 128Mx8 (9) VR7PA567258GBZ 2GB 256Mx72 256Mx8 (9) VR7PA567258GBA 2GB 256Mx72 256Mx8 (9) VR7PA567258GBD 2GB 256Mx72 256Mx8 (9) VR7PA567258GBF 2GB 256Mx72 256Mx8 (9) VR7PA567258FBZ 2GB 256Mx72 128Mx8 (18) VR7PA567258FBA 2GB 256Mx72 128Mx8 (18) VR7PA567258FBD 2GB 256Mx72 128Mx8 (18) VR7PA567258FBF 2GB 256Mx72 128Mx8 (18) VR7PA127258HBZ 4GB 512Mx72 512Mx8 (9) VR7PA127258HBA 4GB 512Mx72 512Mx8 (9) VR7PA127258HBD 4GB 512Mx72 512Mx8 (9) VR7PA127258HBF 4GB 512Mx72 512Mx8 (9) VR7PA127258HBG 4GB 512Mx72 512Mx8 (9) VR7PA127258GBZ 4GB 512Mx72 256Mx8 (18) VR7PA127258GBA 4GB 512Mx72 256Mx8 (18) VR7PA127258GBD 4GB 512Mx72 256Mx8 (18) VR7PA127258GBF 4GB 512Mx72 256Mx8 (18) VR7PA127258GBG 4GB 512Mx72 256Mx8 (18) VR7PA1G7258HBZ 8GB 1Gx72 512Mx8 (18) VR7PA1G7258HBA 8GB 1Gx72 512Mx8 (18) VR7PA1G7258HBD 8GB 1Gx72 512Mx8 (18) VR7PA1G7258HBF 8GB 1Gx72 512Mx8 (18) VR7PA1G7258HBG 8GB 1Gx72 512Mx8 (18) VR7PA2G7258JBZ 16GB 2Gx72 1Gx8(18) VR7PA2G7258JBA 16GB 2Gx72 1Gx8(18) VR7PA2G7258JBD 16GB 2Gx72 1Gx8(18) VR7PA2G7258JBF 16GB 2Gx72 1Gx8(18) VR7PA2G7258JBG 16GB 2Gx72 1Gx8(18) Note: For part numbers containing an x, contact Viking for the complete PN Viking Part Number Capacity Device Package Module Ranks Performance CAS Latency TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 1 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx Features         JEDEC standard Power Supply o VDD = VDDQ = 1.5V ±0.075V o VDDSPD = +3.0V to +3.6V 204-pin Registered Dual-In-Line Memory Module with parity bit for address and control bus. 8 Internal Banks. Programmable CAS Latency: 6, 7, 9, 11 Programmable CAS Write Latency (CWL). Programmable Additive Latency (Posted CAS). Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF)         On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity. Refresh. Self Refresh and Power Down Modes. ZQ Calibration for output driver and ODT. System Level Timing Calibration Support via Write Leveling and Multi Purpose Register (MPR) Read Pattern. Serial Presence Detect with EEPROM. On-DIMM Thermal Sensor. Asynchronous Reset. RoHS Compliant* (see last page) Nomenclature Module Standard PC3-6400 PC3 -8500 PC3-10600 PC3-12800 PC3-14900 SDRAM Standard DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Clock 400MHz 533MHz 667MHz 800MHz 933MHz Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 2 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx PIN CONFIGURATIONS (REG) Pin Front Side Pin Back Side Pin Front Side Pin Back Side Pin 1 VREFDQ 2 Vss 53 Vss 54 DQ28 105 3 Vss 4 DQ4 55 DQ24 56 DQ29 5 DQ0 6 DQ5 57 DQ25 58 Vss 7 DQ1 8 Vss 59 DM3 60 9 11 13 Vss DM0 DQ2 10 12 14 DQS0# DQS0 Vss 61 63 65 Vss DQ26 DQ27 15 DQ3 16 DQ6 67 17 Vss 18 DQ7 19 DQ8 20 Vss 21 DQ9 22 23 Vss 25 Front Pin Side Back Side Pin Front Side Pin Back Side A2 157 DM5 158 Vss A1 106 107 A0 108 BA1 159 DQ42 160 DQ46 109 VDD 110 VDD 161 DQ43 162 DQ47 DQS3# 111 CK0 112 Par_In 163 Vss 164 Vss 62 64 66 DQS3 Vss DQ30 113 CK0# 114 Err_Out 165 115 VDD 116 VDD 167 117 A10/AP 118 S3# 169 DQ48 DQ49 Vss 166 168 170 DQ52 DQ53 Vss Vss 68 DQ31 119 BA0 120 S2# 171 DQS6# 172 DM6 69 CB0 70 Vss 121 WE# 122 RAS# 173 DQS6 174 DQ54 71 CB1 72 CB4 123 VDD 124 VDD 175 Vss 176 DQ55 DQ12 73 Vss 74 CB5 125 CAS# 126 ODT0 177 DQ50 178 Vss 24 DQ13 75 DQS8# 76 DM8 127 S0# 128 ODT1 179 DQ51 180 DQ60 DQS1# 26 Vss 77 DQS8 78 Vss 129 S1# 130 A13 181 Vss 182 DQ61 27 DQS1 28 DM1 79 Vss 80 CB6 131 VDD 132 VDD 183 DQ56 184 Vss 29 31 Vss DQ10 30 32 RESET# Vss 81 83 CB2 CB3 82 84 CB7 VREFCA 133 135 DQ32 134 DQ33 136 DQ36 DQ37 185 187 DQ57 Vss 186 DQS7# 188 DQS7 33 DQ11 34 DQ14 85 VDD 86 VDD 137 138 Vss 189 DM7 190 Vss 35 Vss 36 DQ15 87 CKE0 88 A15 139 DQS4# 140 Dm4 191 DQ58 192 DQ62 37 DQ16 38 Vss 89 CKE1 90 A14 141 DQS4 142 DQ38 193 DQ59 194 DQ63 39 DQ17 40 DQ20 91 BA2 92 A9 143 DQ39 195 Vss 196 Vss 41 Vss 42 DQ21 93 VDD 94 VDD 145 DQ34 146 Vss 197 SA0 198 EVENT# 43 DQS2# 44 DM2 95 A12/BC# 96 A11 147 DQ35 148 DQ44 199 VDDSPD 200 SDA 45 47 DQS2 Vss 46 48 Vss DQ22 97 99 A8 A5 98 100 A7 A6 149 151 Vss 150 DQ40 152 DQ45 Vss 201 203 SCL Vtt 49 DQ18 50 DQ23 101 VDD 102 VDD 153 DQ41 154 DQS5# 51 DQ19 52 Vss 103 A3 104 A4 155 Vss Vss Vss 144 156 SA1 Vtt 202 204 DQS5 Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 3 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx PIN FUNCTION DESCRIPTION SYMBOL TYPE POLARITY CK0 IN Positive Edge /CK0 IN Negative Edge CKE[1:0] IN Active High S[3:0]# IN Active Low ODT[1:0] RAS#, CAS#, WE# VREFDQ IN Active High IN Active Low Supply VREFCA Supply BA[2:0] IN - A[15:13, 12/BC,11, 10/AP,9:0] IN - I/O - Supply IN Supply Supply I/O I/O Active High DQ [63:0], CB [7:0] VDD, VSS DM [8:0] VDD, VSS VTT DQS[17:0] DQS [17:0]# Positive Edge Negative Edge TDQS[17:9], TDQS[17:9]# OUT SA [2:0] IN - SDA I/O - SCL IN - DESCRIPTION Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver. Negative line of the differential pair of system clock inputs that drives the input to the onDIMM Clock Driver. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations continue. These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of register outputs. On-Die Termination control signals When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the operation to be executed by the SDRAM. Reference voltage for DQ0-DQ63 and CB0-CB7. Reference voltage for A0-A15, BA0-BA2, RAS#, CAS#, WE#, S0#, S1#, CKE0, CKE1, Par_In, ODT0 and ODT1. Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines mode register is to be accessed during an MRS cycle. Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS# command. The address inputs also provide the op-code during Mode Register Set commands. Data and Check Bit Input/Output pins Power and ground for the DDR SDRAM input buffers and core logic. Masks write data when high, issued concurrently with input data. Power and ground for the DDR SDRAM input buffers and core logic. Termination Voltage for Address/Command/Control/Clock nets. Positive line of the differential data strobe for input and output data. Negative line of the differential data strobe for input and output data. TDQS, TDQS# is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS, TDQS# that is applied to DQS, DQS#. When disabled via mode register A11=0 in MR1, DM, TDQS will provide the data mask function and TDQS# is not used. X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1 These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pull-up. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 4 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx PIN FUNCTION DESCRIPTION SYMBOL TYPE POLARITY EVENT# OUT (open drain) Active Low VDDSPD Supply - RESET# IN Par_In Err_Out# TEST IN OUT DESCRIPTION This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part. Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (the PLL will remain synchronized with the input clock) Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even) Parity error found in the Address and Control bus Used by memory bus analysis tools (unused (NC) on memory DIMMs) Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 5 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx MECHANICAL OUTLINE SINGLE RANK Dimensions are in mm. Tolerance is +/- 0.127, unless otherwise stated. 67.60 3.80 Max 30.00 SIDE VIEW 20.00 TYP 1.00 +/- 0.10 FRONT BACK Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 6 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx MECHANICAL OUTLINE DUAL RANK Dimensions are in mm. Tolerance is +/- 0.127, unless otherwise stated. 67.60 3.80 Max 30.00 SIDE VIEW 20.00 TYP 1.00 +/- 0.10 FRONT BACK Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 7 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx FUNCTIONAL BLOCK DIAGRAM S0# S1# 1:2 BA[n:0] R E G I S T E R A[n:0] RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 CK0 CK0# PAR_IN RESET# P L L RCS0A: U[4:1], U9 RCS0B: U[8:5] RCS1A: U[13:10], U18 RCS1B: U[17:14] RBA[2:0]A: U[4:1], U[13:9], U18 RBA[2:0]B: U[8:5], U[17:14] RA[n:0]A: U[4:1], U[13:9], U18 RA[n:0]B: U[8:5], U[17:14] RRASA: U[4:1], U[13:9], U18 RRASB: U[8:5], U[17:14] RCASA: U[4:1], U[13:9], U18 RCASB: U[8:5], U[17:14] RWEA: U[4:1], U[13:9], U18 RWEB: U[8:5], U[17:14] RCKE0A: U[4:1], U9 RCKE0B: U[8:5] RCKE1A: U[13:10], U18 RCKE1B: U[17:14] RODT0A: U[4:1], U9 RODT0B: U[8:5] RODT1A: U[13:10], U18 RODT1B: U[17:14] PCK0: U[4:1], U9 PCK2: U[13:10], U18 PCK1: U[8:5] PCK3: U[17:14] Thermal Sensor With SPD SCL EVENT A0 A1 A2 SDA EVENT SA0 SA1 SA2 VDDSPD VDD VTT VREFCA VREFDQ VSS Serial PD U1~U18 U1~U18 U1~U18 U1~U18 Notes: The resistor values may vary depending on systems application ERR_OUT RST#: SDRAMs U[18:1] Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 8 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx FUNCTIONAL BLOCK DIAGRAM DQS DQS# TDQS TDQS# DQ [7:0] U13 U3 DQS DQS# TDQS TDQS# DQ [7:0] U2 DQS DQS# TDQS TDQS# DQ [7:0] U11 U1 DQS DQS# TDQS TDQS# DQ [7:0] U10 DQS DQS# TDQS TDQS# DQ [7:0] ZQ PCK1B PCK1B# RCKE1B RODT1B U6 DQS DQS# TDQS TDQS# DQ [7:0] U15 U7 DQS DQS# TDQS TDQS# DQ [7:0] U16 U8 DQS DQS# TDQS TDQS# DQ [7:0] ZQ VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# TDQS TDQS# DQ [7:0] ZQ ZQ VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# TDQS TDQS# DQ [7:0] ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS6 DQS6# DM6/DQS15 DQS15# DQ[55:48] VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] U12 VSS ZQ ZQ U17 VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# TDQS TDQS# DQ [7:0] ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS7 DQS7# DM7/DQS16 DQS16# DQ[63:56] VSS VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] ZQ VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# TDQS TDQS# DQ [7:0] ZQ ZQ VSS Vtt Notes: 1. DQ to I/O wiring may be changed within a byte. 2. Data and Strobe resistor values are 15 ohm +/- 5% 3. Vtt resistor values are 36 ohm 4. ZQ resistor values are 240 ohm VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# TDQS TDQS# DQ [7:0] ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS0 DQS0# DM0/DQS9 DQS9# DQ[7:0] ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS5 DQS5# DM5/DQS14 DQS14# DQ[47:40] VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# TDQS TDQS# DQ [7:0] ZQ DQS1 DQS1# DM1/DQS10 DQS10# DQ[15:8] U14 VSS VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] ZQ VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# TDQS TDQS# DQ [7:0] ZQ DQS2 DQS2# DM2/DQS11 DQS11# DQ[23:16] DQS DQS# TDQS TDQS# DQ [7:0] VSS VSS DQS3 DQS3# DM3/DQS12 DQS12# DQ31:24] U5 VSS U4 DQS4 DQS4# DM4/DQS13 DQS3# DQ[39:32] CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] U18 VSS DQS DQS# TDQS TDQS# DQ [7:0] RS1B# RS0B# RRASB# RCASB# RWEB# PCK0B PCK0B# RCKE0B RODT0B A[N:0]B /BA[N:0]B 2 RANK MODULE ONLY PCK1A PCK1A# RCKE1A RODT1A U9 CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# TDQS TDQS# DQ [7:0] ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS8 DQS8# DM8/DQS17 DQS17# CB[7:0] RS1A# RS0A# RRASA# RCASA# RWEA# PCK0A PCK0A# RCKE0A RODT0A A[N:0]A /BA[N:0]A 2 RANK MODULE ONLY Vtt Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 9 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to GND Vin, Vout -0.4 ~ 1.975 V Voltage on VDD supply relative to GND VDD -0.4 ~ 1.975 V Voltage on VDDQ supply relative to GND VDDQ -0.4 ~ 1.975 V Storage temperature TSTG -55 ~ +100 C Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (SSTL_1.5) Recommended operating conditions (Voltages referenced to GND, Tcase = 0 to 85C) Parameter Case Temperature Supply voltage Supply voltage for DQ, DQS Reference Voltage for DQ, DM inputs Reference Voltage for ADD, CMD inputs Terminal Voltage EEPROM Supply Voltage Input high voltage Input low voltage Symbol Min. Max. Unit Notes Tcase VDD VDDQ VREFDQ(DC) VREFCA(DC) VTT VDDSPD VIH(AC) VIH(DC) VIL(AC) VIL(DC) 0 1.425 1.425 0.49 x VDD 0.49 x VDD 0.49 x VDD 3.0 VREF + 0.175 VREF + 0.100 VSS -5 -5 -5 -10 95 1.575 1.575 0.51 x VDD 0.51 x VDD 0.51 x VDD 3.6 VDD VREF - 0.175 VREF – 0.100 5 5 5 10 ºC V V V V V V 5 1, 2 1, 2 3, 4 3, 4 3, 4 V V Single Rank Input leakage IIL µA current Dual Rank Single Rank Output leakage IOL µA current Dual Rank Note: 1. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together 2. Under all conditions VDDQ must be less than or equal to VDD. 3. The ac peak noise on VREF may not allow VREF to deviate from VREF.DC by more than ±1% VDD (for reference: approx. ± 15 mV). 4. For reference: approx. VDD/2 ± 15 mV. 5. Refresh rate required to be doubled (tREFI = 3.9µs) when 85°C < TC < 95°C. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 10 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx DEVICE CAPACITANCE DDR3-800 Min Max DDR3-1066 Min Max DDR3-1333 Min Max Units Notes CIO 1.5 3.0 1.5 2.7 1.5 2.5 pF 1,2,3 CCK CDCK CDDQS CI CZQ 0.8 0 0 0.75 - 1.6 0.15 0.2 1.4 3 0.8 0 0 0.75 - 1.6 0.15 0.2 1.35 3 0.8 0 0 0.75 - 1.4 0.15 0.15 1.3 3 pF pF pF pF pF 2,3 2,3,4 2,3,5 2,3,6 2,3,7 Parameter Input/output capacitance (DQ, DM, DQS, DQS#, TDQS,TDQS#) Input capacitance, CK and CK# Symbol DDR3-1600 Min Max DDR3-1866 Min Max Min Max Units Notes CIO 1.5 2.3 1.4 2.2 pF 1,2,3 CCK 0.8 1.4 0.8 1.3 pF 2,3 Input capacitance delta, CK and CK# Input/output capacitance delta DQS and DQS# Input capacitance, (CTRL, ADD, CMD input-only pins) Input/output capacitance of ZQ pin CDCK CDDQS CI CZQ 0 0 0.75 - 0.15 0.15 1.3 3 0 0 0.75 - 0.15 0.15 1.2 3 pF pF pF pF 2,3,4 2,3,5 2,3,6 2,3,7 Parameter Input/output capacitance (DQ, DM, DQS, DQS#, TDQS,TDQS#) Input capacitance, CK and CK# Input capacitance delta, CK and CK# Input/output capacitance delta DQS and DQS# Input capacitance, (CTRL, ADD, CMD input-only pins) Input/output capacitance of ZQ pin Symbol DEVICE CAPACITANCE (Cont.) Note: 1. Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK# 5. Absolute value of CIO(DQS)-CIO(DQS#) 6. CI applies to ODT, CS#, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#. 7. Maximum external load capacitance on ZQ pin: 5 pF. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 11 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx DC CHARACTERISTICS DEFINITIONS (Recommended operating conditions unless otherwise noted, Tcase = 0 to 85 C) Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6 IDD6ET IDD7 Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current (slow exit); All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge power-down current (fast exit); All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Extended Temperature Range Self-Refresh Current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled, Applicable for MR2 setting A6=0 and A7=1 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Units Notes mA 1, 2 mA 1, 2 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 2 mA 1, 2 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 2 Notes: 1. Calculated values are from component data. 2. One module rank in the active IDD; the other rank in IDD2P-S (slow exit) 3. All ranks in this IDD condition. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 12 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx DC CHARACTERISTICS CURRENTS SINGLE RANK 1Gbit Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 DDR3-800 405 495 90 180 225 225 225 405 765 810 1035 90 108 1305 DDR3-1066 405 495 90 180 225 225 225 405 765 810 1035 90 108 1305 DDR3-1333 450 540 90 180 225 225 225 450 900 945 1035 90 108 1575 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA DC CHARACTERISTICS CURRENTS DUAL RANK 1Gbit Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 DDR3-800 495 585 180 360 450 450 450 810 855 900 2070 180 216 1395 DDR3-1066 495 585 180 360 450 450 450 810 855 900 2070 180 216 1395 DDR3-1333 540 630 180 360 450 450 450 900 990 1035 2070 180 216 1665 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 13 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx DC CHARACTERISTICS CURRENTS SINGLE RANK 2Gbit Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 DDR3-800 819 1008 117 225 468 477 288 513 1413 1161 2322 108 108 2403 DDR3-1066 945 1125 117 297 594 603 378 648 1755 1485 2439 108 108 2646 DDR3-1333 1053 1224 117 315 675 693 423 747 2070 1755 2529 108 108 3213 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA DC CHARACTERISTICS CURRENTS DUAL RANK 2Gbit Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 DDR3-800 936 1125 234 450 936 954 576 1026 1530 1278 4644 216 216 2520 DDR3-1066 1062 1242 234 594 1188 1206 756 1296 1872 1602 4878 216 216 2763 DDR3-1333 1170 1341 234 630 1350 1386 846 1494 2187 1872 5058 216 216 3330 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 14 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx DC CHARACTERISTICS CURRENTS SINGLE RANK 4Gbit Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit 495 396 531 162 234 243 252 288 288 1107 855 2016 180 225 1440 423 558 162 252 252 261 315 315 1260 990 2052 180 225 1710 495 594 162 288 288 288 342 342 1413 1125 2115 180 225 1980 558 630 162 333 315 315 369 369 1566 1269 2178 180 225 2259 mA mA mA mA mA mA mA mA mA mA mA mA mA mA 180 252 324 351 378 1035 855 1800 198 252 1530 DC CHARACTERISTICS CURRENTS DUAL RANK 4Gbit Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 713 842 259 363 466 505 583 544 1491 1231 2593 285 363 2204 558 693 324 468 486 504 576 576 1269 1017 2016 360 450 1602 585 720 324 504 504 522 630 630 1422 1152 2052 360 450 1872 657 756 324 576 576 576 684 684 1575 1287 2115 360 450 2142 720 792 324 666 630 630 738 738 1728 1431 2178 360 450 2421 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 15 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx DC CHARACTERISTICS CURRENTS SINGLE RANK 8Gbit Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit 549 621 99 72 252 270 270 405 855 855 2070 216 72 1440 567 648 99 90 270 288 288 423 945 945 2115 216 90 1530 585 675 99 108 288 306 306 441 1035 1035 2160 216 108 1620 603 702 99 126 306 324 324 459 1125 1125 2205 216 126 1710 621 729 99 144 324 342 342 477 1215 1215 2250 216 144 1800 mA mA mA mA mA mA mA mA mA mA mA mA mA mA DC CHARACTERISTICS CURRENTS DUAL RANK 8Gbit Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit 790 894 142 103 363 388 388 583 1231 1231 2982 311 103 2074 816 933 142 129 388 414 414 609 1361 1361 3046 311 129 2204 842 972 142 155 414 440 440 635 1491 1491 3111 311 155 2333 868 1011 142 181 440 466 466 661 1620 1620 3176 311 181 2463 894 1050 142 207 466 492 492 687 1750 1750 3241 311 207 2593 mA mA mA mA mA mA mA mA mA mA mA mA mA mA REGISTERING CLOCK DRIVER SPECIFICATIONS SSTE82882 or equivalent Symbol VDD VREF VTT Parameter DC supply voltage DC reference voltage DC termination voltage VIH(AC) AC high-level input voltage Pins Min Nom Max Units – – – Control, command, address 1.425 0.49 × VDD VREF – 40 mV 1.5 0.5 × VDD VREF 1.575 0.51 × VDD VREF + 40 mV V V V VREF + 175mV – VDD + 0.4 V Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 16 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx Control, command, –0.4 – VREF - 175mV V address Control, VIH(DC) DC high-level input voltage command, VREF + 100mV – VDD + 0.4 V address Control, VIL(DC) DC low-level input voltage command, –0.4 – VREF - 100mV V address VIH RESET#, High-level input voltage 0.65 × VDD – VDD V (CMOS) MIRROR VIL RESET#, Low-level input voltage 0 – 0.35 × VDD V (CMOS) MIRROR Differential input crosspoint CK, CK#, FBIN, VIX(AC) 0.5 × VDD - 175mV 0.5 × VDD 0.5 × VDD + 175mV V voltage range FBIN# VID(AC) Differential input voltage CK, CK# 350 – VDD mV IOH High-level output current FBOUT, FBOUT# – – 11 mA IOL Low-level output current ERR_OUT# 25 mA Notes: Timing and switching specifications for the register are critical for proper operation of the DDR3 SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. VIL(AC) AC low-level input voltage Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 17 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx AC CHARACTERISTICS Refresh parameters by device density Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units REF command to ACT or tRFC 110 160 260 350 ns REF command time 0 °C ≤ TCASE ≤ 85 °C 7.8 7.8 7.8 7.8 µs Average periodic refresh tREFI interval 85 °C < TCASE ≤ 95 °C 3.9 3.9 3.9 3.9 μs Note: 1) Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. Notes 1 DDR3-800 Speed Bins and Operating Conditions Speed Bin CL-nRCD-nRP Parameter Internal read command to first data Symbol tAA ACT to internal read or write delay time tRCD DDR3-800 6-6-6 min max 15 20 Unit Notes ns 15 — ns PRE command period tRP 15 — ns ACT to ACT or REF command period tRC 52.5 — ns ACT to PRE command period CL = 6 CWL = 5 Supported CL Settings Supported CWL Settings tRAS tCK(AVG) 37.5 2.5 9 * tREFI 3.3 6 5 ns ns nCK nCK 1, 2, 3 13 DDR3-1066 Speed Bins and Operating Conditions Speed Bin CL-nRCD-nRP Parameter Internal read command to first data DDR3-1066 7-7-7 min max 13.125 20 Symbol tAA ACT to internal read or write delay time tRCD 13.125 — ns PRE command period tRP 13.125 — ns ACT to ACT or REF command period tRC 50.625 — ns ACT to PRE command period CWL = 5 CL = 6 CWL = 6 CWL = 5 CL = 7 CWL = 6 CWL = 5 CL = 8 CWL = 6 Supported CL Settings Supported CWL Settings tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 37.5 9 * tREFI 2.5 3.3 Reserved Reserved 1.875 < 2.5 Reserved 1.875 < 2.5 6, 7, 8 5, 6 Unit Note ns ns ns ns ns ns ns ns nCK nCK 1,2,3,6, 1,2,3,4, 4, 1,2,3,4, 4, 1,2,3, 13 Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Office: 714.913.2200 Fax: 714.913.2202Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PAxx7258xxx-LF  Revision D  Page 18 of 30 DDR3 72bit Registered SODIMM VR7PAxx7258xxx DDR3-1333 Speed Bins and Operating Conditions Speed Bin CL-nRCD-nRP Parameter DDR3-1333 9-9-9 min Symbol Unit Note max Internal read command to first data tAA 13.5 (13.125)5,11 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125)5,11 — ns PRE command period tRP 13.5 (13.125)5,11 — ns ACT to ACT or REF command period tRC 49.5 (49.125)5,11 — ns ACT to PRE command period CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 36 2.5 9 * tREFI 3.3 ns ns ns ns ns 1,2,3,7 1,2,3,4,7 4 4 CL = 7 CWL = 6 tCK(AVG) ns 1,2,3,4,7 CWL = 7 CWL = 5 CWL = 6 CWL = 7 CWL = 5, 6 CWL = 7 CWL = 5, 6 tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) CWL = 7 tCK(AVG) ns ns ns ns ns ns ns ns 1,2,3,4 4 1,2,3,7 1,2,3,4 4 1,2,3,4 4 1,2,3 CL = 8 CL = 9 CL = 10 Reserved Reserved Reserved 1.875 < 2.5 (Optional)5,11 Reserved Reserved 1.875 < 2.5 Reserved Reserved 1.5