AD S
ADS7804
780
4
ADS
780
4
SBAS019A – JANUARY 1992 – REVISED MAY 2003
12-Bit 10µs Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
DESCRIPTION
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The ADS7804 is a complete 12-bit sampling analog-to-digital
(A/D) converter using state-of-the-art CMOS structures. It
contains a complete 12-bit, capacitor-based, SAR A/D converter with S/H, reference, clock, interface for microprocessor use, and three-state output drivers.
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100kHz min SAMPLING RATE
STANDARD ±10V INPUT RANGE
72dB min SINAD WITH 45kHz INPUT
±0.45 LSB max INL
DNL: 12 Bits “No Missing Codes”
SINGLE +5V SUPPLY OPERATION
PIN-COMPATIBLE WITH 16-BIT ADS7805
USES INTERNAL OR EXTERNAL
REFERENCE
COMPLETE WITH S/H, REF, CLOCK, ETC.
FULL PARALLEL DATA OUTPUT
100mW max POWER DISSIPATION
28-PIN 0.3" PLASTIC DIP AND SO PACKAGES
Clock
The ADS7804 is specified at a 100kHz sampling rate, and
guaranteed over the full temperature range. Laser-trimmed
scaling
resistors
provide
an
industrystandard ±10V input range, while the innovative design
allows operation from a single +5V supply, with power
dissipation under 100mW.
The 28-pin ADS7804 is available in plastic 0.3" DIP and SO
packages, both fully specified for operation over the industrial –40°C to +85°C range.
Successive Approximation Register and Control Logic
R/C
CS
BYTE
BUSY
CDAC
20kΩ
±10V Input
10kΩ
4kΩ
Comparator
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
CAP
Buffer
Internal
+2.5V Ref
4kΩ
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1992-2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Analog Inputs: VIN ............................................................................. ±25V
CAP ................................... +VANA +0.3V to AGND2 –0.3V
REF .......................................... Indefinite Short to AGND2
Momentary Short to VANA
Ground Voltage Differences: DGND, AGND1, AGND2 ................. ±0.3V
VANA ....................................................................................................... 7V
VDIG to VANA ..................................................................................... +0.3V
VDIG ....................................................................................................... 7V
Digital Inputs ........................................................... –0.3V to +VDIG +0.3V
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ............................................... +300°C
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
MAXIMUM
LINEARITY
ERROR
(LSB)
MINIMUM
SIGNAL-TO(NOISE+DISTORTION)
RATIO (LSB)
PACKAGE-LEAD
(DESIGNATOR)(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS7804P
±0.9
70
DIP-28 (NT)
–40°C to +85°C
ADS7804P
ADS7804P
Tube, 13
ADS7804PB
±0.45
72
DIP-28 (NT)
–40°C to +85°C
ADS7804PB
ADS7804PB
Tube, 13
ADS7804U
±0.9
70
SO-28 (DW)
–40°C to +85°C
ADS7804U
"
"
"
"
"
"
ADS7804U
ADS7804U/1K
Tube, 28
Tape and Reel, 1000
ADS7804UB
±0.45
72
SO-28 (DW)
–40°C to +85°C
ADS7804UB
"
"
"
"
"
"
ADS7804UB
ADS7804UB/1K
Tube, 28
Tape and Reel, 1000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, fS = 100kHz, and VDIG = VANA = +5V, using internal reference, unless otherwise specified.
ADS7804P, U
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise(2)
Full Scale Error(3,4)
Full Scale Error Drift
Full Scale Error(3,4)
Full Scale Error Drift
Bipolar Zero Error(3)
Bipolar Zero Error Drift
Power Supply Sensitivity
(VDIG = VANA = VD)
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Full-Power Bandwidth(6)
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery(7)
2
MAX
MIN
TYP
12
ANALOG INPUT
Voltage Ranges
Impedance
Capacitance
THROUGHPUT SPEED
Conversion Time
Complete Cycle
Throughput Rate
ADS7804PB, UB
±10V
23
35
5.7
Acquire and Convert
✻
8
10
±7
±2
±2
+4.75V < VD < +5.25V
FS Step
Bits
V
kΩ
pF
✻
✻
µs
µs
kHz
±0.45
±0.45
LSB(1)
LSB
Bits
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
LSB
✻
✻
Ensured
0.1
45kHz
45kHz
45kHz
45kHz
✻
✻
±0.9
±0.9
fIN =
fIN =
fIN =
fIN =
UNITS
✻
✻
✻
100
Ext. 2.5000V Ref
Ext. 2.5000V Ref
MAX
±0.5
±5
±0.5
±0.25
±0.25
✻
±10
±10
✻
±0.5
✻
✻
80
✻
–80
70
70
72
72
250
✻
40
Sufficient to meet AC specs
2
150
✻
ns
✻
✻
✻
dB(5)
dB
dB
dB
kHz
µs
ns
ADS7804
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SBAS019A
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = –40°C to +85°C, fS = 100kHz, and VDIG = VANA = +5V, using internal reference, unless otherwise specified.
ADS7804P, U
PARAMETER
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
(Must use external buffer.)
Internal Reference Drift
External Reference Voltage Range
for Specified Linearity
External Reference Current Drain
CONDITIONS
Output Capacitance
TYP
2.48
2.5
1
2.3
8
2.5
Ext. 2.5000V Ref
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
VOH
Leakage Current
MIN
Power Dissipation
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
Thermal Resistance (θJA)
Plastic DIP
SO
MAX
MIN
TYP
–0.3
+2.0
MAX
UNITS
V
µA
2.52
✻
✻
✻
✻
2.7
✻
✻
✻
ppm/°C
V
✻
µA
✻
✻
✻
✻
V
V
µA
µA
✻
100
+0.8
VD +0.3V
±10
±10
✻
✻
Parallel 12 Bits
Binary Two’s Complement
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State,
VOUT = 0V to VDIG
High-Z State
+0.4
Must be ≤ VANA
±5
✻
V
V
µA
15
15
pF
83
83
✻
✻
ns
ns
✻
✻
V
V
mA
mA
✻
mW
✻
✻
✻
°C
°C
°C
✻
+4
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
POWER SUPPLIES
Specified Performance
VDIG
VANA
+IDIG
+IANA
ADS7804PB, UB
+4.75
+4.75
+5
+5
0.3
16
fS = 100kHz
+5.25
+5.25
✻
✻
✻
✻
✻
✻
100
–40
–55
–65
+85
+125
+150
75
75
✻
✻
✻
✻
✻
°C/W
°C/W
NOTES: (1) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7804, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and
temperatures. (3) As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full
Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes
the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which
Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input overvoltage.
ADS7804
SBAS019A
www.ti.com
3
PIN CONFIGURATION
VIN
1
28
VDIG
AGND1
2
27
VANA
REF
3
26
BUSY
CAP
4
25
CS
AGND2
5
24
R/C
D11 (MSB)
6
23
BYTE
D10
7
22
DZ
ADS7804
DIGITAL
I/O
D9
8
21
DZ
D8
9
20
DZ
D7 10
19
DZ
D6 11
18
D0 (LSB)
D5 12
17
D1
D4 13
16
D2
DGND 14
15
D3
PIN #
NAME
1
VIN
DESCRIPTION
2
AGND1
3
REF
Reference Input/Output. 2.2µF tantalum capacitor to ground.
Reference Buffer Capacitor. 2.2µF tantalum capacitor to ground.
Analog Input. See Figure 7.
Analog Ground. Used internally as ground reference point.
4
CAP
5
AGND2
6
D11 (MSB)
O
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
7
D10
O
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.
8
D9
O
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.
9
D8
O
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.
10
D7
O
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.
11
D6
O
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.
12
D5
O
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.
13
D4
O
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.
14
DGND
15
D3
O
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.
16
D2
O
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.
17
D1
O
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.
18
D0 (LSB)
O
Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
19
DZ
O
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
20
DZ
O
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
21
DZ
O
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
22
DZ
O
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
23
BYTE
I
Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH).
24
R/C
I
With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C
enables the parallel output.
Analog Ground.
Digital Ground.
25
CS
I
Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.
26
BUSY
O
At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs
have been updated.
27
VANA
Analog Supply Input. Nominally +5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors.
28
VDIG
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA.
TABLE I. Pin Assignments.
4
ADS7804
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SBAS019A
BASIC OPERATION
CS
R/C
BUSY
1
X
X
None. Databus is in Hi-Z state.
↓
0
1
Initiates conversion ‘n’. Databus remains
in Hi-Z state.
0
↓
1
Initiates conversion ‘n’. Databus enters Hi-Z
state.
0
1
↑
Conversion ‘n’ completed. Valid data from
conversion ‘n’ on the databus.
↓
1
1
Enables databus with valid data from
conversion ‘n’.
↓
1
0
Enables databus with valid data from
conversion ‘n-1’(1). Conversion n in process.
0
↑
0
Enables databus with valid data from
conversion ‘n-1’(1). Conversion ‘n’ in process.
0
0
↑
New conversion initiated without acquisition
of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.
X
X
0
New convert commands ignored. Conversion
‘n’ in process.
Figure 1 shows a basic circuit to operate the ADS7804 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (6µs max) will initiate a conversion. BUSY
(pin 26) will go LOW and stay LOW until the conversion is
completed and the output registers are updated. Data will be
output in Binary Two’s Complement with the MSB on pin 6.
BUSY going HIGH can be used to latch the data. All convert
commands will be ignored while BUSY is LOW.
The ADS7804 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert commands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain
will be corrected in software (refer to the Calibration section).
OPERATION
NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion “n-1”.
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) LOW for a
minimum of 40ns immediately puts the sample/hold of the
ADS7804 in the hold state and starts conversion ‘n’. BUSY
(pin 26) will go LOW and stay LOW until conversion ‘n’ is
completed and the internal output register has been updated.
All new convert commands during BUSY LOW will be ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without sufficient
time to acquire a new signal.
The ADS7804 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert commands assures accurate acquisition of a new signal. Refer to
Table II for a summary of CS, R/C, and BUSY states and
Figures 3 through 5 for timing diagrams.
Table II. Control Line Functions for Read and Convert.
CS and R/C are internally OR’d and level triggered. There is
not a requirement which input goes LOW first when initiating
a conversion. If, however, it is critical that CS or R/C initiates
conversion ‘n’, be sure the less critical input is LOW at least
10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output will become active
whenever R/C goes HIGH. Refer to the Reading Data section.
200Ω
33.2kΩ
+
1
28
2
27
2.2µF
3
26
4
25
5
24
B11 (MSB)
6
23
B10
7
+
0.1µF
+
+5V
10µF
BUSY
2.2µF
+
R/C
22
LOW
ADS7804
B9
8
21
LOW
B8
9
20
LOW
B7
10
19
LOW
B6
11
18
B0 (LSB)
B5
12
17
B1
B4
13
16
B2
14
15
B3
Convert Pulse
40ns min
6µs max
FIGURE 1. Basic Operation.
ADS7804
SBAS019A
www.ti.com
5
READING DATA
PARALLEL OUTPUT (During a Conversion)
The ADS7804 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS (pin
25) is LOW. Any other combination of CS and R/C will tristate the parallel output. Valid conversion data can be read
in a full parallel, 12-bit word or two 8-bit bytes on pins 6-13
and pins 15-22. BYTE (pin 23) can be toggled to read both
bytes within one conversion cycle. Refer to Table III for ideal
output codes and Figure 2 for bit locations relative to the
state of BYTE.
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
DESCRIPTION
ANALOG INPUT
Full Scale Range
±10V
Least Significant
Bit (LSB)
4.88mV
+Full Scale
(10V – 1LSB)
Midscale
One LSB below
Midscale
–Full Scale
BINARY CODE
9.99512V
After conversion ‘n’ has been initiated, valid data from conversion ‘n-1’ can be read and will be valid up to 16µs after the
start of conversion ‘n’. Do not attempt to read data from 16µs
after the start of conversion ‘n’ until BUSY (pin 26) goes
HIGH; this may result in reading invalid data. Refer to Table
IV and Figures 3 and 5 for timing specifications.
Note! For the best possible performance, data should not be
read during a conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate the
output mode of the converter. See Figure 3.
HEX CODE
0111 1111 1111
SYMBOL
DESCRIPTION
t1
Convert Pulse Width
MIN TYP MAX UNITS
6000
ns
7FF
t2
Data Valid Delay after R/C LOW
8
µs
BUSY Delay from R/C LOW
BUSY LOW
65
8
ns
µs
40
0V
0000 0000 0000
000
t3
t4
–4.88mV
1111 1111 1111
FFF
t5
BUSY Delay after
End of Conversion
220
ns
–10V
1000 0000 0000
800
t6
Aperture Delay
40
ns
7.6
Table III. Ideal Input Voltages and Output Codes.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 26) will go HIGH. Valid data
from conversion ‘n’ will be available on D11-D0 (pin 6-13 and
15-18 when BYTE is LOW). BUSY going HIGH can be used
to latch the data. Refer to Table IV and Figures 3 and 5 for
timing specifications.
8
µs
2
µs
83
ns
t7
Conversion Time
t8
Acquisition Time
t9
Bus Relinquish Time
10
35
t10
BUSY Delay after Data Valid
50
200
ns
t11
Previous Data Valid
after R/C LOW
7.4
µs
t7 + t6
Throughput Time
t12
R/C to CS Setup Time
10
t13
Time Between Conversions
10
t14
Bus Access Time
and BYTE Delay
10
9
10
µs
ns
µs
83
ns
TABLE IV. Conversion Timing.
BYTE LOW
BYTE HIGH
+5V
Bit 11 (MSB)
6
Bit 10
7
23
Bit 3
6
22 LOW
Bit 2
7
ADS7804
23
22 Bit 4
ADS7804
Bit 9
8
21 LOW
Bit 1
8
21 Bit 5
Bit 8
9
20 LOW
Bit 0 (LSB)
9
20 Bit 6
Bit 7 10
19 LOW
LOW 10
19 Bit 7
Bit 6 11
18 Bit 0 (LSB)
LOW 11
18 Bit 8
Bit 5 12
17 Bit 1
LOW 12
17 Bit 9
Bit 4 13
16 Bit 2
LOW 13
16 Bit 10
14
15 Bit 3
14
15 Bit 11
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).
6
ADS7804
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SBAS019A
t1
R/C
t13
t2
t4
BUSY
t3
t6
t5
Convert
Acquire
MODE
Acquire
t7
DATA BUS
Previous
Data Valid
t8
Previous
Data Valid
Hi-Z
t9
Convert
Not Valid
Data Valid
Hi-Z
Data Valid
t10
t11
FIGURE 3. Conversion Timing with Outputs Enabled after Conversion (CS Tied LOW.)
t12
t12
t12
t12
R/C
t1
CS
t3
t4
BUSY
t6
MODE
Convert
Acquire
Acquire
t7
Hi-Z State
DATA BUS
Data Valid
Hi-Z State
t9
t14
FIGURE 4. Using CS to Control Conversion and Read Timing.
t12
t12
R/C
CS
BYTE
Pins 6 - 13
Hi-Z
High Byte
t14
Pins 15 - 22
Hi-Z
Low Byte
Low Byte
t14
High Byte
Hi-Z
t9
Hi-Z
FIGURE 5. Using CS and BYTE to Control Data Bus.
ADS7804
SBAS019A
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7
INPUT RANGES
HARDWARE CALIBRATION
The ADS7804 offers a standard ±10V input range. Figure 6
shows the necessary circuit connections for the ADS7804
with and without hardware trim. Offset and full scale error(1)
specifications are tested and guaranteed with the fixed
resistors shown in Figure 6b. Adjustments for offset and
gain are described in the Calibration section of this data
sheet.
To calibrate the offset and gain of the ADS7804, install the proper
resistors and potentiometers as shown in Figure 6a. The calibration range is ±15mV for the offset and ±60mV for the gain.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and
gain will be corrected in software (refer to the Calibration
section).
The nominal input impedance of 23kW results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external resistors. The input resistor divider network provides inherent
overvoltage protection guaranteed to at least ±25V. The 1%
resistors used for the external circuitry do not compromise
the accuracy or drift of the converter. They have little influence relative to the internal resistors, and tighter tolerances
are not required.
SOFTWARE CALIBRATION
To calibrate the offset and gain of the ADS7804 in software,
no external resistors are required. See the No Calibration
section for details on the effects of the external resistors.
Refer to Table V for range of offset and gain errors with and
without external resistors.
NO CALIBRATION
See Figure 6b for circuit connections. The external resistors
shown in Figure 6b may not be necessary in some applications.
These resistors provide compensation for an internal adjustment
of the offset and gain which allows calibration with a single supply.
The nominal transfer function of the ADS7804 will be bound by
the shaded region seen in Figure 7 with a typical offset of –30mV
and a typical gain error of –1.5%. Refer to Table V for range of
offset and gain errors with and without external resistors.
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
CALIBRATION
The ADS7804 can be trimmed in hardware or software. The
offset should be trimmed before the gain since the offset
directly affects the gain. To achieve optimum performance,
several iterations may be required.
WITH
EXTERNAL
RESISTORS
WITHOUT
EXTERNAL
RESISTORS
UNITS
BPZ
–10 < BPZ < 10
–2 < BPZ < 2
–45 < BPZ < 5
–8 < BPZ < 1
mV
LSBs
Gain
Error
–0.5 < error < 0.5
–0.25 < error < 0.25(1)
–0.6 < error < –0.55
–0.45 < error < –0.3(1)
% of FSR
NOTE: (1) High Grade.
TABLE VII. Bipolar Offset and Gain Errors With and Without
External Resistors.
±10V With Hardware
a)
±10V Without Hardware
b)
Trim
Trim
200Ω
1
±10V
2
33.2kΩ
+5V
2.2µF
50kΩ
Offset
50kΩ
+
3
200Ω
1
±10V
VIN
2
AGND1
33.2kΩ
2.2µF
+
REF
3
VIN
AGND1
REF
576kΩ
4
Gain
2.2µF
4
CAP
+
2.2µF
5
5
AGND2
CAP
+
AGND2
NOTE: Use 1% metal film resistors.
FIGURE 6. Circuit Diagram With and Without External Resistors.
8
ADS7804
www.ti.com
SBAS019A
Digital
Output
7FF
–10V
–9.99983V –9.9998V
–50mV
9.9997V
–15mV
9.999815V
+10V
Analog
Input
Ideal Transfer Function
With External Resistors
Range of Transfer Function
Without External Resistors
800
FIGURE 7. Full Scale Transfer Function.
REFERENCE
The ADS7804 can operate with its internal 2.5V reference or
an external reference. By applying an external reference to
pin 5, the internal reference can be bypassed. The reference
voltage at REF is buffered internally with the output on CAP
(pin 4).
The internal reference has an 8 ppm/°C drift (typical) and
accounts for approximately 20% of the full scale error
(FSE = ±0.5% for low grade, ±0.25% for high grade).
REF
REF (pin 3) is an input for an external reference or the output
for the internal 2.5V reference. A 2.2µF capacitor should be
connected as close to the REF pin as possible. The capacitor
and the output resistance of REF create a low pass filter to
bandlimit noise on the reference. Using a smaller value
capacitor will introduce more noise to the reference degrading the SNR and SINAD. The REF pin should not be used to
drive external AC or DC loads.
The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size of
the converter which can improve the SNR.
CAP
CAP (pin 4) is the output of the internal reference buffer. A
2.2µF capacitor should be placed as close to the CAP pin as
possible to provide optimum switching currents for the CDAC
throughout the conversion cycle and compensation for the
output of the internal buffer. Using a capacitor any smaller
than 1µF can cause the output buffer to oscillate and may not
have sufficient charge for the CDAC. Capacitor values larger
than 2.2µF will have little affect on improving performance.
The output of the buffer is capable of driving up to 2mA of
current to a DC load. DC loads requiring more than 2mA of
current from the CAP pin will begin to degrade the linearity
of the ADS7804. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC
loads. Do not attempt to directly drive an AC load with the
output voltage on CAP. This will cause performance degradation of the converter.
ADS7804
SBAS019A
www.ti.com
9
LAYOUT
SIGNAL CONDITIONING
POWER
For optimum performance, tie the analog and digital power pins
to the same +5V power supply and tie the analog and digital
grounds together. As noted in the electrical specifications, the
ADS7804 uses 90% of its power for the analog circuitry. The
ADS7804 should be considered as an analog component.
The +5V power for the A/D should be separate from the +5V
used for the system’s digital logic. Connecting VDIG (pin 28)
directly to a digital supply can reduce converter performance
due to switching noise from the digital logic. For best performance, the +5V supply can be produced from whatever
analog supply is used for the rest of the analog signal
conditioning. If +12V or +15V supplies are present, a simple
+5V regulator can be used. Although it is not suggested, if
the digital supply must be used to power the converter, be
sure to properly filter the supply. Either using a filtered digital
supply or a regulated analog supply, both VDIG and VANA
should be tied to the same +5V source.
GROUNDING
Three ground pins are present on the ADS7804. DGND is
the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground which all analog signals
internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path
of least resistance back to the power supply.
All the ground pins of the A/D should be tied to the analog
ground plane, separated from the system’s digital logic ground,
to achieve optimum performance. Both analog and digital
ground planes should be tied to the “system” ground as near
to the power supplies as possible. This helps to prevent
dynamic digital ground currents from modulating the analog
ground through a common impedance to power ground.
10
The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The FET
switch on the ADS7804, compared to the FET switches on
other CMOS A/D converters, releases 5%-10% of the charge.
There is also a resistive front end which attenuates any
charge which is released. The end result is a minimal
requirement for the anti-alias filter on the front end. Any op
amp sufficient for the signal in an application will be sufficient
to drive the ADS7804.
The resistive front end of the ADS7804 also provides a
guaranteed ±25V overvoltage protection. In most cases, this
eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS7804 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversion, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus. Tri-state outputs
can also be used when the A/D is the only peripheral on the
data bus.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7804 has an internal LSB size of 610µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance. The effects of this phenomenon will
be more obvious when using the pin-compatible ADS7805 or
any of the other 16-bit converters in the ADS Family. This is
due to the smaller internal LSB size of 38µV.
ADS7804
www.ti.com
SBAS019A
PACKAGE DRAWINGS
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
PINS **
A
24
28
A MAX
1.260
(32,04)
1.425
(36,20)
A MIN
1.230
(31,24)
1.385
(35,18)
B MAX
0.310
(7,87)
0.315
(8,00)
B MIN
0.290
(7,37)
0.295
(7,49)
DIM
24
13
0.280 (7,11)
0.250 (6,35)
1
12
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040050 / B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
ADS7804
SBAS019A
www.ti.com
11
PACKAGE DRAWINGS (Cont.)
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0° – 8°
A
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
18
20
24
28
A MAX
0.410
(10,41)
0.462
(11,73)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.453
(11,51)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000 / E 08/01
NOTES: A.
B.
C.
D.
12
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
ADS7804
www.ti.com
SBAS019A
PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS7804U
LIFEBUY
SOIC
DW
28
20
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS7804U
B
ADS7804U/1K
LIFEBUY
SOIC
DW
28
1000
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
ADS7804U
B
ADS7804UB
LIFEBUY
SOIC
DW
28
20
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
ADS7804U
B
ADS7804UG4
LIFEBUY
SOIC
DW
28
20
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS7804U
B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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