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SN74AHCT16245
SCLS335K – MARCH 1996 – REVISED OCTOBER 2014
SN74AHCT16245 16-Bit Bus Transceivers With 3-State Outputs
1 Features
3 Description
•
The SN74AHCT16245 device is a 16-bit (dual-octal)
noninverting 3-state transceiver designed for
synchronous two-way communication between data
buses.
1
•
•
•
•
Members of Texas Instruments’
Widebus™ Family
Inputs are TTL-Voltage Compatible
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 250 mA
Per JESD 17
2 Applications
•
•
•
•
•
Device Information(1)
PART NUMBER
SN74AHCT16245
PACKAGE
BODY SIZE (NOM)
TVSOP (48)
9.70 mm × 4.40 mm
SSOP (48)
15.80 mm × 7.50 mm
TSSOP (48)
12.50 mm × 6.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Telecom and Wireless Infrastructures
Electronic Points of Sale
Printers and Other Peripherals
Motor Drives
Health and Fitness
4 Simplified Schematic
1OE
1DIR
G3
3 EN1 [BA]
3 EN2 [AB]
2OE
2DIR
G6
6 EN4 [BA]
6 EN5 [AB]
1A1
1B1
1
2
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
1A8
2A1
1B8
2B1
4
5
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
2A7
2B7
2A8
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHCT16245
SCLS335K – MARCH 1996 – REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
5
5
5
6
6
7
7
7
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Noise Characteristics ................................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
9
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ................................................................... 9
Functional Block Diagrams ....................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1 Trademarks ........................................................... 13
13.2 Electrostatic Discharge Caution ............................ 13
13.3 Glossary ................................................................ 13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
Changes from Revision J (October 2000) to Revision K
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Deleted SN54AHCT16245 device from data sheet................................................................................................................ 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Pin Functions table...................................................................................................................................................... 3
•
Added Handling Ratings table. ............................................................................................................................................... 5
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 5
•
Added Thermal Information table. .......................................................................................................................................... 6
•
Added –40°C to 125°C range for SN74AHCT16245 in Electrical Characteristics table. ....................................................... 6
•
Added TA = –40°C to 125°C for SN74AHCT16245 in the Switching Characteristics table.................................................... 7
•
Added Typical Characteristics. ............................................................................................................................................... 7
•
Added Detailed Description section........................................................................................................................................ 9
•
Added Application and Implementation section.................................................................................................................... 11
•
Added Power Supply Recommendations and Layout sections............................................................................................ 12
2
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6 Pin Configuration and Functions
SN74AHCT16245 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
Pin Functions
PIN
I/O
DESCRIPTION
1DIR
I
Direction pin 1
1B1
I/O
1B1 input or output
3
1B2
I/O
1B2 input or output
4
GND
—
Ground pin
5
1B3
I/O
1B3 input or output
6
1B4
I/O
1B4 input or output
7
VCC
—
Power pin
8
1B5
I/O
1B5 input or output
9
1B6
I/O
1B6 input or output
10
GND
—
Ground pin
11
1B7
I/O
1B7 input or output
12
1B8
I/O
1B8 input or output
13
2B1
I/O
2B1 input or output
14
2B2
I/O
2B2 input or output
15
GND
—
Ground pin
16
2B3
I/O
2B3 input or output
17
2B4
I/O
2B4 input or output
18
VCC
—
Power pin
NO.
NAME
1
2
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SCLS335K – MARCH 1996 – REVISED OCTOBER 2014
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Pin Functions (continued)
PIN
4
I/O
DESCRIPTION
2B5
I/O
2B5 input or output
2B6
I/O
2B6 input or output
21
GND
—
Ground pin
22
2B7
I/O
2B7 input or output
23
2B8
I/O
2B8 input or output
24
2DIR
—
Direction pin 2
25
2OE
I
26
2A8
I/O
2A8 input or output
27
2A7
I/O
2A7 input or output
28
GND
—
Ground pin
29
2A6
I/O
2A6 input or output
30
2A5
I/O
2A5 input or output
31
VCC
—
Power pin
32
2A4
I/O
2A4 input or output
33
2A3
I/O
2A3 input or output
34
GND
—
Ground pin
35
2A2
I/O
2A2 input or output
36
2A1
I/O
2A1 input or output
37
1A8
I/O
1A8 input or output
38
1A7
I/O
1A7 input or output
39
GND
—
Ground pin
40
1A6
I/O
1A6 input or output
41
1A5
I/O
1A5 input or output
42
VCC
—
Power pin
43
1A4
I/O
1A4 input or output
44
1A3
I/O
1A3 input or output
45
GND
—
Ground pin
46
1A2
I/O
1A2 input or output
47
1A1
I/O
1A1 input or output
48
1OE
I
NO.
NAME
19
20
Output Enable 2
Output Enable 1
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
VI
Control Inputs
Input voltage range
VO
I/O
Output voltage range (2)
IIK
Control Inputs
Input clamp current
VI < 0
–20
mA
IOK
I/O
Output clamp current
VO < 0 or VO > VCC
±20
mA
Continuous output current
VO = 0 to VCC
±25
mA
±75
mA
IO
Continuous current through VCC or GND
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
°C
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
1500
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN74AHCT16245
MIN
MAX
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VIO
Input/Output voltage, A or B pins
IOH
High-level output current
–8
IOL
Low-level output current
8
mA
Δt/Δv
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
125
°C
(1)
2
V
V
0.8
V
0
5.5
V
0
VCC
V
–40
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI Application Report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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7.4 Thermal Information
SN74AHCT16245
THERMAL METRIC (1)
DGG
DGV
DL
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
68.1
79.3
61.0
RθJC(top)
Junction-to-case (top) thermal resistance
22.6
31.3
30.8
RθJB
Junction-to-board thermal resistance
35.0
42.3
32.8
ψJT
Junction-to-top characterization parameter
1.3
2.4
8.4
ψJB
Junction-to-board characterization parameter
34.7
41.8
32.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
VOH
IOH = –8 mA
IOL = 50 µA
VOL
IOL = 8 mA
II
OE or DIR
VI = VCC or GND
IOZ (1)
A or B
Inputs
VO = VCC or GND
ICC
ΔICC
(2)
Ci
OE or DIR
Cio
A or B
Inputs
(1)
(2)
6
TA = 25°C
VCC
4.5 V
MIN
TYP
4.4
4.5
MAX
3.94
4.5 V
0 V to
5.5 V
–40°C to 125°C
SN74AHCT16245
SN74AHCT16245
MIN
MAX
MIN
4.4
4.4
3.8
3.8
UNIT
MAX
V
0.1
0.1
0.1
0.36
0.44
0.44
±0.1
±1
±1
µA
±0.25
±2.5
±2.5
µA
V
VI = VCC or GND, IO = 0
5.5 V
4
40
40
µA
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
1.35
1.5
1.5
mA
10
10
10
pF
VI = VCC or GND
5V
2.5
5V
4
pF
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
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7.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
B or A
CL = 15 pF
tPZH
OE
A or B
CL = 15 pF
OE
A or B
CL = 15 pF
A or B
B or A
CL = 50 pF
OE
A or B
CL = 50 pF
OE
A or B
CL = 50 pF
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
(1)
(2)
TA = 25°C
TA = –40°C to 125°C
SN74AHCT16245
SN74AHCT16245
UNIT
TYP
MAX
MIN
MAX
MIN
MAX
4.5 (1)
8.5 (1)
1
9.5
1
11
4.5
(1)
8.5 (1)
1
9.5
1
11
8.9
(1)
(1)
1
14
1
15
8.9 (1)
13 (1)
1
14
1
15
9.2 (1)
14 (1)
1
15
1
15.7
9.2 (1)
14 (1)
1
15
1
15.7
13
7
9.5
1
10.5
1
12
5.3
9.5
1
10.5
1
12
8.3
14
1
15
1
16
8.3
14
1
15
1
16
8
14
1
15
1
15.7
8
14
1
15
1
15.7
1 (2)
CL = 50 pF
1
ns
ns
ns
ns
ns
ns
1
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
7.7 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
SN74AHCT16245
PARAMETER
MIN
TYP
UNIT
MAX
VOL(P)
Quiet output, maximum dynamic VOL
0.6
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.6
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4.8
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
V
2
V
0.8
V
Characteristics are for surface-mount packages only.
7.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
TYP
UNIT
17
pF
7.9 Typical Characteristics
6
5
TPD (ns)
4
3
2
1
TPD in ns
0
-100
-50
0
50
Temperature (qC)
100
150
D001
Figure 1. TPD vs Temperature
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8 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
1.5 V
1.5 V
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
3V
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The SN74AHCT16245 device is a 16-bit (dual-octal) noninverting 3-state transceiver designed for synchronous
two-way communication between data buses. The control-function implementation minimizes external timing
requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
9.2 Functional Block Diagrams
1OE
1DIR
G3
3 EN1 [BA]
3 EN2 [AB]
2OE
2DIR
G6
6 EN4 [BA]
6 EN5 [AB]
1A1
1B1
1
2
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
1A8
1B8
2A1
2B1
4
5
A.
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
2A7
2B7
2A8
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Figure 3. Logic Symbol
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Functional Block Diagrams (continued)
1DIR
2DIR
1OE
1A1
2OE
2A1
1B1
2B1
To Seven Other Channels
To Seven Other Channels
Figure 4. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
TTL inputs
– Lowered switching threshold allows up translation 3.3 V to 5 V
Slow edges reduce output ringing
9.4 Device Functional Modes
Table 1. Function Table
(Each 8-bit Transceiver)
INPUTS
OE
10
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
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10 Application and Implementation
10.1 Application Information
The SN74AHCT16245 is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V
VIL and 2-V VIH. This feature makes the device ideal for translating up from 3.3 V to 5 V. Figure 6 shows this type
of translation.
10.2 Typical Application
Regulated 5 V to 3.3 V
Regulated 3.3 V
Regulated 5 V
OE
VCC
OE
DIR
A1
DIR
B1
µC or other
system boards
A8
VCC
µC or other
system boards
B8
µC
LEDs or Relays
or other
system boards
GND
A1
B1
A8
B8
GND
µC
LEDs or Relays
or other
system boards
Figure 5. Typical Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 25 mA per output and 75 mA total for the part.
– Outputs should not be pulled above VCC.
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Typical Application (continued)
10.2.3 Application Curves
Voltage (1 V/ div)
Output Voltage
Input Voltage
Time (5 ns/div), VCC = 5 V
Figure 6. Up Translation
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended and if there are multiple VCC pins than 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
12
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Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT16245
SN74AHCT16245
www.ti.com
SCLS335K – MARCH 1996 – REVISED OCTOBER 2014
13 Device and Documentation Support
13.1 Trademarks
Widebus is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT16245
13
PACKAGE OPTION ADDENDUM
www.ti.com
8-Sep-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
74AHCT16245DGGRG4
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT16245
Samples
74AHCT16245DLRG4
ACTIVE
SSOP
DL
48
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT16245
Samples
SN74AHCT16245DGGR
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT16245
Samples
SN74AHCT16245DGVR
ACTIVE
TVSOP
DGV
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HF245
Samples
SN74AHCT16245DL
LIFEBUY
SSOP
DL
48
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT16245
SN74AHCT16245DLR
ACTIVE
SSOP
DL
48
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT16245
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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