TSU5N65M

650V N-Channel MOSFET General Description Features This Power MOSFET is produced using Truesemi‘s advanced planar stripe DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switched mode power supplies, active power factor correction based on half bridge topology. Absolute Maximum Ratings Symbol • 3.0A,650V,Max.RDS(on)=3.27 Ω @ VGS =10V • Low gate charge(typical 16nC) • High ruggedness • Fast switching • 100% avalanche tested • Improved dv/dt capability TJ=25℃ unless otherwise specified Parameter Value Units VDSS Drain-Source Voltage 650 V VGS Gate-Source Voltage ± 30 V TC = 25℃ 3.0 A TC = 100℃ 1.8 A ID Drain Current IDM Pulsed Drain Current (Note 1) 12 A EAS Single Pulsed Avalanche Energy (Note 2) 210 mJ EAR Repetitive Avalanche Energy (Note 1) 5.8 mJ dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns 58 W 0.46 W/℃ -55 to +150 ℃ 300 ℃ PD TJ, TSTG TL Power Dissipation (TC = 25℃) -Derate above 25℃ Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8” from case for 5 seconds * Drain current limited by maximum junction temperature. Thermal Resistance Characteristics Symbol Parameter Max Units RθJC Thermal Resistance,Junction-to-Case 2.16 ℃/W RθJA Thermal Resistance,Junction-to-Ambient* 50 ℃/W RθJA Thermal Resistance,Junction-to-Ambient 110 ℃/W © 2018 Truesemi Semiconductor Corporation Ver.B4 www.truesemi.com TSD5N65M/TSU5N65M TSD5N65M/TSU5N65M Symbol unless otherwise specified Parameter Test Conditions Min Typ Max Units Gate Threshold Voltage VDS = VGS, ID = 250 uA㎂ 2.0 -- 4.0 V Static Drain-Source On-Resistance VGS = 10 V, ID =1.5A -- 2.5 3.27 Ω Forward Transconductance VDS=40V,ID=1.5A -- 4.7 -- S 650 -- -- V ID = 250 uA, Referenced to 25℃ -- 0.65 -- V/℃ VDS = 650 V, VGS = 0 V -- -- 10 uA VDS = 520 V, TJ = 125℃ -- -- 10 uA On Characteristics VGS RDS(ON) gFS (Note 4) Off Characteristics BVDSS Drain-Source Breakdown Voltage △BVDSS Breakdown Voltage Temperature / △TJ Coefficient VGS = 0 V, ID = 250 uA㎂ IDSS Zero Gate Voltage Drain Current IGSSF Gate-Body Leakage Current,Forward VGS = 30 V, VDS = 0 V -- -- 100 nA㎁ IGSSR Gate-Body Leakage Current,Reverse VGS =- 30 V, VDS = 0 V -- -- -100 nA㎁ -- 560 -- pF㎊ -- 55 -- pF㎊ -- 7 -- pF -- 10 -- ns -- 40 -- ns㎱ -- 40 -- ns㎱ -- 50 -- ns㎱ -- 16 -- nC -- 2.5 -- nC -- 6.5 -- nC Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz Switching Characteristics td(on) Turn-On Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd VDS = 300 V, ID = 4.5A, RG = 25 Ω (Note 4,5) VDS = 480 V, ID = 4.5A, VGS = 10 V (Note 4,5) Gate-Drain Charge Source-Drain Diode Maximum Ratings and Characteristics IS Continuous Source-Drain Diode Forward Current -- -- 3.0 ISM Pulsed Source-Drain Diode Forward Current -- -- 12 VSD Source-Drain Diode Forward Voltage IS =3.0A, VGS = 0 V -- -- 1.4 trr Reverse Recovery Time IS =4.5A, VGS = 0 V -- 300 -- ns㎱ Qrr Reverse Recovery Charge diF/dt = 100 A/μs -- 2.0 -- uC (Note 4) A V NOTES: 1. 2. 3. 4. 5. Repetitive Rating: Pulse width limited by maximum junction temperature IAS=4.5A, VDD=50V, RG=25 Ω,Starting TJ=25 ℃ ISD≤4.5A, di/dt ≤ 200A/us, VDD ≤ BVDSS, Starting TJ = 25 ℃ Pulse Test: Pulse width ≤ 300us, Duty Cycle ≤ 2% Essentially Independent of Operating Temperature Typical Characteristics © 2018 Truesemi Semiconductor Corporation Ver.B4 www.truesemi.com TSD5N65M/TSU5N65M Electrical Characteristics TJ=25 ℃ TSD5N65M/TSU5N65M Typical Characteristics Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature Figure 3. On-Resistance Variation vs Drain Current and Gate Voltage Figure 6. Gate Charge Characteristics Figure 5. Capacitance Characteristics © 2018 Truesemi Semiconductor Corporation Ver.B4 www.truesemi.com TSD5N65M/TSU5N65M Typical Characteristics Figure 7. Breakdown Voltage Variation vs Temperature Figure 8. On-Resistance Variation vs Temperature Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs Case Temperature Figure 11. Transient Thermal Response Curve © 2018 Truesemi Semiconductor Corporation Ver.B4 www.truesemi.com TSD5N65M/TSU5N65M Fig 12. Gate Charge Test Circuit & Waveform 50KΩ 12V VGS Same Type as DUT Qg 200nF 10V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Fig 13. Resistive Switching Test Circuit & Waveforms RL VDS VDS 90% VDD RG ( 0.5 rated VDS ) Vin DUT 10V 10% td(on) tr td(off) t on tf t off Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms L 1 EAS = ---- LL IAS2 2 VDS VDD ID BVDSS IAS RG ID (t) 10V DUT VDS (t) VDD tp © 2018 Truesemi Semiconductor Corporation Ver.B4 Time www.truesemi.com TSD5N65M/TSU5N65M Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ IS L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • IS controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current IS ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VDD Vf Body Diode Forward Voltage Drop © 2018 Truesemi Semiconductor Corporation Ver.B4 www.truesemi.com TSD5N65M/TSU5N65M Package Dimension TO-252(D-PAK)(A) © 2018 Truesemi Semiconductor Corporation Ver.B4 www.truesemi.com TSD5N65M/TSU5N65M Package Dimension TO-252(D-PAK)(B) © 2018 Truesemi Semiconductor Corporation Ver.B4 www.truesemi.com TSD5N65M/TSU5N65M Package Dimension TO-251(I-PAK)(A) © 2018 Truesemi Semiconductor Corporation Ver.B4 www.truesemi.com TSD5N65M/TSU5N65M Package Dimension TO-251(I-PAK)(B) © 2018 Truesemi Semiconductor Corporation Ver.B4 www.truesemi.com