74HC02N

74HC02 Quad 2−Input NOR Gate High−Performance Silicon−Gate CMOS FEATURES          Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A ESD Performance: HBM 2000 V; Machine Model 200 V Chip Complexity: 40 FETs or 10 Equivalent Gates These are Pb−Free Devices DIP14 SOP14 TSSOP14 ORDERING INFORMATION DEVICE Package Type MARKING Packing Packing Qty 74HC02N DIP14 74HC02 TUBE 1000pcs/box 74HC02M/TR SOP14 74HC02 REEL 2500pcs/reel TSSOP14 74HC02 REEL 2500pcs/reel 74HC02MT/TR http://www.hgsemi.com.cn 1/8 2019 MAY 74HC02 LOGIC DIAGRAM FUNCTION TABLE Inputs A L L H H http://www.hgsemi.com.cn B L H L H 2/8 Output Y H L L L 2019 MAY 74HC02 PIN ASSIGNMENT DIP14/SOP14/TSSOP14 MAXIMUM RATINGS Symbol VCC Vin Vout Iin Parameter Value Unit – 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Supply Voltage (Referenced to GND) DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, SOP Package TSSOP Package 500 450 mW Tstg Storage Temperature – 65 to + 150 °C 260 °C TL Lead Temperature, 1 mm from Case for 10 Seconds SOP or TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance cir- cuit. For proper operation, Vin and Vout should be constrained to the range GND ≤ (Vin or Vout) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).Unused outputs must be left open. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not im- plied. Extended exposure to stresses above the Recommended Operating Conditions may af- fect device reliability. Derating SOP Package: 7 mW/°C from 65° to 125°C ；TSSOP Package: 6.1 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time(Figure 1) http://www.hgsemi.com.cn VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 3/8 Min Max Unit 2.0 6.0 V 0 VCC V -40 + 85 °C 0 0 0 1000 500 400 ns 2019 MAY 74HC02 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 Vin = VCC or GND 6.0 0.1 1.0 Vin = VCC or GND |Iout| = 0 µA 6.0 VIH VIL Maximum Low−Level Input Vout = 0.1 V or VCC – 0.1 V Voltage |Iout| ≤ 20 µA VOL Iin ICC Vin = VIH or VIL |Iout| ≤ 20 µA Minimum High−Level OutputVoltage Vin = VIH or VIL mA |Iout| ≤ 4.0 mA |Iout| ≤ 5.2 mA |Iout| ≤ 2.4 Vin = VIH or VIL |Iout| ≤ 20 µA Maximum Low−Level OutputVoltage Maximum Input Leakage Current Maximum Quiescent SupplyCurrent (per Package) Guaranteed Limit -40 to 25°C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 Minimum High−Level Input Vout = 0.1 V or VCC – 0.1 V Voltage |Iout| ≤ 20 µA VOH VCC (V) Vin = VIH or VIL mA |Iout| ≤ 4.0 mA |Iout| ≤ 5.2 mA |Iout| ≤ 2.4 ≤ 85°C ≤ 125°C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.0 20 1.0 40 Unit V V V V µA µA AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol VCC (V) Parameter tPLH, tPHL Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) Cin CPD Maximum Input Capacitance Power Dissipation Capacitance (Per Gate)* http://www.hgsemi.com.cn 4/8 Guaranteed Limit Unit -40 to ≤ 85°C ≤ 125°C 25°C 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 75 30 15 13 75 30 15 13 95 40 19 16 95 40 19 16 110 55 22 19 110 55 22 19 — 10 10 10 Typical @ 25 ns pF C, VCC = 5.0 V 22 ns pF 2019 MAY 74HC02 Figure 1. Switching Waveforms Figure 2. Test Circuit Figure 3. Expanded Logic Diagram (1/4 of the Device) http://www.hgsemi.com.cn 5/8 2019 MAY 74HC02 Physical Dimensions SOP14 Q A C C1 B D A1 a 0.25 b Dimensions In Millimeters(SOP14) A A1 B C C1 D Min： 1.35 0.05 8.55 5.80 3.80 0.40 0° 0.35 Max： 1.55 0.20 8.75 6.20 4.00 0.80 8° 0.45 Q a Symbol： Q a b 1.27 BSC TSSOP14 Dimensions In Millimeters(TSSOP14) A A1 B C C1 D Min： 0.85 0.05 4.90 6.20 4.30 0.40 0° 0.20 Max： 0.95 0.20 5.10 6.60 4.50 0.80 8° 0.25 Symbol： http://www.hgsemi.com.cn 6/8 b 0.65 BSC 2019 MAY 74HC02 Physical Dimensions DIP14 B L1 L E D1 D d A c a Dimensions In Millimeters(DIP14) A B D D1 E L L1 a c Min： 6.10 18.94 8.40 7.42 3.10 0.50 3.00 1.50 0.40 Max： 6.68 19.56 9.00 7.82 3.55 0.70 3.60 1.55 0.50 Symbol： http://www.hgsemi.com.cn 7/8 d 2.54 BSC 2019 MAY 74HC02 IMPORTANT STATEMENT: Huaguan Semiconductor reserves the right to change its products and services without notice. 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