100VDS/±20VGS/15A(ID) N-Channel Enhancement Mode MOSFET
Features
Applications
VDSS=100V/VGSS=±20V/ID=15A
RDS(ON)=105mΩ(Max.)@VGS=10V
RDS(ON)=175mΩ(Max.)@VGS=4.5V
ESD protect
Reliable and Rugged
High Density Cell Design For Ultra Low
On-Resistance
HD1H15A
Synchronous Rectification
Power Management in Inverter System
TO-252
TO-251
Chip Diagram
HD1H15A
1.Gate 2. Drain 3. Source
Physical Characteristics
Switching Time Test Circuit and
Waveforms
Wafer Diameter 8 inches (± 0.1 inche)
Wafer Thickness: 8mils (±0.6 mil)
Die size: 1700μm x 1240μm (Including scribe
line)
Scribe Line Width: 60um
Gross die: 12,549
Metalization:
Frontside: Al/Si/Cu
Backside: Ti/Ni/Ag
Metal thickness:
Front-side: 4.0μm
Back0side: 1.4μm
Bonding Area:
Gate: 300μm x 430μm
(Die edge to gate metal 34μm)
Source: Full metalized surface of source region
(Die edge to source metal 51μm)
Recommended wire bonding:
Gate:1.5mils Au wire x 1
Source: 12mils Al wire x 1
Recommended package: SOP-8(Dual)
Rev. A.0 – Feb., 2012
1
100VDS/±20VGS/15A(ID) N-Channel Enhancement Mode MOSFET
HD1H15A
Absolute Maximum Ratings (TA=25°C unless otherwise noted)
Symbol
VDSS
VGSS
ID1
IDM1
IS1
TJ
TSTG
Parameter
Drain-Source Voltage
Gate –Source Voltage
TC=70°C
Continuous Drain Current
TC=25°C
300us Pulsed Drain Current Tested
Diode Continuous Forward Current
Operating Junction Temperature
Storage Temperature Range
Typical
100
±20
2.8
3.5
14
3
150
-55 ~ 150
Unit
V
V
A
A
A
A
°C
°C
Note: 1: Surface Mounted on 1in2 pad area, t ≦ 10sec..
2: UIS tested and pluse width limited by maximum junction temperature 150°C (initial temperature TJ=25°C).
Electrical Characteristics (TA=25°C unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
Static Characteristics
BVDSS
Drain-Source Breakdown Voltage VGS=0V,ID=250uA
100
VDS=80V,VGS=0V
IDSS
Zero Gate Voltage Drain Current
TJ=85°C
VGS(th)
Gate Threshold Voltage
VDS=VGS,ID=250uA
1.5
IGSS
Gate Leakage Current
VGS=±16V, VDS=0V
VGS=10V, ID=3.5A
RDS(on)1 Drain-Source On-Resistance
VGS=4.5V, ID=2A
Diode Characteristics
VSD1
Diode Forward Voltage
ISD=3A,VGS=0V
0.6
trr
Reverse Recovery Time
ISD=15A,
dISD/dt=100A/us
Qrr
Reverse Recovery Charge
2
Dynamic Characteristics
Ciss
Input Capacitance
VGS=0V, VDS=30V
Coss
Output Capacitance
Frequency=1MHz
Crss
Reverse Transfer Capacitance
td(on)
Turn-On Delay Time
VDD=30V, RL=30Ω
tr
Turn-On Rise Time
ID=1A, VGEN=10V
td(off)
Turn-Off Delay Time
RG=6Ω
tf
Turn-Off Fall Time
Gate Charge Characteristics2
Qg
Total Gate Charge
VDS=50V, VGS=10V
Qgs
Gate-Source Charge
ID=15A
Qgd
Gate-Drain Charge
Note: 1: Pulse test ; pulse width ≦ 300ns, duty cycle ≦ 2%.
2: Guaranteed by design, not subject to production testing.
Rev. A.0 – Feb., 2012
2
Typ
Max. Unit
V
2
85
135
0.8
36
50
900
60
40
8
6
40
24
20
3
3.1
1
30
2.5
±10
105
175
1.1
uA
V
uA
mΩ
V
ns
nC
pF
15
11
75
45
ns
nC
100VDS/±20VGS/15A(ID) N-Channel Enhancement Mode MOSFET
Typical Characteristics
Rev. A.0 – Feb., 2012
3
HD1H15A
100VDS/±20VGS/15A(ID) N-Channel Enhancement Mode MOSFET
Typical Characteristics (Cont.)
Rev. A.0 – Feb., 2012
4
HD1H15A
100VDS/±20VGS/15A(ID) N-Channel Enhancement Mode MOSFET
Typical Characteristics (Cont.)
Rev. A.0 – Feb., 2012
5
HD1H15A
Package Dimension
TO
TO-252
2.3±0.1
6.6±0.2
1.2±0.3
9.7+0.5
-0.3
2.7±0.3
0.5±0.05
5.6±0.2
1±0.2
5.35±0.15
1.2±0.3
0.05+0.1
-0.05
0.8±0.2
0.6±0.2
2.3typ
2 3typ
2.3typ
0.5+0.1
-0.05
Package Dimension
TO
TO-252
Package Dimension
TO
TO-251
6.6±0.2
2.3±0.1
0.8±0.15
0.6±0.1
2.3typ
2 3typ
2.3typ
7.8±0
±0.4
±
0.3
7.5
0.75±0.15
7±0.2
0.5±0.05
5.6±0.2
5.35±0.15
0.5+0.1
-0.05
1.2±0.3
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