AAT1168B-Q5-T

Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B Product information presented is current as of publication date. Details are subject to change without notice. TRIPLE-CHANNEL TFT LCD POWER SOLUTION WITH OPERATIONAL AMPLIFIERS FEATURES Built in 3A, 0.2 Switching NMOS Positive LDO Driver Up to 28V/5mA Negative LDO Driver Down to −14V/5mA 1 VCOM and 4 VGAMMA Operational Amplifiers 28V High Voltage Switch for VGH Internal Soft-Start Function 1.2MHz Fixed Switching Frequency 3 Channels Fault and Thermal Protection Low Dissipation Current QFN-32 Package Available GENERAL DESCRIPTION The AAT1168/AAT1168A/AAT1168B is a triple-channel TFT LCD power solution that provides a step-up PWM controller, two LDO drivers (one for positive high voltage and one for negative voltage), five operational amplifiers, and one high voltage switch up to 28V for TFT LCD display. The PWM controller consists of an on-chip voltage reference, oscillator, error amplifier, current sense circuit, comparator, under-voltage lockout protection and internal soft-start circuit. The thermal and power fault protection prevents internal circuit being damaged by excessive power. The LDO drivers generate two regulated output voltage set by external resistor dividers. VGH voltage does not activate until DLY voltage exceeds 1.25V. The AAT1168/AAT1168A/AAT1168B contains 4+1 operational amplifiers. VO1, VO2, VO4, and VO5 are for PIN CONFIGURATION VOUT3 1 VREF 2 24 EO 23 IN1 gamma corrections and VO3 is for VCOM . In the short circuit condition, operational amplifiers are capable of sourcing ±100mA current for VGAMMA , and ±200mA current for VCOM . With the minimal external components, the AAT1168/A/B offers a simple and economical solution GND 3 GND1 VO1 VI1VI1+ VO2 4 5 6 7 8 AAT1168/ AAT1168A/ AAT1168B 22 VDD 21 SW 20 VO5 19 VI518 for TFT LCD power. VI5+ 17 VO4 – – Advanced Analog Technology, Inc. – Version 1.00 Page 1 of 22 司公限有份股技科比類灣台 – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B ORDERING INFORMATION DEVICE TYPE AAT1168 PART NUMBER AAT1168 -Q5-T PACKAGE Q5:VQFN325*5 PACKING T: Tape and Reel TEMP. RANGE 40 ° C to + 85 ° C MARKING AAT1168 XXXXX XXXX AAT1168A XXXXX XXXX AAT1168B XXXXX XXXX MARKING DESCRIPTION Device Type Lot no.(6~9digits) Date Code (4digits) Device Type Lot no.(6~9digits) Date Code (4Digits) Device Type Lot no.(6~9digits) Date Code (4Digits) AAT1168A AAT1168A -Q5-T Q5:VQFN325*5 T: Tape and Reel 40 ° C to + 85 ° C AAT1168B AAT1168B -Q5-T Q5:VQFN325*5 T: Tape and Reel 40 ° C to + 85 ° C NOTE: The product is lead free and halogen free. TYPICAL APPLICATION – Advanced Analog Technology, Inc. – Version 1.00 Page 2 of 22 司公限有份股技科比類灣台 – – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B ABSOLUTE MAXIMUM RATINGS PARAMETER VDD to GND VDD1, SW to GND (for AAT1168/AAT1168B) VDD1, SW to GND (for AAT1168A) VOUT3, OUT3, VGH to GND (for AAT1168/AAT1168B) VOUT3, OUT3, VGH to GND (for AAT1168A) OUT2 to GND Input Voltage 1 (IN1, IN2, IN3, DLY, CTL) Input Voltage 2 (VI1+, VI1 − , VI2+, VI2 − , VI3+, VI3 − , VI4+, VI4 − , VI5+, VI5 − ) Output Voltage 1 (EO, VREF ) Output Voltage 2 (ADJ, VO1, VO2, VO3, VO4, VO5) Operating Free-Air Temperature Range Storage Temperature Range Maximum Junction Temperature Package Thermal Resistance Package Thermal Resistance Power Dissipation SYMBOL VALUE 7 14.5 25 28 40 UNIT V V V V V V V V V V VDD VH1 VH1 VH2 VH2 VH3 VI1 VI2 VO1 VO2 TC −14 VDD +0.3 VH1 +0.3 VDD +0.3 VH1 +0.3 –40 C to +85 C –45 C to +125 C +125 34 1.1 1,618 C C C C /W C /W mW TSTORAGE TJ JA JC Pd NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the devices. Exposure to ABSOLUTE MAXIMUM RATINGS conditions for extended periods may affect device reliability. – Advanced Analog Technology, Inc. – Version 1.00 Page 3 of 22 司公限有份股技科比類灣台 – – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B ELECTRICAL CHARACTERISTICS ( VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient temperature, VDD = 5V, VDD1 = 10V.) PARAMETER VDD Input Voltage Range VDD1 Input Voltage Range SYMBOL TEST CONDITION MIN 2.6 AAT1168/AAT1168B 8 8 2.1 2.3 2.2 2.4 0.56 5.60 7 160 TYP MAX 5.5 14 23 2.3 2.5 0.80 10.0 10 UNIT V V V V V mA mA mA VDD VDD1 AAT1168A Falling Rising VDD Under Voltage Lockout VUVLO VDD Operating Current VDD1 Operating Current Thermal Shutdown IVDD IVDD1 TSHDN VIN1 = 1.5V, Not Switching VIN1 = 1.0V, Switching VVI1+ ~ VVI5+ = 4V C Reference Voltage PARAMETER Reference Voltage Line Regulation Load Regulation SYMBOL TEST CONDITION IVREF = 100µA IVREF = 100µA, VDD = 2.6V~5.5V IVREF = 0~100 µ A MIN 1.231 TYP 1.250 2 1 MAX 1.269 5 5 UNIT V mV mV VREF VRI VRO Oscillator PARAMETER Oscillation Frequency Maximum Duty Cycle SYMBOL TEST CONDITION MIN 1.05 84 TYP 1.20 87 MAX 1.35 90 UNIT MHz % fOSC DMAX – Advanced Analog Technology, Inc. – Version 1.00 Page 4 of 22 司公限有份股技科比類灣台 – – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B ELECTRICAL CHARACTERISTICS ( VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient temperature, VDD = 5V, VDD1 = 10V.) Soft Start & Fault Detect PARAMETER Channel 1 Soft Start Time Channel 2 Soft Start Time Channel 3 Soft Start Time Channel 1 to Channel 2 Delay Channel 2 to Channel 3 Delay SYMBOL TEST CONDITION MIN TYP 14 14 14 AAT1168A Only AAT1168A Only AAT1168/AAT1168B During Fault Protect Trigger Time 7 7 55 165 1.00 1.13 0.40 1.00 1.05 1.17 0.45 1.05 1.10 1.20 0.50 1.10 MAX UNIT ms ms ms ms ms ms ms V V V V t SS1 t SS2 t SS3 t D12 t D23 t FP AAT1168A AAT1168/AAT1168B IN1 Fault Protection Voltage IN2 Fault Protection Voltage IN3 Fault Protection Voltage VF1 VF2 VF3 AAT1168A Error Amplifier (Channel 1) PARAMETER Feedback Voltage Input Bias Current Feedback-Voltage Line Regulation Transconductance Voltage Gain SYMBOL TEST CONDITION MIN 1.221 TYP 1.233 0 0.05 105 1,500 MAX 1.245 40 0.15 UNIT V nA %/V VIN1 IB1 VRI1 Gm AV VIN1 = 1V to 1.5V Level to Produce VEO = 1.233V 2.6V < VDD < 5.5V ∆I = 5 µ A –40 µS V/V – Advanced Analog Technology, Inc. – Version 1.00 Page 5 of 22 司公限有份股技科比類灣台 – – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B ELECTRICAL CHARACTERISTICS ( VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient temperature, VDD = 5V, VDD1 = 10V.) N-MOS Switch (Channel 1) PARAMETER Current Limit On-Resistance Leakage Current SYMBOL TEST CONDITION MIN TYP 3.0 MAX UNIT A ILIM R ON ISWOFF ISW = 1.0A VSW = 12V 0.2 0.01 20.00 µA Negative Charge Pump (Channel 2) PARAMETER IN2 Threshold Voltage IN2 Input Bias Current OUT2 Leakage Current OUT2 Source Current SYMBOL TEST CONDITIONS MIN 235 –40 TYP 250 0 MAX 265 40 UNIT mV nA VIN2 IB2 IOFF2 IOUT2 IOUT2 = –100 µ A VIN2 = –0.25V to 0.25V VIN2 = 0V, OUT2 = –12V VIN2 = 0.35V, OUT2 = –10V −20 1 4 −50 µA mA Positive Charge Pump (Channel 3) PARAMETER IN3 Threshold Voltage IN3 Input Bias Current OUT3 Leakage Current OUT3 Sink Current SYMBOL TEST CONDITIONS MIN 1.22 –40 TYP 1.25 0 40 1 4 MAX 1.28 40 80 UNIT V nA VIN3 IB3 IOFF3 IOUT3 IOUT3 = 100 µ A VIN3 = 1V to1.5V VIN3 = 1.4V, OUT3 = 28V VIN3 = 1.1V, OUT3 = 25V µA mA – Advanced Analog Technology, Inc. – Version 1.00 Page 6 of 22 司公限有份股技科比類灣台 – – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B ELECTRICAL CHARACTERISTICS ( VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient temperature, VDD = 5V, VDD1 = 10V.) High Voltage Switch Controller PARAMETER DLY Source Current DLY Threshold Voltage DLY Discharge RON CTL Input Low Voltage CTL Input High Voltage CTL Input Bias Current Propagation Delay CTL to VGH VOUT3 to VGH Switch R-on ADJ to VGH Switch R-on SYMBOL TEST CONDITIONS MIN –4 1.22 TYP –5 1.25 8 0.5 2 V V 0 100 15 30 30 60 40 nA ns MAX –6 1.28 UNIT IDLY VDLY RDLY VIL VIH IB4 t PP R ONSC R ONDC VCTL = 0 to VDD OUT3 = 25V µA V –40 VDLY = 1.5V, VCTL = VDD VDLY = 1.5V, VCTL = GND – Advanced Analog Technology, Inc. – Version 1.00 Page 7 of 22 司公限有份股技科比類灣台 – – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B ELECTRICAL CHARACTERISTICS ( VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient temperature, VDD = 5V, VDD1 = 10V.) VCOM and VGAMMA Buffer PARAMETER Input Offset Voltage Input Bias Current SYMBOL TEST CONDITIONS MIN –40 TYP 2 0 MAX 12 40 UNIT mV nA VOS IB5 VVI1+ ~ VVI5+ = 4V VVI1+ ~ VVI5+ = 4V IVO1 , IVO2 , IVO4 , IVO5 = 10mA, VVI1 , VVI2 , VVI4 , VVI5 = 4V IVO3 = 50mA, VVI3 = 4V VOL - 4.02 4.05 - 4.03 4.06 V Output Swing (for AAT1168) VOH IVO1 , IVO2 , IVO4 , IVO5 = –10mA VVI1 , VVI2 , VVI4 , VVI5 = 4V IVO3 = −50mA , VVI3 = 4V 3.95 3.98 - 3.94 - 3.97 mA mA Short Circuit Current ISHORT IVO1 , IVO2 , IVO4 , IVO5 IVO3 VVI1+ , VVI3+ = 2V to 8V, ±100 ±200 Slew Rate SR VVI3+ ~ VVI5+ = 8V to 2V, 20% to 80% VVI1+ ~ VVI5+ = 3.5V to 4.5V, 90% - 12 - V/ µ s Settling Time tS - 5 - µs – Advanced Analog Technology, Inc. – Version 1.00 Page 8 of 22 司公限有份股技科比類灣台 – – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B PIN DESCRIPTION PIN NO. QFN-32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 NAME VOUT3 VREF GND GND1 VO1 VI1– VI1+ VO2 VI2– VI2+ GND2 VI3+ VO3 VDD1 VI4+ VI4– VO4 VI5+ VI5– VO5 SW VDD IN1 EO IN3 OUT3 IN2 I/O O O I I O I I I I I I O I I O I O I O I DESCRIPTION Channel 3 Output Voltage (gate high voltage input) Internal Reference Voltage Output Ground SW MOS Ground Operational Amplifier 1 Output Operational Amplifier 1 Negative Input Operational Amplifier 1 Positive Input Operational Amplifier 2 Output Operational Amplifier 2 Negative Input Operational Amplifier 2 Positive Input Ground for Operational Amplifiers VCOM Operational Amplifier Positive Input VCOM Operational Amplifier Output High Voltage Power Supply Input Operational Amplifier 4 Positive Input Operational Amplifier 4 Negative Input Operational Amplifier 4 Output Operational Amplifier 5 Positive Input Operational Amplifier 5 Negative Input Operational Amplifier 5 Output Main PWM Switching Pin Power Supply Input Main PWM Feedback Pin Main PWM Error Amplifier Output Positive Charge Pump Feedback Pin Positive Charge Pump Output Negative Charge Pump Feedback Pin – Advanced Analog Technology, Inc. – Version 1.00 Page 9 of 22 司公限有份股技科比類灣台 – – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B PIN NO. QFN-32 28 29 30 31 32 NAME OUT2 DLY CTL ADJ VGH I/O O I I O O Negative Charge Pump Output High Voltage Switch Delay Control High Voltage Switch Control Pin Gate High Voltage Fall Time Setting Pin Switching Gate High Voltage for TFT DESCRIPTION FUNCTION BLOCK DIAGRAM AAT1168 2 VREF 1.233V Reference Voltage 1.25V 0.25V Error Amplifier 22 VDD Fail Fail / Thermal Control 23 IN1 SW 21 Digital Control Block GND1 4 1. 233V EO 24 Comparator Current Sense and Limit GND 3 GND2 11 OUT2 28 OUT3 26 Oscillator 27 IN2 0. 25V 25 IN3 1. 25V 6 VI17 VI1+ VO1 5 VO2 8 VO3 VO4 13 9 VI210 VI2+ 12 VI3+ 16 VI415 VI4+ 19 VI518 17 VI5+ VO5 20 VDD1 High Voltage Control 14 29 DLY 30 CTL Ω 2.5kΩ 31 ADJ 32 VOUT3 VGH 1 – Advanced Analog Technology, Inc. – Version 1.00 Page 10 of 22 司公限有份股技科比類灣台 – – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B TYPICAL APPLICATION CIRCUIT Vin 3.3V To 5V C1 10 F R1 10 C2 0.1 F 22 L 6.8 H VADD R10 7 VI1+ R11 VDD SW 21 D DFLS220L AAT1168/A/B 10 VI2+ C3 47 F GND1 4 12 VI3+ IN1 23 R3 10k VDD1 14 C4 0.1 F GND2 11 R2 97.6k VOUT1 13.3V/300mA R12 R13 15 VI4+ R14 18 VI5+ R15 SW C5 1F C6 1F R4 6.8k C13 1F 6 VI1R16 10 5 VO1 9 VI2R17 10 OUT3 26 8 VO2 16 VI4R18 10 17 VO4 19 VI5R19 10 R20 10 13 VO3 IN3 25 20 VO5 U1 BAT54S VGAMMA C14 1F Q1 MMBT4403 C7 1F C15 1F SW R5 200k C8 1F U2 BAT54S C16 1F R6 10k VOUT3 25V/30mA VCOM C17 10 F VOUT3 1 C9 0.1 F C10 0.1 F SW U3 BAT54S 30 CTL 29 DLY R7 6.8k OUT2 28 31 ADJ IN2 27 R9 10k VREF 2 24 EO GND 3 C12 0.1 F R8 62k CTL C18 R21 Q2 MMBT4401 VGH 32 VGH R22 57.6k C19 1.8nF C11 1F VOUT2 -6V/30mA Figure 1. Typical Application Circuit – Advanced Analog Technology, Inc. – Version 1.00 Page 11 of 22 司公限有份股技科比類灣台 – – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B TYPICAL OPERATING CHARACTERISTICS ( VIN = 5V, VOUT1 = 12V, VOUT2 = −7V, VOUT3 = 27V, TC = +25 C , unless otherwise noted.) – – Advanced Analog Technology, Inc. – Version 1.00 Page 12 of 22 司公限有份股技科比類灣台 – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B TYPICAL OPERATING CHARACTERISTICS ( VIN = 5V, VOUT1 = 12V, VOUT2 = −7V, VOUT3 = 27V, TC = +25 C , unless otherwise noted.) – – Advanced Analog Technology, Inc. – Version 1.00 Page 13 of 22 司公限有份股技科比類灣台 – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B DESIGN PROCEDURE Boost Converter Design Setting the Output Voltage and Selecting the Lead Compensation Capacitor The output voltage of boost converter is set by the resistor divider from the output (VOUT1) to GND with the center tap connected to the IN1. Where VIN1 , the boost converter feedback regulation voltage is 1.233V. Choose R2 (Figure 2) between 5.1k to 51k and calculate R1 to satisfy the following equation. κ= ILpeak IIN η : Boost converter efficiency κ : The ratio of the inductor peak to peak ripple current to the input DC current VIN : Input voltage VO : Output voltage IO : Output load current fS : Switching frequency D : Duty cycle ILPEAK : Inductor peak to peak ripple current IIN : Input DC current V  R1 = R2  OUT1 − 1  VIN1  VOUT1 The AAT1168 SW current limit ( ILIM ) and inductor’ saturation current rating ( ILSAT ) should exceed IL(peak ) , and the inductor's DC current rating should exceed IIN . For the best efficiency, choose an inductor with less DC series resistance ( rL ). EO 24 RC CP CC gm VREF IN1 23 R1 VIN1 R2 ILIM and ILSAT > IL ( peak ) AAT1168/A/B ILDC > IIN IL (peak ) = IIN + VIND , 2Lfs Figure 2. Feedback Circuit IIN = IO , η(1 − D) 2 Inductor Selection The minimum inductance value is selected to make sure that the system operates in continuous conduction mode (CCM) for high efficiency and to prevent EMI. The equation of inductor used a parameter κ , which is the ratio of the inductor peak to peak ripple current to the input DC current. The best trade-off between voltage 0.5. L≥ ηVO D(1 − D)2 , κIOfs VIN , VO – –  IO  PDCR ≈   rL  η(1 − D)  ILDC : DC current rating of inductor PDCR : Power loss of inductor series resistance C6-K1.8L 3.9 µ H 6.8 µ H 10 µ H Table 1.Inductor Data List rL DC CURRENT RATING 41 m 68 m 81 m 2.5A 2.2A 1.8A ripple of transient output current and permanent output current has a κ between 0.4 and MITSUMI Product-Max Height: 1.9mm Example 1: In the typical application circuit (Figure 1) the output load current is 300mA with 13.3V output D = 1− Advanced Analog Technology, Inc. – Version 1.00 Page 14 of 22 司公限有份股技科比類灣台 – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B voltage and input voltage of 5V. Choose a κ of 0.465 and efficiency of 90%. 0.9 * 13.3 L≥ 0.624(0.376 )2 ≈ 6.8 µ H 0.465 * 0.3 * 1.16 IO IIN = = 0.89A η(1 − D) Input Capacitor Selection The input capacitors have two important functions in PWM controller. First, an input capacitor provides the power for soft start procedure and supply the current for the gate-driving circuit. A 10 µ F ceramic capacitor is used in typical circuit. Second, an input bypass capacitor reduces the current peaks, the input voltage drop, and noise injection into the IC. A low ESR ceramics capacitor 0.1 µ F is used in typical circuit. To ensure the low noise supply at VDD , VDD is decoupled from input capacitor using an RC low pass filter. VD IL (peak ) = IIN + IN = 1.095A 2Lf s PDCR = 0.043W or 1% power loss Schottky Diode Selection Schottky has to be able to dissipate power. The dissipated power is the forward voltage and input DC current. To achieve the best efficiency, choose a Schottky diode with less recovery capacitor (CT) for fast recovery time and low forward voltage (VF). For boost converter, the reverse voltage rating (VR) should be higher than the maximum output voltage, and current rating should exceed the input DC current. PDIODE = PDSW + PDCOM PDSW = (1 − D)VFQR fs QR = VR CT PDCOM = VFIO /(1 − D) PDIODE : Total power loss of diode for boost converter PDSW : Switching loss of diode for boost converter PDCOM : Conduction loss of diode for boost converter Figure 3. Input Bypass Capacitor Affects the VDD Drop Output Capacitor The output capacitor maintains the DC output voltage. A Low ESR ( rC ) ceramic capacitor can reduce the output ripple and power loss. There are two parameters which can affect the output voltage ripple: 1. the voltage drops when the inductor current flows Table 2. Schottky ata ist SMA B220A B240A 0.24V 0.24V DIODES Product, Max-Height: 2.3mm For example, PDIODE = PDSW + PDCOM = 0.203W or 5.1% power loss. – – Advanced Analog Technology, Inc. – Version 1.00 Page 15 of 22 司公限有份股技科比類灣台 L L L L D D D D VF VR CT through the ESR of output capacitor; 2. charging and discharging of the output capacitor also affect the output voltage ripple. 14V 28V 150pF 150pF VRIPPLE = VRIPPLE (COUT ) + VRIPPLE (ESR ) VRIPPLE (COUT ) ≈ IOD fS COUT VRIPPLE (ESR) ≈ IL(peak) rC – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B PESR = ILpeak ( ) 2 .rC + ESR: Equivalent Series Resistance Example 2: COUT = 38µF, rC = 20m + − − VRIPPLE (COUT ) = 4mV VRIPPLE (ESR) = 22mV VRIPPLE = 26mV PESR = 0.023W or 0.6% power loss − + β Boost Converter Power loss The largest portions of power loss in the boost converter are the internal power MOSFET, the inductor, the Schottky diode, and the output capacitor. If the boost converter has 90% efficiency, there is approximately 3.3% power loss in the internal MOSFET, 1% power loss in the inductor, 5.1% power loss in the Schottky diode, and 0.6% power loss in the output capacitor. Figure 5. Block Diagram of Boost Converter with Peak Current Mode (PCM) Power Stage Transfer Functions The duty to output voltage transfer function Tp is: V (s + w esr )(s − w z2 ) Tp (s) = O = Tp0 d s2 + 2ξw ns + wn2 W here Tp0 = VO And −rC 1 , w esr = 1 − D ) (RL + rC ) CrC ( Loop Compensation Design The voltage-loop gain with current loop closed sets the stability of steady state response and dynamic performance of transient response. The loop compensation design is as follows: w z2 = ξ= RL (1 − D)2 − r , wn = L 2 (1 − D)2 RL + r LC (RL + rC ) , C[r (RL + rC ) + RLrc (1 − D ) ] + L 2 LC (RL + rC ) [r + (1 − D ) RL ] 2 β r = rL + DrDS + (1 − D)RF rL is the inductor equivalent series resistance, rC is capacitor ESR, RL is the converter load resistance, C is output filter capacitor, rDS is the transistor turn on resistance, and RF is the diode forward resistance. The duty to inductor current transfer function Tpi is: Tpi (s) = il s + w zi = Tpi0 2 d s + 2ξw n s + w n 2 VO (RL + 2rC ) 1 , w zi = C (RL / 2 + rC ) L (RL + rC ) Figure 4. Closed-current Loop for Boost with PCM W here Tpi0 = – – Advanced Analog Technology, Inc. – Version 1.00 Page 16 of 22 司公限有份股技科比類灣台 – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B Current Sampling Transfer Function Error voltage to duty transfer function Fm is: Fm (s) = 2fs2 s2 + 2ξw ns + w n2 d = v ei Tpi0RCSs ( s + w zi ) ( s + w sh ) V W here β = FB VO The compensator transfer function TC (s) = VC s + wc = gmRC v fb s ( ) W here w sh = M − Ma 3w s  1 − α   ,α = 2 π  1+ α  M1 + Ma W here wc = 1 RCCC w s = 2πfs Therefore, Fm depends on duty to inductor current transfer function Tpi , and fs is the clock switching frequency; RCS is the current-sense amplifier transresistance. For the boost converter, M1 = VIN / L and M2 = ( VO − VIN )/ L . For AAT1168, RCS = 0.24 V/A, Ma is slope 6. compensation, Ma = 0.8×10 The closed-current loop transfer function Ticl is: Figure 6. Voltage Loop Compensator Compensator design guide: Ticl (s) = s 12fs x RCS Tpi0 ( s + w ) s2 + w s +12f 2 zi sh s 2 ( 2 + 2ξw n s + w n2 ) ( ) 1. Crossover frequency fci < 2. Gain margin>10dB 1 fs 2 The control to output voltage transfer function Td is: VO (s) Td (s) = = Ticl (s)Tp (s) VC (s) The voltage-loop gain with current loop closed is: 4. The L vi (s) = 1 at crossover frequency, Therefore, the compensator resistance, RC is determined by: RC = VO 2πfciCRCS (RL + 2rC ) VFB gmk  r (1 − D ) RL −  (1 − D )     L vi (s) = βTC (s)Td (s) = β gm R C 2 s + w c 12fs Tp0 × s R CS Tpi0 (s + w z1 )(s − w z2 ) (s + w zi )(s 2 + sw sh + 12fs 2 ) – – Advanced Analog Technology, Inc. – – Version 1.00 Page 17 of 22 ∘ The Voltage-Loop Gain with Current Loop Closed 3. Phase margin>45 司公限有份股技科比類灣台 Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B Table 3 K factor Table Best Corner K factor Frequency 23.740 kHz 21.842 kHz 20.095 kHz 15.649 kHz 13.247 kHz 4.692 5.083 6.042 5.230 4.703 C 21.533µF 25.079µF 32.587µF 36.312µF 38.469µF Positive and Negative LDO driver Output Voltage Selection The output voltage of positive LDO driver is set by a resistive divider from the output (Vout3) to GND with the center tap connected to the IN3, where VIN3, the positive LDO driver feedback regulation voltage, is 1.25V. Choose R6 (Figure 8) between 10k 51k . And calculate R5 with the following equation. and 5. The output filter capacitor is chosen so C RL pole cancels RC CC zero R  εRCCC = C  L + rC  , and 2  C  RL  CC = + rC   εRC  2   Vout 3  R5 = R6  − 1 V  IN3   The output voltage of negative LDO driver is set by a resistive divider from the output (VGL) to VREF with the center tap connected to the IN2, where VIN2, the negative LDO driver feedback regulation voltage, is 0.25V. Choose R9 (Figure 9) between 10k and ε = (1 ~ 3) Example 3: 51k and calculate R8 with the following equation. VIN = 5V, VO = 13.3V, IO = 300mA, fs = 1,190kHz, VFB = 1.233V, L = 6.65µH, Gm = 85µS, rL = 76.689 m rC = 9.13m RF = 0.7667 , CC = 1.95nF, RC = 7.6k , C = 38.5µF, ε = 3, RCS = 0.23V/A. 60  V − VGL   R 8 = R 9  IN2 V   REF − VIN2  40 Magnitude (dB) 20 0 -20 -40 -90 -135 Phase (deg) -180 -225 -270 10 2 Figure 7. Bode Plot of Loop Gain Using Matlab Simulation – – Advanced Analog Technology, Inc. – Version 1.00 Page 18 of 22 司公限有份股技科比類灣台 , Bode Diagram Figure 8. The Positive LDO Driver 10 3 10 Frequency (Hz) 4 10 5 10 6 ® – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B C9 0.1 F SW U3 BAT 54 S C10 0.1 F Table 4 Pass Transistor Specifications MMBT4401 MMBT4403 0.5V 90 VBE(max) R7 6.8k Ω OUT2 28 R8 62kΩ IN 2 27 R9 10k Ω VREF 2 C12 0.1 F C11 1F Q2 MMBT4401 0.65V 130 hfe(min) DIODES Product, Case: SOT23 VOUT2 -6V/30mA Example 5: Output current of VOUT3 and VOUT2 are 30mA, the minimum base-emitter resistor can be calculated as Figure 9. The Negative LDO Driver Example 4: For system design VOUT3 = 25V, R 5 = 200k , R 6 = 10k VOUT2 = −6V, R 8 = 62k , R 9 = 10k , The minimum value can be used, however, the larger value has the advantage of reducing quiescent current. So we choose 6.8k to be R4. R 4 (min) ≥ 0.5 /(( 1mA − 30mA ) / 90) ≥ 750 R 7(min) ≥ 0.65 /(( 1mA − 30mA ) / 130) ≥ 845 Flying Capacitors Increasing the flying capacitor ( C5 , C7 , C9 ) values can lower output voltage ripples. The 1µF ceramic capacitors works well in positive LDO driver. A 0.1µF ceramic capacitor works well in negative LDO driver. Charge Pump Output Capacitor Using low ESR ceramic capacitor to reduce the output voltage ripple is recommended. With ceramic capacitor, output voltage ripple is dominated by the capacitance value. The minimum capacitance value can be calculated by the following equation: LDO Driver Diode To achieve high efficiency, a Schottky diode should be used. BAT54S (Figure 8 and 9) has fast recovery time and low forward voltage for best efficiency. Cout ≥ Iload 2Vripple fs LDO Driver Base-Emitter Resistors For AAT1168, the minimum drive current for positive and negative LDO driver are 1mA, thus the minimum base-emitter resistance can be calculated by the following equation: Example 6: The output voltage ripple of VOUT3 and VGL is under 1%, the minimum capacitance value can be calculated as R 4 (min) ≥ VBE(max) /((IOUT3 (min) − IC ) / hfe( min ) ) ) R 7(min) ≥ VBE(max) /((IOUT 2(min) − IC ) / hfe( min ) 30mA ≈ 0.1µF η2 × 250mV × 1.19MHz 30mA Cout( VGL ) ≥ ≈ 0.33µF η2 × 60mV × 1.19MHz Cout(VOUT3 ) ≥ η : Efficiency, about 60% at charge pump circuit – – Advanced Analog Technology, Inc. – Version 1.00 Page 19 of 22 司公限有份股技科比類灣台 – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B Operational Amplifier The AAT1168 have five amplifiers independent. The operational amplifiers are usually used to drive VCOM and the gamma correction divider string for TFT-LCD. The output resistors and capacitors of amplifiers are as low pass filter and compensator for unity GAIN stable. Table 5. Recommended Components DESCRIPTION DESIGNATION 6.8 µH, 1.8A, L MITSUMI C6-K1.8L 6R8 200mA 30V Schottky barrier U1, U2, U3 diode (SOT-23), DIODES BAT54S 2A 20V rectifier diode D DIODES DFLS220L 10 µF, 25V X5R ceramic C3 capacitor C5, C6, C7 1 µF, 25V X5R ceramic capacitor 0.1 µF, 50V X5R ceramic C2, C4, C9, C10, C12 capacitor Soft Start Waveform – – Advanced Analog Technology, Inc. – 司公限有份股技科比類灣台 Version 1.00 Page 20 of 22 – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B LAYOUT CONSIDERATION Layout Guide The system’s performances including switching noise, transient response, and PWM feedback loop stability are greatly affected by the PC board layout and grounding. There are some general guidelines for layout: plane on the PCB. This will reduce noise and ground loop errors as well as absorb more of the EMI radiated by the inductor. For boards with more than two layers, a ground plane can be used to separate the power plane and the signal plane for improved performance. PC Board Layout Inductor Always try to use a low EMI inductor with a ferrite core. Filter Capacitors Place low ESR ceramics filter capacitors (between 0.1µF and 0.22µF) close to VDD and VREF pins. This will eliminate as much trace inductance effects as possible and give the internal IC rail a cleaner voltage supply. The ground connection of the VDD and VREF bypass capacitor should be connected to the analog ground pin (GND) with a wide trace. Output Capacitors Place output capacitors as close as possible to the IC. Minimize the length and maximize the width of traces to get the best transient response and reduce the ripple noise. We choose 10µF ceramics capacitor to reduce the ripple voltage, and use 0.1µF ceramics capacitor to reduce the ripple noise. Feedback If external compensation components are needed for stability, they should also be placed close to the IC. Take care to avoid the feedback voltage-divider resistors’ trace near the SW. Minimize feedback track lengths to avoid the digital signal noise of TFT control board. Ground Plane The grounds of the IC, input capacitors, and output capacitors should be connected close to a ground plane. It would be a good design rule to have a ground – – Advanced Analog Technology, Inc. – 司公限有份股技科比類灣台 Version 1.00 Page 21 of 22 – Advanced Analog Technology, Inc. May 2008 AAT1168/1168A/1168B PACKAGE DIMENSION VQFN32 PIN PIN 1 INDENT C b E E2 e A1 D A D2 L SYMBOL A A1 b C D D2 E E2 e L y DIMENSIONS IN MILLIMETERS MIN TYP MAX 0.8 0.9 1.0 0.00 0.02 0.05 0.18 0.25 0.30 -----0.2 -----4.9 5.0 5.1 3.05 3.10 3.15 4.9 5.0 5.1 3.05 3.10 3.15 -----0.5 -----0.35 0.40 0.45 0.000 -----0.075 – – Advanced Analog Technology, Inc. – 司公限有份股技科比類灣台 Version 1.00 Page 22 of 22 –