ABPX1130-XXXSC-T

P reliminary A BPX1130 A dvanced Programmable Clock F EATURES • • • • • P IN CONFIGURATION • • • • • A dvanced programmable PLL design Very low Jitter and Phase Noise (< 40ps Pk-Pk typical) O utput frequency up to 375MHz CMOS. S upports differential CMOS output to produce PECL, LVDS XIN/FIN inputs. GND C rystal inputs: CLK0 o F undamental crystal: 10MHz-30MHz CLK1 o 3 RD o vertone crystal: Up to 75MHz o R eference input: Up to 200MHz A ccepts