ABX8039QC

( Preliminary) A BX8037/38/39 3 8-640MHz Low Phase Noise XO F EATURES • • • L ess than 0.4ps RMS (12kHz-20MHz) phase jitter for a ll frequencies . L ess than 25ps peak to peak jitter for all frequencies. L ow phase noise output (@ 1MHz frequency offset ∗ - 144dBc/Hz for 106.25MHz ∗ - 144dBc/Hz for 156.25MHz ∗ - 144dBc/Hz for 212.5MHz ∗ - 140dBc/Hz for 312.5MHz, ∗ - 131dBC/Hz for 622.08MHz 1 9MHz-40MHz crystal input. 3 8MHz-640MHz output. A vailable in PECL, LVDS, or CMOS outputs. O utput Enable selector. 2 .5V & 3.3V operation. A vailable in 3x3 QFN or 16-pin TSSOP packages. PACKAGE PIN ASSIGNMENT VDDANA XIN XOUT SEL2^ OE_CTRL DNC GNDANA LP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GNDBUF QBAR VDDBUF Q GNDBUF LM ABX803X VDDANA SEL0^ 10 D ESCRIPTION T he ABX803X is a monolithic low jitter and low phase noise high performance clock, capable of maintaining 0.4ps RMS phase jitter and CMOS, LVDS or PECL outputs, covering a wide frequency output range up to 640MHz. It allows high performance and high frequency output, using a low cost fundamental crystal of between 19-40MHz. The frequency selector pads of ABX803X enable output frequencies of (2, 4, 8, or 16) * F XIN . The ABX803X is designed to address the demanding requirements of high performance applications such Fiber Channel, serial ATA, Ethernet, SAN, etc. XOUT SEL2^ OE_CTRL DNC 12 13 14 15 16 1 11 SEL1^ 9 XIN • • • • • • 16-pin TSSOP 3x3 QFN 8 7 GNDBUF QBAR VDDBUF Q ABX803X 2 3 4 6 5 GNDANA Note1: QBAR is used for single ended CMOS output. Note2: ^ Denotes internal pull up resistor. B LOCK DIAGRAM VCO Divider Charge Pump + Loop Filter Output Divider (1,2,4,8) GNDBUF LP LM XIN XOUT XTAL OSC Phase Detector VCO (F XiN x16) QBAR Q Performance Tuner OE 3 0332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 w ww.Abracon.com 9 /1/05 Page 1 ( Preliminary) A BX8037/38/39 3 8-640MHz Low Phase Noise XO O UTPUT ENABLE LOGICAL LEVELS P art # A BX8038 (PECL) A BX8037 & 39 (CMOS or LVDS) OE 0 ( Default) 1 0 1 (Default) S tate Output enabled Tri-state T ri-state Output enabled P IN DESCRIPTIONS N ame V DDANA X IN X OUT S EL2 O E_CTRL D NC G NDANA LP LM G NDBUF Q V DDBUF Q BAR G NDBUF S EL1 S EL0 TSSOP Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3x3mm QFN Pin number 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 Type P I O I I P P O P O P I I VDD for analog Circuitry. Description Crystal input pin. (See Crystal Specifications on page 3). Crystal output pin. (See Crystal Specifications on page 3). Output frequency Selector pin. Output enable control pin. (See OE_CTRL Logic Levels on page 1). Do Not Connect Ground for analog circuitry. Tuning inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between LP and adjacent LM pin. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. GND connection for output buffer circuitry. PECL or LVDS output. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. Complementary PECL, LVDS output; Or single ended CMOS output. GND connection for output buffer circuitry. Output frequency Selector pin. Output frequency Selector pin. 3 0332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 w ww.Abracon.com 9 /1/05 Page 2 ( Preliminary) A BX8037/38/39 3 8-640MHz Low Phase Noise XO F REQUENCY SELECTION TABLE S EL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 S EL0 0 1 0 1 0 1 0 1 S elected Multiplier/Output Frequency V CO Max* V CO Min* R eserved R eserved F in x 2 F in x 8 F in x 16 F in x 4 A ll SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0. * Special Test Modes to help selecting the inductor value for the target output frequency. P ERFORMANCE TUNING & INDUCTOR VALUE SELECTION P lease refer to Abracon’s “Tuning Assistant” software to automatically calculate the optimum inductor values. In addition, the chart below could be used as a reference for quick inductor value selection. Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max” represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock in the middle of its tuning range with maximum margin on either side. 3 0332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 w ww.Abracon.com 9 /1/05 Page 3 ( Preliminary) A BX8037/38/39 3 8-640MHz Low Phase Noise XO E LECTRICAL SPECIFICATIONS 1 . Absolute Maximum Ratings P ARAMETERS S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. - 0.5 - 0.5 - 65 - 40 MAX. 4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2 UNITS V V V °C °C °C °C kV E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * N ote : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2 . Crystal Specifications P ARAMETERS C rystal Resonator Frequency C rystal Loading Rating C rystal Shunt Capacitance R ecommended ESR SYMBOL F XIN C L (xtal) C 0 (xtal) RE CONDITIONS P arallel Fundamental Mode MIN. 19 TYP. 1 7.7 MAX. 40 5 30 UNITS MHz pF pF Ω A T cut N ote : Crystal Loading rating: 17.7pF is the loading the crystal sees from the XO chip. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires less load to be at nominal frequency, then a capacitor can placed in series with the crystal. If the crystal requires more load to be at nominal frequency, capacitors can be placed from XIN and XOUT to ground. This however may reduce the oscillator gain. 3 . General Electrical Specifications P ARAMETERS S upply Current, Dynamic (with Loaded Outputs) O perating Voltage O utput Clock Duty Cycle S hort Circuit Current N ote: C MOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load. SYMBOL I DD V DD CONDITIONS P ECL/LVDS/CMOS P ECL/LVDS 38MHz