ACE24C32_1

                                                                                 ACE24C32/64                                               Technology Description Two-wire Serial EEPROM The ACE24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. Features Low Operation Voltage: Vcc = 1.7V to 5.5V Internally Organized: 4096 x 8,8192 x 8 Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 1MHz (2.5V~5.5V) and 400 kHz (1.7V) Compatibility Write Protect Pin for Hardware Data Protection 32-byte Page Write Modes (Partial Page Writes are Allowed) Self-timed Write Cycle (5 ms max) High-reliability - Endurance: 1,000,000 Write Cycles - Data Retention: 100 Years TDFN ROHS compliant Packages Wafer Sales: available in inked wafer Form Absolute Maximum Ratings Operating Temperature -55℃ to +125℃ Storage Temperature -65℃ to +150℃ Voltage on Any Pin with Respect to Ground -1.0V to +7.0V Maximum Operating Voltage 6.25V DC Output Current 5.0 mA *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Packaging Type TDFN VER 1.3 1                                                                                   ACE24C32/64                                               Technology Pin Configurations Pin Name A0~A2 SDA SCL WP VCC GND Function Device Address Inputs Serial Data Input / Output Serial Clock Input Write Protect Power Supply Ground Two-wire Serial EEPROM Block Diagram Figure 1 VER 1.3 2                                                                                  ACE24C32/64                                               Technology Ordering information Selection Guide ACE24C32/64 XX + X U : Tube T : Tape and Reel Pb - free DM : TDFN Two-wire Serial EEPROM Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. Serial Data (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. Device/Page Addresses (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other ACE24CXX/ACE24CXX devices. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).If the pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board Vcc plane is < 3pF, if coupling is > 3pF recommends connecting the address pins to GND. Write Protect (WP): The ACE24C32/64 has a Write Provides hardware data protection. The WP pin allows normal write operations when connected to ground (GND). When the Write Protect pin is connected to Vcc. All write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled is < 3pF , if coupling is > 3pF, recommends connecting the pins to GND. Switching WP to Vcc prior to a write operation creates a software write protected function. Write Protect Description WP Pin Status WP=VCC WP=GND Part of the Array Protected ACE24C32 ACE24C64 Full (32K) Memory Full (64K) Memory Normal Read/Write Operations VER 1.3 3                                                                                  ACE24C32/64                                               Technology Memory Organization Two-wire Serial EEPROM ACE24C32, 32K Serial EEPROM: Internally organized with 128 pages of 32 bytes each, the 32K requires a 12-bit data word address for random word addressing. ACE24C64, 64K Serial EEPROM: Internally organized with 256 pages of 32 bytes each, the 64K requires a 13-bit data word address for random word addressing. Pin Capacitance(1) Applicable over recommended operating range from: TA = 25℃, f = 1.0 MHz, VCC = +1.7V. Symbol CI/O 1 CIN 1 Test Condition Input / Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) Max Units Conditions 8 6 pF pF VI/O = 0V VIN = 0V Note: 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, (unless otherwise noted). Symbol VCC ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VOL2 VOL1 Parameter Supply Voltage Supply Current Supply Current Standby Current Standby Current Input Leakage Current Output Leakage Current Input Low Level Input High Level Output Low Level 2 Output Low Level 1 Test Condition Min 1.7 Typ Max 5.5 Units V mA mA µA µA µA µA V V V V VCC = 5V, Read at 400KHz VCC = 5V, Write at 400KHz VCC = 1.7V, VIN = VCC/ VSS VCC = 5.5V, VIN = VCC/ VSS VIN = VCC/VSS VOUT = VCC/ VSS -0.6 VCCx0.7 VCC = 3.0V, IOL = 2.1 mA VCC = 1.7V, IOL = 0.15 mA 0.4 2.0 1.0 3.0 1.0 6.0 0.10 0.05 3.0 3.0 VCCx0.3 VCC+0.5 0.4 0.2 Note: 1. VIL min and VIH max are reference only and are not tested. VER 1.3 4                                                                                  ACE24C32/64                                               Technology AC Characteristics Applicable over recommended operating range from: Two-wire Serial EEPROM TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol fSCL TLOW THIGH tI 1 Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High 1.7-volt 2.5-volt 5.5-volt Min Max Min Max Min Max 400 1.3 0.6 100 0.45 0.45 50 1000 0.4 0.4 50 1000 Units kHz µs µs TAA TBUF1 THD.STA TSU.STA THD.DAT TSU.DAT TR TF TSU.STO TDH TWR Endurance (1) Clock Low to Data Out Valid Time the bus must be free before a new transmission can Start Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time Inputs Fall Time Stop Setup Time Data Out Hold Time Write Cycle Time 3.6V, 25℃, Page Mode 0.1 0.9 0.05 0.55 0.05 0.55 1.3 0.6 0.6 0 100 0.3 300 0.6 50 5 0.25 50 5 1,000,000 0.5 0.25 0.25 0 100 0.3 100 0.25 50 5 0.5 0.25 0.25 0 100 0.3 100 µs µs µs µs µs ns µs ns µs ns ms Write Cycles Notes:1. This parameter is characterized and not 100% tested. 2.AC measurement conditions: RL (connects to Vcc): 1.3kΩ Input pulse voltages: 0.3 Vcc to 0.7 Vcc Input rise and fall times: ≦50 ns Input and output timing reference voltages: 0.5Vcc VER 1.3 5                                                                                  ACE24C32/64                                               Technology Device Operation Two-wire Serial EEPROM Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Figure 4). Data changes during SCL high periods will indicate a start or stop condition as defined below. Start Condition: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Figure 5). Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Figure 5). Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. Standby Mode : The ACE24C32/64 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the stop bit and the completion of any internal operations. Memory Reset : After an interruption in protocol power loss or system reset, any two-wire part can be protocol reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high and then. 3. Create a start condition as SDA is high. Bus Timing Figure 2．SCL: Serial Clock, SDA: Serial Data I/O VER 1.3 6                                                                                  ACE24C32/64                                               Technology Write Cycle Timing Two-wire Serial EEPROM Figure 3．SCL: Serial Clock, SDA: Serial Data I/O Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 4．Data Validity Figure 5．Start and Stop Definition Figure 6．Output Acknowledge VER 1.3 7                                                                                  ACE24C32/64                                               Technology Device Addressing Two-wire Serial EEPROM The 32K, 64K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The 32/64K EEPROM use the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hard-wired input pins. The A2,A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eight bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. Noise protection: Special internal circuitry place on the SDA and SCL pins prevent small noise spikes from activating the device. Date Security: The ACE24C32/64 has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at Vcc. Write Operations Byte Write: A write operation requires two 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 8). Page Write: The 32K/64K EEPROM is capable of an 32-byte page write.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 9). The data word address lower five bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. VER 1.3 8                                                                                  ACE24C32/64                                               Technology Two-wire Serial EEPROM Acknowledge Polling: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. Current Address Read: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 10). Random Read: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 11). Sequential Read: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit (64K) is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 12). 1 MSB 0 1 0 A2 A1 A0 R/W LSB VER 1.3 9                                                                                  ACE24C32/64                                               Technology Two-wire Serial EEPROM Figure 7．Device Address Figure 8．Byte Write Figure 9．Page Write Figure 10．Current Address Read VER 1.3 10                                                                                  ACE24C32/64                                               Technology Two-wire Serial EEPROM Figure 11． Random Read Figure 12． Sequential Read VER 1.3 11                                                                                  ACE24C32/64                                               Technology Packaging information TDFN Two-wire Serial EEPROM Top View Bottom View Side View *Control Dimensions: Millimeter Symbol A A1 A3 D E D1 E1 k b e L Millimeter Min. Max. 0.700 0.800 0.000 0.050 0.203REF. 1.900 2.100 2.900 3.100 1.400 1.600 1.400 1.600 0.200MIN. 0.200 0.300 0.500TYP. 0.200 0.400 VER 1.3 12                                                                                  ACE24C32/64                                               Technology Two-wire Serial EEPROM Notes ACE does not assume any responsibility for use as critical components in life support devices or systems without the express written approval of the president and general counsel of ACE Electronics Co., LTD. As sued herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ACE Technology Co., LTD. http://www.ace-ele.com/ VER 1.3 13