ACE93C46DPUH

                                                                                      ACE93C46                                               Technology Description Three-wire Serial EEPROM The ACE93C46 provides 1024 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 64 words of 16 bits each, when the ORG pin is connected to VCC and 128 words of 8 bits each when it is tied to ground. The ACE93C46 is available in space-saving 8-lead PDIP, 8-lead TSSOP and 8-lead JEDEC SOIC packages. The ACE93C46 is enabled through the Chip Select pin (CS), and accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The WRITE cycle is completely self-timed and no separate erase cycle is required before write. The Write cycle is only enabled when it is in the Erase/Write Enable state. When CS is brought “high” following the initiation of a write cycle, the DO pin outputs the Ready/Busy status. Features Low-voltage operation – 1.8 (VCC=1.8 to 5.5V) Three-wire serial Interface 2MHz clock rate(5V) compatibility Self-timed write cycle (5 ms max) High-reliability – Endurance: 1 Million write cycles Data retention: 100 Years 8-lead PDIP, SOP-8, TSSOP-8 Packages Packaging Type DIP-8 SOP-8 TSSOP-8 Pin Configurations Pin Name CS SK DI DO GND Vcc ORG DC Function Chip select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Internal Organization Don’t Connect VER 1.2 1                                                                                        ACE93C46                                               Technology Block Diagram Three-wire Serial EEPROM Note: When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground, the “x 8” organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the “x 16” organization is selected. Absolute Maximum Ratings DC Supply Voltage -0.3 to 6.5V Input / Output Voltage GND -0.3 to Vcc 0.3V Operating Ambient Temperature -40 to 85℃ Storage Temperature -65 to 150℃ *Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. VER 1.2 2                                                                                       ACE93C46                                               Technology Ordering information Selection Guide ACE93C46 XX + XH Halogen-free U : Tube T : Tape and Reel Pb - free DP : PDIP-8 FM : SOP-8 TM : TSSOP-8 Three-wire Serial EEPROM Pin Capacitance Applicable over recommended operating range from TA=25℃, f=1.0MHz,VCC=+1.8V (unless otherwise noted) Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI) Symbol Max Unit Conditions COUT CIN 5 5 pF pF VOUT=0V VIN=0V DC Characteristics Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.8V to +5.5V, (unless otherwise noted). Symbol VCC1 VCC2 VCC3 ICC1 ISB1 ISB2 ISB3 ILI(1) ILI(2) IOL VIL1(3) VIH1(3) Parameter Supply Voltage Supply Voltage Supply Voltage Test Condition Min 1.8 2.7 4.5 Typ Max 5.5 5.5 5.5 Units V V  V  mA µA µA µA µA µA µA V V 3 VCC = 5.0V, Supply Current Standby Current Standby Current Standby Current Input Leakage Input Leakage Output Leakage Input Low Voltage Input High Voltage Read at 1.0MHz Write at 1.0MHz VCC = 1.8V, CS=0V VCC = 2.7V, CS=0V VCC = 5.0V, CS=0V VIN = 0 to VCC VIN = 0 to VCC VIN = 0 to VCC 2.7V≦Vcc≦5.5V 2.7V≦Vcc≦5.5V -0.3 2.0 0.1 2.0 0.1 0.2 0.9 2.0 3.0 1.0 1.0 1.0 1.0 3.0 1.0 0.8 Vcc+0.3 VER 1.2                                                                                       ACE93C46 Max Vcc+0.3 Vcc+0.3 0.4 Units V V V                                               Technology Symbol VIL2(3) VIH2(3) VOL1 VOH1 VOL2 VOH2 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Condition 1.8V≦Vcc≦2.7V 1.8V≦Vcc≦2.7V 2.7V≦Vcc≦5.5V IOL=2.1mA IOH=-0.4mA 1.8V≦Vcc≦2.7V IOL=0.15mA IOH=-100uA Three-wire Serial EEPROM Min -0.3 Vcc*0.7 Typ 2.4 0.2 Vcc-0.2 V Note: 1. DI.CS. SK input pin 2. ORG input pin 3. VIL min and VIH max are reference only and are not tested. Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.8V to +5.5V, CL=1TTL Gate and 100pF (unless otherwise noted). Symbol fsx Parameter SK Clock Frequency Test Condition 4.5≦Vcc≦5.5v 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V 4.5≦Vcc≦5.5v Min 0 0 0 250 250 1000 250 250 1000 250 250 1000 50 50 200 100 100 400 0 Typ Max 2 1 0.25 Units MHz tskh SK High Time 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V 4.5≦Vcc≦5.5v ns tskl SK Low Time 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V 4.5≦Vcc≦5.5v ns tcs Minimum CS Low Time 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V 4.5≦Vcc≦5.5v 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V 4.5≦Vcc≦5.5v 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V Relative to SK ns tcss CS Setup Time Relative to SK Relative to SK ns tdis tcsh DI Setup Time CS Hold Time ns ns VER 1.2 4                                                                                       ACE93C46 Units ns 250 250 1000 250 250 1000 250 250 1000 100 100 400 ns ms Write Cycle ns ns ns                                               Technology Symbol tdih Parameter DI Hold Time Three-wire Serial EEPROM Test Condition Min 100 100 400 Typ Max 4.5≦Vcc≦5.5v 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V 4.5≦Vcc≦5.5v 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V 4.5≦Vcc≦5.5v Relative to SK tpd1 Output Delay to “1” AC Test tpd0 Output Delay to “0” AC Test 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V 4.5≦Vcc≦5.5v tsv CS to Status Valid AC Test 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V 4.5≦Vcc≦5.5v 2.7≦Vcc≦5.5V 1.8V≦Vcc≦5.5V 1.5 1M tdf twp Endurance(1) CS to DO in High Impedance Write Cycle Time 5.0V, 25℃ AC Test CS=VIL 5 Note: 1. This parameter is characterized and is not 100% tested. Functional Description The ACE93C46 is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic“1”) followed by the appropriate op code and the desired memory address location. Instruction Set for the ACE93C46 Instruction SB READ EWEN REASE WRITE ERAL WRAL 1 1 1 1 1 1 OP Code 10 00 11 01 00 00 Address *8 *16 A6-A0 11XXXXX A6-A0 A6-A0 A5-A0 11XXXX A5-A0 A5-A0 *8 Data *16 Comments Read data stored in memory, at specified address Write enable must precede all programming modes Erase memory location An-A0 Writes memory location An-A0 Erases all memory locations. Valid only at VCC=4.5V to 5.5V Writes all memory locations. Valid VER 1.2 5 D7-D0 D15-D0 10XXXXX 10XXXX 01XXXXX 01XXXX D7-D0 D15-D0                                                                                       ACE93C46                                               Technology Three-wire Serial EEPROM only at VCC=4.5V to 5.5V Disables all programming instructions EWDS 1 00 00XXXXX 00XXXX Notes: The X’s in the address field represent don’t care values and must be clocked. READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable(EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). A logic “1” at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the selftimed programming cycle, TWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250ns (TCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%. VER 1.2 6                                                                                       ACE93C46                                               Technology ERASE/WRITE DISABLE (EWDS): Three-wire Serial EEPROM To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. Timing Diagrams Note: This is the minimum SK period. Figure 1: Synchronous Data Timing Organization Key for Timing Diagrams I/O AN DN ACE93C46 (1K) *16 A5 D15 *8 A6 D7 Figure 2: Read Timing VER 1.2 7                                                                                       ACE93C46                                               Technology Three-wire Serial EEPROM Figure 3: EWEN Timing Figure 4: EWDS Timing Figure 5: WRITE Timing Note: Valid only at VCC=4.5V to 5.5V Figure 6: WRAL Timing (1) VER 1.2 8                                                                                       ACE93C46                                               Technology Three-wire Serial EEPROM Figure 7: ERASE Timing Note: Valid only at VCC=4.5V to 5.5V Figure 8: ERAL Timing (1) VER 1.2 9                                                                                       ACE93C46                                               Technology Packaging information PDIP-8 Three-wire Serial EEPROM Note: Dimensions in Millimeters. VER 1.2 10                                                                                       ACE93C46                                               Technology SOP-8 Three-wire Serial EEPROM Note: Dimensions in Millimeters. VER 1.2 11                                                                                       ACE93C46                                               Technology TSSOP-8 Three-wire Serial EEPROM Note: Dimensions in Millimeters. VER 1.2 12                                                                                       ACE93C46                                               Technology Three-wire Serial EEPROM Notes ACE does not assume any responsibility for use as critical components in life support devices or systems without the express written approval of the president and general counsel of ACE Electronics Co., LTD. As sued herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ACE Technology Co., LTD. http://www.ace-ele.com/ VER 1.2 13