11AA02E64T-I/SN

11AA02E48/11AA02E64 2K UNI/O® Serial EEPROMs with EUI-48™ or EUI-64™ Node Identity Device Selection Table Density (bits) VCC Range Page Size (Bytes) Temp. Ranges Packages Node Address 11AA02E48 2K 1.8V-5.5V 16 I SN, TT EUI-48™ 11AA02E64 2K 1.8V-5.5V 16 I SN, TT EUI-64™ Part Number Features Description • Preprogrammed Globally Unique, 48-Bit or 64-Bit Node Address • Compatible with EUI-48™ and EUI-64™ • Single I/O, UNI/O® Serial Interface Bus • Low-Power CMOS Technology: - 1 mA active current, typical - 1 µA standby current, maximum • 256 x 8-Bit Organization • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kbps Maximum Bit Rate – Equivalent to 100 kHz Clock Frequency • Self-Timed Write Cycle (including Auto-Erase) • Page-Write Buffer for up to 16 Bytes • STATUS Register for Added Control: - Write Enable Latch bit - Write-In-Progress bit • Block Write Protection: - Protect none, 1/4, 1/2 or all of array • Built-in Write Protection: - Power-on/off data protection circuitry - Write enable latch • High Reliability: - Endurance: 1,000,000 erase/write cycles - Data retention: >200 years - ESD protection: >4,000V • 3-Lead SOT-23 and 8-Lead SOIC Packages • Pb-Free and RoHS Compliant • Available Temperature Ranges: - Industrial (I): -40°C to +85°C The Microchip Technology Inc. 11AA02E48/11AA02E64 (11AA02EXX(1)) device is a 2 Kbit Serial Electrically Erasable PROM. The device is organized in blocks of x8-bit memory and support the patented(2) single I/O UNI/O® serial bus. By using Manchester encoding techniques, the clock and data are combined into a single, serial bit stream (SCIO), where the clock signal is extracted by the receiver to correctly decode the timing and value of each bit. Note 1: 11AA02EXX is used in this document as a generic part number for the 11AA02E48 and 11AA02E64 devices. 2: Microchip’s UNI/O® Bus products are covered by the following patents issued in the U.S.A.: 7,376,020 and 7,788,430. Low-voltage design permits operation down to 1.8V, with standby and active currents of only 1 µA and 1 mA, respectively. The 11AA02EXX is available in standard 8-lead SOIC and 3-lead SOT-23 packages. Package Types (not to scale) 3-Lead SOT-23 (TT) 2 VSS VCC 3 1 SCIO SOIC (SN) NC 1 8 VCC NC 2 7 NC NC 3 6 NC VSS 4 5 SCIO Pin Function Table Name SCIO VSS VCC  2008-2018 Microchip Technology Inc. Function Serial Clock, Data Input/Output Ground Supply Voltage DS20002122E-page 1 11AA02E48/11AA02E64 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V SCIO w.r.t. VSS .....................................................................................................................................-0.6V to VCC+1.0V Storage temperature ................................................................................................................................. -65°C to 150°C Ambient temperature under bias................................................................................................................. -40°C to 85°C ESD protection on all pins.......................................................................................................................................... 4 kV † NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. Symbol No. Characteristic Electrical Characteristics: Industrial (I): VCC = 2.5V to 5.5V VCC = 1.8V to 2.5V Min. Max. Units TA = -40°C to +85°C TA = -20°C to +85°C Test Conditions D1 VIH High-Level Input Voltage 0.7 VCC VCC+1 V D2 VIL Low-Level Input Voltage -0.3 0.3 VCC V VCC ≥ 2.5V -0.3 0.2 VCC V VCC < 2.5V 0.05 Vcc — V VCC ≥ 2.5V (Note 1) IOH = -300 µA, VCC = 5.5V D3 VHYS Hysteresis of Schmitt Trigger Inputs (SCIO) D4 VOH High-Level Output Voltage D5 D6 VOL IO D7 ILI D8 CINT D9 D10 D11 D12 Note 1: 2: VCC -0.5 — V VCC -0.5 — V IOH = -200 µA, Vcc = 2.5V — 0.4 V IOI = 300 µA, VCC = 5.5V — 0.4 V IOI = 200 µA, Vcc = 2.5V Output Current Limit (Note 2) — ±4 mA VCC = 5.5V (Note 1) — ±3 mA Vcc = 2.5V (Note 1) Input Leakage Current (SCIO) — ±1 µA VIN = VSS or VCC Internal Capacitance (all inputs and outputs) — 7 pF TA = 25°C, FCLK = 1 MHz, VCC = 5.0V (Note 1) — 3 mA VCC = 5.5V, FBUS = 100 kHz, CB = 100 pF — 1 mA VCC = 2.5V, FBUS = 100 kHz, CB = 100 pF — 5 mA VCC = 5.5V Low-Level Output Voltage ICCREAD Read Operating Current ICCWRITE Write Operating Current — 3 mA VCC = 2.5V Iccs Standby Current — 1 µA VCC = 5.5V, TA = 85°C ICCI Idle Mode Current — 50 µA VCC = 5.5V This parameter is periodically sampled and not 100% tested. The SCIO output driver impedance will vary to ensure IO is not exceeded.  2008-2018 Microchip Technology Inc. DS20002122E-page 2 11AA02E48/11AA02E64 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = 2.5V to 5.5V VCC = 1.8V to 2.5V AC CHARACTERISTICS Param. Symbol No. Characteristic Min. Max. Units 1 FBUS Serial Bus Frequency 10 100 kHz 2 TE Bit Period 10 100 µs 3 TIJIT Input Edge Jitter Tolerance — ±0.06 UI 4 FDRIFT Serial Bus Frequency Drift Rate Tolerance — ±0.50 % per byte 5 FDEV Serial Bus Frequency Drift Limit — ±5 % per command 6 TOJIT Output Edge Jitter — ±0.25 UI 7 TR SCIO Input Rise Time (Note 1) — 100 ns 8 TF SCIO Input Fall Time (Note 1) — 100 ns 9 TSTBY Standby Pulse Time 600 — µs 10 TSS Start Header Setup Time 10 — µs 11 THDR Start Header Low Pulse Time 5 — µs 12 TSP Input Filter Spike Suppression (SCIO) — 50 ns 13 TWC Write Cycle Time (byte or page) — Endurance (per page) 1M 14 TA = -40°C to +85°C TA = -20°C to +85°C Test Conditions Note 2 Note 2 Note 1 5 ms Write, WRSR commands 10 ms ERAL, SETAL commands — cycles 25°C, VCC = 5.5V (Note 3) Note 1: This parameter is periodically sampled and not 100% tested. 2: A Unit Interval (UI) is equal to 1-bit period (TE) at the current bus frequency. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained on Microchip’s website: www.microchip.com. TABLE 1-3: AC TEST CONDITIONS AC Waveform VLO = 0.2V VHI = VCC - 0.2V CL = 100 pF Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC  2008-2018 Microchip Technology Inc. DS20002122E-page 3 11AA02E48/11AA02E64 FIGURE 1-1: 10 BUS TIMING – START HEADER 11 2 SCIO Data ‘0’ FIGURE 1-2: Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘0’ Data ‘1’ MAK bit NoSAK bit BUS TIMING – DATA 2 7 8 Data ‘1’ Data ‘0’ 12 SCIO Data ‘0’ FIGURE 1-3: Data ‘1’ Data ‘1’ BUS TIMING – STANDBY PULSE 9 SCIO Standby Mode FIGURE 1-4: BUS TIMING – JITTER 2 3 Ideal Edge from Master  2008-2018 Microchip Technology Inc. 2 3 Ideal Edge from Master 6 6 Ideal Edge from Slave 6 6 Ideal Edge from Slave DS20002122E-page 4 11AA02E48/11AA02E64 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 11AA02EXX family of serial EEPROMs support the UNI/O® protocol. They can be interfaced with microcontrollers, including Microchip’s PIC® microcontrollers, ASICs, or any other device with an available discrete I/O line that can be configured properly to match the UNI/O protocol. The 11AA02EXX devices contain an 8-bit instruction register. The devices are accessed via the SCIO pin. Data is embedded into the I/O stream through Manchester encoding. The bus is controlled by a master device which determines the clock period, controls the bus access and initiates all operations, while the 11AA02EXX works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is active. FIGURE 2-1: BLOCK DIAGRAM STATUS Register HV Generator EEPROM Memory Control Logic I/O Control Logic X Array Dec Page Latches CurrentLimited Slope Control Y Decoder SCIO VCC VSS  2008-2018 Microchip Technology Inc. Sense Amp. R/W Control DS20002122E-page 5 11AA02E48/11AA02E64 3.0 BUS CHARACTERISTICS 3.1 Standby Pulse If a command is terminated in any manner other than a NoMAK/SAK combination, then the master must perform a standby pulse before beginning a new command, regardless of which device is to be selected When the master has control of SCIO, a standby pulse can be generated by holding SCIO high for TSTBY. At this time, the 11AA02EXX will reset and return to Standby mode. Subsequently, a high-to-low transition on SCIO (the first low pulse of the header) will return the device to the active state. . Note: Once a command is terminated satisfactorily (i.e., via a NoMAK/SAK combination during the Acknowledge sequence), performing a standby pulse is not required to begin a new command as long as the device to be selected is the same device selected during the previous command. However, a period of TSS must be observed after the end of the command and before the beginning of the start header. After TSS, the start header (including THDR low pulse) can be transmitted in order to begin the new command. An example of two consecutive commands is shown in Figure 3-1. Note that the device address is the same for both commands, indicating that the same device is being selected both times. A standby pulse cannot be generated while the slave has control of SCIO. In this situation, the master must wait for the slave to finish transmitting and to release SCIO before the pulse can be generated. If, at any point during a command, an error is detected by the master, a standby pulse should be generated and the command should be performed again. Standby Pulse(1) Start Header MAK SAK CONSECUTIVE COMMANDS EXAMPLE MAK NoSAK FIGURE 3-1: After a POR/BOR event occurs, a low-to-high transition on SCIO must be generated before proceeding with communication, including a standby pulse. Device Address SCIO Start Header 1 0 1 0 0 0 0 0 Device Address MAK SAK MAK NoSAK NoMAK SAK TSS 0 1 0 1 0 1 0 1 SCIO 0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first standby pulse. 3.2 Start Data Transfer All operations must be preceded by a start header. The start header consists of holding SCIO low for a period of THDR, followed by transmitting an 8-bit ‘01010101’ code. This code is used to synchronize the slave’s internal clock period with the master’s clock period, so accurate timing is very important. FIGURE 3-2: When a standby pulse is not required (i.e., between successive commands to the same device), a period of TSS must be observed after the end of the command and before the beginning of the start header. Figure 3-2 shows the waveform for the start header, including the required Acknowledge sequence at the end of the byte. START HEADER SCIO TSS THDR Data ‘0’ Data ‘1’  2008-2018 Microchip Technology Inc. Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK NoSAK DS20002122E-page 6 11AA02E48/11AA02E64 3.3 FIGURE 3-4: Acknowledge MAK (‘1’) SAK (‘1’) NoMAK (‘0’) NoSAK(1) An Acknowledge routine occurs after each byte is transmitted, including the start header. This routine consists of two bits. The first bit is transmitted by the master, and the second bit is transmitted by the slave. Note: A MAK must always be transmitted following the start header. The Master Acknowledge, or MAK, is signified by transmitting a ‘1’, and informs the slave that the current operation is to be continued. Conversely, a Not Acknowledge, or NoMAK, is signified by transmitting a ‘0’, and is used to end the current operation (and initiate the write cycle for write operations). Note: When a NoMAK is used to end a WRITE or WRSR instruction, the write cycle is not initiated if no bytes of data have been received. The slave Acknowledge, or SAK, is also signified by transmitting a ‘1’, and confirms proper communication. However, unlike the NoMAK, the NoSAK is signified by the lack of a middle edge during the bit period. Note: Note 1: 3.4 ACKNOWLEDGE BITS A NoSAK is defined as any sequence that is not a valid SAK. Device Addressing A device address byte is the first byte received from the master device following the start header. The device address byte consists of a four-bit family code, for the 11AA02EXX this is set as ‘1010’. The last four bits of the device address byte are the device code, which is hardwired to ‘0000’. FIGURE 3-5: In order to guard against bus contention, a NoSAK will occur after the start header. DEVICE ADDRESS BYTE ALLOCATION SLAVE ADDRESS MAK SAK A NoSAK will occur for the following events: • Following the start header • Following the device address, if no slave on the bus matches the transmitted address • Following the command byte, if the command is invalid, including Read, CRRD, Write, WRSR, SETAL, and ERAL during a write cycle. • If the slave becomes out of sync with the master • If a command is terminated prematurely by using a NoMAK, with the exception of immediately after the device address. See Figure 3-3 and Figure 3-4 for details. 1 3.5 0 1 0 0 0 0 0 Bus Conflict Protection To help guard against high-current conditions arising from bus conflicts, the 11AA02EXX features a current-limited output driver. The IOL and IOH specifications describe the maximum current that can be sunk or sourced, respectively, by the SCIO pin. The 11AA02EXX will vary the output driver impedance to ensure that the maximum current level is not exceeded. If a NoSAK is received from the slave after any byte (except the start header), an error has occurred. The master should then perform a standby pulse and begin the desired command again. FIGURE 3-3: ACKNOWLEDGE ROUTINE Master Slave MAK SAK  2008-2018 Microchip Technology Inc. DS20002122E-page 7 11AA02E48/11AA02E64 3.6 Device Standby The 11AA02EXX features a low-power Standby mode during which the device is waiting to begin a new command. A high-to-low transition on SCIO will exit low-power mode and prepare the device for receiving the start header. Standby mode will be entered upon the following conditions: • A NoMAK followed by a SAK (i.e., valid termination of a command) • Reception of a standby pulse Note: 3.7 In the case of the WRITE, WRSR, SETAL, or ERAL commands, the write cycle is initiated upon receipt of the NoMAK, assuming all other write requirements have been met. Device Idle The 11AA02EXX features an Idle mode during which all serial data is ignored until a standby pulse occurs. Idle mode will be entered upon the following conditions: • Invalid device address • Invalid command byte, including Read, CRRD, Write, WRSR, SETAL and ERAL during a write cycle • Missed edge transition • Reception of a MAK following a WREN, WRDI, SETAL, or ERAL command byte • Reception of a MAK following the data byte of a WRSR command An invalid start header will indirectly cause the device to enter Idle mode. Whether or not the start header is invalid cannot be detected by the slave, but will prevent the slave from synchronizing properly with the master. If the slave is not synchronized with the master, an edge transition will be missed, thus causing the device to enter Idle mode. 3.8 Synchronization At the beginning of every command, the 11AA02EXX utilizes the start header to determine the master’s bus clock period. This period is then used as a reference for all subsequent communication within that command. The 11AA02EXX features re-synchronization circuitry which will monitor the position of the middle data edge during each MAK bit and subsequently adjust the internal time reference in order to remain synchronized with the master.  2008-2018 Microchip Technology Inc. There are two variables which can cause the 11AA02EXX to lose synchronization. The first is frequency drift, defined as a change in the bit period, TE. The second is edge jitter, which is a single occurrence change in the position of an edge within a bit period, while the bit period itself remains constant. 3.8.1 FREQUENCY DRIFT Within a system, there is a possibility that frequencies can drift due to changes in voltage, temperature, etc. The re-synchronization circuitry provides some tolerance for such frequency drift. The tolerance range is specified by two parameters, FDRIFT and FDEV. FDRIFT specifies the maximum tolerable change in bus frequency per byte. FDEV specifies the overall limit in frequency deviation within an operation (i.e., from the end of the start header until communication is terminated for that operation). The start header at the beginning of the next operation will reset the re-synchronization circuitry and allow for another FDEV amount of frequency drift. 3.8.2 EDGE JITTER Ensuring that edge transitions from the master always occur exactly in the middle or end of the bit period is not always possible. Therefore, the re-synchronization circuitry is designed to provide some tolerance for edge jitter. The 11AA02EXX adjusts its phase every MAK bit, so TIJIT specifies the maximum allowable peak-to-peak jitter relative to the previous MAK bit. Since the position of the previous MAK bit would be difficult to measure by the master, the minimum and maximum jitter values for a system should be considered the worst-case. These values will be based on the execution time for different branch paths in software, jitter due to thermal noise, etc. The difference between the minimum and maximum values, as a percentage of the bit period, should be calculated and then compared against TIJIT to determine jitter compliance. Note: Because the 11AA02EXX only re-synchronizes during the MAK bit, the overall ability to remain synchronized depends on a combination of frequency drift and edge jitter (i.e., if the MAK bit edge is experiencing the maximum allowable edge jitter, then there is no room for frequency drift). Conversely, if the frequency has drifted to the maximum amount tolerable within a byte, then no edge jitter can be present. DS20002122E-page 8 11AA02E48/11AA02E64 4.0 DEVICE COMMANDS After the device address byte, a command byte must be sent by the master to indicate the type of operation to be performed. The code for each instruction is listed in Table 4-1. TABLE 4-1: INSTRUCTION SET Instruction Name Hex Code Description READ 0000 0011 0x03 Read data from memory array beginning at specified address CRRD 0000 0110 0x06 Read data from current location in memory array WRITE 0110 1100 0x6C Write data to memory array beginning at specified address WREN 1001 0110 0x96 Set the write enable latch (enable write operations) WRDI 1001 0001 0x91 Reset the write enable latch (disable write operations) RDSR 0000 0101 0x05 Read STATUS register WRSR 0110 1110 0x6E Write STATUS register ERAL 0110 1101 0x6D Write ‘0x00’ to entire array SETAL 0110 0111 0x67 Write ‘0xFF’ to entire array Read Instruction The Read command allows the master to access any memory location in a random manner. After the READ instruction has been sent to the slave, the two bytes of the Word Address are transmitted, with an Acknowledge sequence being performed after each byte. Then, the slave sends the first data byte to the master. If more data is to be read, the master sends a MAK, indicating that the slave should output the next data byte. This continues until the master sends a NoMAK, which ends the operation. READ COMMAND SEQUENCE Standby Pulse Start Header Device Address MAK SAK FIGURE 4-1: To provide sequential reads in this manner, the 11AA02EXX contains an internal Address Pointer which is incremented by one after the transmission of each byte. This Address Pointer allows the entire memory contents to be serially read during one operation. When the highest address is reached, the Address Pointer rolls over to address ‘0x00’ if the master chooses to continue the operation by providing a MAK. MAK NoSAK 4.1 Instruction Code SCIO 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 SCIO Word Address LSB MAK SAK Word Address MSB 1 0 1 0 0 0 0 0 MAK SAK Command MAK SAK 0 1 0 1 0 1 0 1 SCIO 7 6 5 4 3 2 1 0  2008-2018 Microchip Technology Inc. 7 6 5 4 3 2 1 0 Data Byte n NoMAK SAK Data Byte 2 MAK SAK Data Byte 1 MAK SAK 0 0 0 0 0 0 1 1 7 6 5 4 3 2 1 0 DS20002122E-page 9 11AA02E48/11AA02E64 4.2 TABLE 4-2: Current Address Read (CRRD) Instruction INTERNAL ADDRESS COUNTER The internal address counter featured on the 11AA02EXX maintains the address of the last memory array location accessed. The CRRD instruction allows the master to read data back beginning from this current location. Consequently, no word address is provided upon issuing this command. Command READ or WRITE MAK edge following each Address byte Counter is updated with newly received value Note that, except for the initial word address, the READ and CRRD instructions are identical, including the ability to continue requesting data through the use of MAKs in order to sequentially read from the array. READ, WRITE, or CRRD MAK/NoMAK edge following each data byte Counter is incremented by 1 As with the READ instruction, the CRRD instruction is terminated by transmitting a NoMAK. Note: If, following each data byte in a READ, WRITE, or CRRD instruction, neither a MAK nor a NoMAK edge is received (i.e., if a standby pulse occurs instead), the internal address counter will not be incremented. Note: During a Write command, once the last data byte for a page has been loaded, the internal Address Pointer will rollover to the beginning of the selected page. — Table 4-2 lists the events upon which the internal address counter is modified. Action Power-on Reset Counter is undefined Standby Pulse Start Header Device Address MAK SAK CRRD COMMAND SEQUENCE MAK NoSAK FIGURE 4-2: Event SCIO 7 6 5 4 3 2 1 0 SCIO MAK SAK Data Byte 1 1 0 1 0 0 0 0 0 MAK SAK Command MAK SAK 0 1 0 1 0 1 0 1 Data Byte 2 7 6 5 4 3 2 1 0 Data Byte n SCIO NoMAK SAK 0 0 0 0 0 1 1 0 7 6 5 4 3 2 1 0  2008-2018 Microchip Technology Inc. DS20002122E-page 10 11AA02E48/11AA02E64 Write Instruction Prior to any attempt to write data to the 11AA02EXX, the write enable latch must be set by issuing the WREN instruction (see Section 4.4 “Write Enable (WREN) and Write Disable (WRDI) Instructions”). Once the write enable latch is set, the user may proceed with issuing a WRITE instruction (including the header and device address bytes) followed by the MSB and LSB of the Word Address. Once the last Acknowledge sequence has been performed, the master transmits the data byte to be written. Upon receipt of each word, the four lower-order Address Pointer bits are internally incremented by one. The higher-order bits of the word address remain constant. If the master should transmit data past the end of the page, the address counter will roll over to the beginning of the page, where further received data will be written. Note: The 11AA02EXX features a 16-byte page buffer, meaning that up to 16 bytes can be written at one time. To utilize this feature, the master can transmit up to 16 data bytes to the 11AA02EXX, which are temporarily stored in the page buffer. After each data byte, the master sends a MAK, indicating whether or not another data byte is to follow. A NoMAK indicates that no more data is to follow, and as such will initiate the internal write cycle. If a NoMAK is generated before any data has been provided, or if a standby pulse occurs before the NoMAK is generated, the 11AA02EXX will be reset, and the write cycle will not be initiated. FIGURE 4-3: WRITE COMMAND SEQUENCE Standby Pulse Start Header MAK NoSAK Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page size (16 bytes) and end at addresses that are integer multiples of the page size minus 1. As an example, the page that begins at address 0x30 ends at address 0x3F. If a page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. MAK SAK 4.3 Device Address SCIO Word Address LSB 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 SCIO MAK SAK Word Address MSB 1 0 1 0 0 0 0 0 MAK SAK Command MAK SAK 0 1 0 1 0 1 0 1 SCIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 No MAK SAK Data Byte 2 MAK SAK Data Byte 1 MAK SAK 0 1 1 0 1 1 0 0 Data Byte n 7 6 5 4 3 2 1 0 Twc  2008-2018 Microchip Technology Inc. DS20002122E-page 11 11AA02E48/11AA02E64 Write Enable (WREN) and Write Disable (WRDI) Instructions The 11AA02EXX contains a write enable latch. See Table 6-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI instruction will reset the latch. The WREN and WRDI instructions must be terminated with a NoMAK following the command byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command. FIGURE 4-4: • • • • • • Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed ERAL instruction successfully executed SETAL instruction successfully executed WRITE ENABLE COMMAND SEQUENCE Standby Pulse Start Header Device Address MAK SAK Note: The following is a list of conditions under which the write enable latch will be reset: MAK NoSAK 4.4 SCIO Command 1 0 1 0 0 0 0 0 NoMAK SAK 0 1 0 1 0 1 0 1 SCIO 1 0 0 1 0 1 1 0 Standby Pulse Start Header Device Address MAK SAK WRITE DISABLE COMMAND SEQUENCE MAK NoSAK FIGURE 4-5: SCIO Command 1 0 1 0 0 0 0 0 NoMAK SAK 0 1 0 1 0 1 0 1 SCIO 1 0 0 1 0 0 0 1  2008-2018 Microchip Technology Inc. DS20002122E-page 12 11AA02E48/11AA02E64 The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user through the WRSR instruction. These bits are nonvolatile. Read Status Register (RDSR) Instruction The RDSR instruction provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows: Note: 7 6 5 4 3 2 1 0 X X X X BP1 BP0 WEL WIP Note: Bits 4-7 are don’t cares, and will read as ‘0’. The WIP and WEL bits will update dynamically (asynchronous to issuing the RDSR instruction). Furthermore, after the STATUS register data is received, the master can provide a MAK during the Acknowledge sequence to request that the data be transmitted again. This allows the master to continuously monitor the WIP and WEL bits without the need to issue another full command. The Write-In-Process (WIP) bit indicates whether the 11AA02EXX is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. This bit is set and cleared using the WREN and WRDI instructions, respectively. This bit is read-only for any other instruction. Once the master is finished, it provides a NoMAK to end the operation. Note: The current drawn for a Read Status Register command during a write cycle is a combination of the ICC Read and ICC Write operating currents. READ STATUS REGISTER COMMAND SEQUENCE Standby Pulse Start Header Device Address MAK SAK FIGURE 4-6: If Read Status Register command is initiated while the 11AA02EXX is currently executing an internal write cycle on the STATUS register, the new Block Protection bit values will be read during the entire command. MAK NoSAK 4.5 SCIO STATUS Register Data 1 0 1 0 0 0 0 0 NoMAK SAK Command MAK SAK 0 1 0 1 0 1 0 1 3 2 1 0 SCIO 0 0 0 0 0 1 0 1 0 0 0 0 Note: The STATUS register data can continuously be read or polled by transmitting a MAK in place of the NoMAK.  2008-2018 Microchip Technology Inc. DS20002122E-page 13 11AA02E48/11AA02E64 TABLE 4-3: Write Status Register (WRSR) Instruction The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array. The partitioning is controlled as illustrated in Table 4-3. BP1 BP0 Array Addresses Write-Protected 0 0 none 0 1 upper 1/4 (C0h-FFh) 1 0 upper 1/2 (80h-FFh) 1 1 all (00h-FFh) After transmitting the STATUS register data, the master must transmit a NoMAK during the Acknowledge sequence in order to initiate the internal write cycle. The WRSR instruction must be terminated with a NoMAK following the data byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command. FIGURE 4-7: WRITE STATUS REGISTER COMMAND SEQUENCE Standby Pulse Start Header Device Address MAK SAK Note: ARRAY PROTECTION MAK NoSAK 4.6 SCIO Status Register Data 1 0 1 0 0 0 0 0 NoMAK SAK Command MAK SAK 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 SCIO 0 1 1 0 1 1 1 0  2008-2018 Microchip Technology Inc. Twc DS20002122E-page 14 11AA02E48/11AA02E64 Erase All (ERAL) Instruction The ERAL instruction allows the user to write ‘0x00’ to the entire memory array with one command. Note that the write enable latch (WEL) must first be set by issuing the WREN instruction. The ERAL instruction is ignored if either of the Block Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2 or all of the array is protected. Note: Once the write enable latch is set, the user may proceed with issuing a ERAL instruction (including the header and device address bytes). Immediately after the NoMAK bit has been transmitted by the master, the internal write cycle is initiated, during which time all words of the memory array are written to ‘0x00’. ERASE ALL COMMAND SEQUENCE Standby Pulse MAK NoSAK FIGURE 4-8: The ERAL instruction must be terminated with a NoMAK following the command byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command. Start Header Device Address MAK SAK 4.7 SCIO Command 1 0 1 0 0 0 0 0 NoMAK SAK 0 1 0 1 0 1 0 1 SCIO Twc 0 1 1 0 1 1 0 1 Set All (SETAL) Instruction The SETAL instruction allows the user to write ‘0xFF’ to the entire memory array with one command. Note that the write enable latch (WEL) must first be set by issuing the WREN instruction. The SETAL instruction is ignored if either of the Block Protect bits (BP0, BP1) is not ‘0’, meaning 1/4, 1/2 or all of the array is protected. Note: Once the write enable latch is set, the user may proceed with issuing a SETAL instruction (including the header and device address bytes). Immediately after the NoMAK bit has been transmitted by the master, the internal write cycle is initiated, during which time all words of the memory array are written to ‘0xFF’. SET ALL COMMAND SEQUENCE Standby Pulse Start Header Device Address MAK SAK FIGURE 4-9: The SETAL instruction must be terminated with a NoMAK following the command byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command. MAK NoSAK 4.8 SCIO Command 1 0 1 0 0 0 0 0 NoMAK SAK 0 1 0 1 0 1 0 1 SCIO 0 1 1 0 0 1 1 1  2008-2018 Microchip Technology Inc. Twc DS20002122E-page 15 11AA02E48/11AA02E64 5.0 DATA PROTECTION The following protection has been implemented to prevent inadvertent writes to the array: • The Write Enable Latch (WEL) is reset on power-up • A Write Enable (WREN) instruction must be issued to set the write enable latch • After a write, ERAL, SETAL, or WRSR command, the write enable latch is reset • Commands to access the array or write to the status register are ignored during an internal write cycle and programming is not affected TABLE 6-1: 6.0 POWER-ON STATE The 11AA02EXX powers on in the following state: • The device is in low-power Shutdown mode, requiring a low-to-high transition on SCIO to enter Idle mode • The Write Enable Latch (WEL) is reset • The internal Address Pointer is undefined • A low-to-high transition, standby pulse and subsequent high-to-low transition on SCIO (the first low pulse of the header) are required to enter the active state . WRITE PROTECT FUNCTIONALITY MATRIX WEL Protected Blocks Unprotected Blocks Status Register 0 Protected Protected Protected 1 Protected Writable Writable  2008-2018 Microchip Technology Inc. DS20002122E-page 16 11AA02E48/11AA02E64 PREPROGRAMMED EUI-48™ OR EUI-64™ NODE ADDRESS 7.0 The 11AA02EXX is programmed at the factory with a globally unique node address stored in the upper 1/4 of the array and write-protected through the STATUS register. The remaining 1,536 bits are available for application use. FIGURE 7-1: MEMORY ORGANIZATION 00h 7.2 The 6-byte EUI-48™ node address value of the 11AA02E48 is stored in array locations 0xFA through 0xFF, as shown in Figure 7-2. The first three bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. The remaining three bytes are the Extension Identifier, and are generated by Microchip to ensure a globally-unique, 48-bit value. 7.2.1 Standard EEPROM Write-Protected Node Address Block 7.1 C0h FFh Factory-Programmed Write Protection 6 X — 5 X — 4 X — 3 BP1 0 2 BP0 1 1 WEL — 0 WIP — This protects the upper 1/4 of the array (0xC0 to 0xFF) from write operations. This array block can be utilized for writing by clearing the BP bits with a Write Status Register (WRSR) instruction. Note that if this is performed, care must be taken to prevent overwriting the node address value.  2008-2018 Microchip Technology Inc. ORGANIZATIONALLY UNIQUE IDENTIFIER (OUI) Each OUI provides roughly 16M (224) addresses. Once the address pool for an OUI is exhausted, Microchip will acquire a new OUI from IEEE to use for programming this model. For more information on past and current OUIs see “Organizationally Unique Identifiers For Preprogrammed EUI-48 and EUI-64 Address Devices” Technical Brief (DS90003187). In order to help guard against accidental corruption of the node address, the BP1 and BP0 bits of the STATUS register are programmed at the factory to ‘0’ and ‘1’, respectively, as shown in the following table. 7 X — EUI-48™ Node Address (11AA02E48) Note: 7.2.2 The OUI will change as addresses are exhausted. Customers are not guaranteed to receive a specific OUI and should design their application to accept new OUIs as they are introduced. EUI-64™ SUPPORT USING THE 11AA02E48 The preprogrammed EUI-48 node address of the 11AA02E48 can easily be encapsulated at the application level to form a globally unique, 64-bit node address for systems utilizing the EUI-64 standard. This is done by adding 0xFFFE between the OUI and the Extension Identifier, as shown below. Note: As an alternative, the 11AA02E64 features an EUI-64 node address that can be used in EUI-64 applications directly without the need for encapsulation, thereby simplifying system software. See Section 7.3 “EUI-64™ Node Address (11AA02E64)” for details. DS20002122E-page 17 11AA02E48/11AA02E64 FIGURE 7-2: Description EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (11AA02E48) 24-bit Organizationally Unique Identifier Data 00h Array Address FAh 04h A3h 24-bit Extension Identifier 12h 34h 56h FFh Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56 Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56  2008-2018 Microchip Technology Inc. DS20002122E-page 18 11AA02E48/11AA02E64 EUI-64™ Node Address (11AA02E64) 7.3 The 8-byte EUI-64™ node address value of the 11AA02E64 is stored in array locations 0xF8 through 0xFF, as shown in Figure 7-3. The first three bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. The remaining five bytes are the Extension Identifier, and are generated by Microchip to ensure a globally-unique, 64-bit value. Note: In conformance with IEEE guidelines, Microchip will not use the values 0xFFFE and 0xFFFF for the first two bytes of the EUI-64 Extension Identifier. These two values are specifically reserved to allow applications to encapsulate EUI-48 addresses into EUI-64 addresses. FIGURE 7-3: Description EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (11AA02E64) 40-bit Extension Identifier 24-bit Organizationally Unique Identifier Data 00h Array Address F8h 04h A3h 12h 34h 56h 78h 90h FFh Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90  2008-2018 Microchip Technology Inc. DS20002122E-page 19 11AA02E48/11AA02E64 8.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 8-1. TABLE 8-1: 8.1 PIN FUNCTION TABLE Name 3-pin SOT-23 8-pin SOIC SCIO 1 5 Serial Clock, Data Input/Output VCC 2 8 Supply Voltage Ground VSS 3 4 NC — 1, 2, 3, 6, 7 Description No Internal Connection Serial Clock, Data Input/Output (SCIO) SCIO is a bidirectional pin used to transfer commands and addresses into, as well as data into and out of the device. The serial clock is embedded into the data stream through Manchester encoding. Each bit is represented by a signal transition at the middle of the bit period.  2008-2018 Microchip Technology Inc. DS20002122E-page 20 11AA02E48/11AA02E64 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead SOIC Example XXXXXXXT XXXXYYWW NNN 11A2E48I SN e3 1628 1L7 3-Lead SOT-23 (11AA02E48) Example XXNN E217 3-Lead SOT-23 (11AA02E64) Example XXXNNN AAA1L7 1st Line Marking Code Part Number SOT-23 SOIC 11AA02E48 E2NN 11A2E48T 11AA02E64 AAANNN 11A2E64T Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC® designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2008-2018 Microchip Technology Inc. DS20002122E-page 21 11AA02E48/11AA02E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 2 1 e B NX b 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H SEE VIEW C VIEW A–A 0.23 L (L1) VIEW C Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2  2008-2018 Microchip Technology Inc. DS20002122E-page 22 11AA02E48/11AA02E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L Footprint L1 Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2  2008-2018 Microchip Technology Inc. DS20002122E-page 23 11AA02E48/11AA02E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev B  2008-2018 Microchip Technology Inc. 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