1553BBC-AR

Core1553BBC MIL-STD-1553B Bus Controller Product Summary Intended Use • • 1553B Bus Controller (BC) DMA Backend Interface to External Memory – Synthesis Scripts Actel-Developed Testbenches, VHDL and Verilog • Synthesis and Simulation Support • • Synthesis: Synplicity®, Synopsys® (Design Compiler®/ FPGA CompilerTM/FPGA ExpressTM), ExemplarTM Simulation: Vital-Compliant VHDL Simulators and OVI-Compliant Verilog Simulators Key Features • • Supports MIL-STD-1553B Interfaces to External RAM – Supports up to 128kbytes of Memory – Synchronous or Asynchronous Backend Interface – Backend Interface Identical to Core1553BRT Selectable Clock Rate of 12, 16, 20, or 24 MHz Provides Direct CPU Access to Memory Interfaces to Standard 1553B Transceivers Fully Automated Message Scheduling – Frame Support – Conditional Branching and Sub-routines – Variable Inter-message Gaps and RT Response Times – Real Time Clock for Message Scheduling – Asynchronous Message Support Verification and Compliance • • • Actel-Developed Simulation Testbench Core Implemented on the 1553B BC Development System Third-Party 1553B Compliance Testing of the 1553B Encoder and Decoder Blocks Implemented in an A54SXA32-STD Device • • • • Development System (Optional) • • • Complete 1553B BC Implementation in an SX-A Device Includes a PCI Interface for Host CPU Connection Includes Transceivers Components and Bus Termination Supported Families • • • • • • • Fusion ProASIC3/E ProASICPLUS Axcelerator RTAX SX-A RTSX-S Contents General Description ................................................... 2 Core1553BBC Device Requirements .......................... 4 Core1553BBC Verification and Compliance .............. 4 MIL-STD-1553B Bus Overview .................................... 4 I/O Signal Descriptions ............................................. 6 Bus Transceivers ........................................................ 20 Development System ............................................... 20 Typical BC System ..................................................... 22 Specifications ............................................................ 24 Ordering Information .............................................. 28 List of Changes ......................................................... 29 Datasheet Categories ............................................... 29 Core Deliverables • Netlist Version – Compiled RTL Simulation Model, Compliant with the Actel Libero™ Integrated Design Environment (IDE) – Compatible with the Actel Designer Place-andRoute Tool RTL Version – VHDL or Verilog Core Source Code • December 2005 © 2005 Actel Corporation v 4 .0 1 Core1553BBC MIL-STD-1553B Bus Controller General Description The Core1553BBC provides a complete, MIL-STD-1553B Bus Controller (BC). A typical system implementation using the Core1553BBC is shown in Figure 1. Core1553BBC reads message descriptor blocks from the memory and generates messages that are transmitted on the 1553B bus. Data words are read from the memory and transmitted on the 1553B bus. Data received is written to the memory. The core can be configured directly to connect to synchronous or asynchronous memory devices. The core consists of five main blocks: the 1553B encoder, the 1553B decoder, a protocol controller block, a CPU interface, and a backend interface (Figure 2). Backend Interface Memory BUSAINEN BUSAINP BUSAINN BUSAOUTINH BUSAOUTP BUSAOUTN RCVSTBA RXDAIN RXDAIN TXINHA TXDAIN TXDAIN Transceiver (Not Included) RCVSTBA RXDBIN RXDBIN TXINHA TXDBIN TXDBIN Glue Logic CPU CPU Interface Encoder Decoder BUSBINEN BUSBINP BUSBIN BUSAOUTINH BUSBOUTP BUSBOUTN Core1553BBC Actel FPGA Figure 1 • Typical Core1553BBC System BusA Protocol Controller BusB Backend Interface CPU Interface and Registers Core1553BBC Memory 64K*16 Figure 2 • Core1553BBC BC Block Diagram 2 v4.0 Core1553BBC MIL-STD-1553B Bus Controller A single 1553B encoder takes each word to be transmitted and serializes it using Manchester encoding. The encoder includes independent logic to prevent the BC from transmitting for greater than the allowed period and to provide loopback fail logic. The loopback logic monitors the received data and verifies that the core has correctly received every word that is transmitted. The encoder output is gated with the bus enable signals to select which buses the RT should be transmitting. Since the BC knows which bus is in use at any time, only a single decoder is required. The decoder takes the serial Manchester received data from the bus and extracts the received data words. The decoder requires a 12, 16, 20, or 24 MHz clock to extract the data and the clock from the serial stream. The decoder contains a digital phased lock loop (PLL) that generates a recovery clock used to sample the incoming serial data. The data is then deserialized and the 16-bit word decoded. The decoder detects whether a command, status or data word has been received and checks that no Manchester encoding or parity errors occurred in the word. The protocol controller block handles all the message sequencing and error recovery. This is a complex state machine that reads the 1553B message frames from the memory and transmits them on the 1553B bus. The CPU interface allows the system CPU to access the control registers within the BC. It also allows the CPU to directly access the memory connected to the backend interface. These features can simplify system design. The backend interface for the Core1553BBC allows a simple connection to a memory device. The backend interface can be configured to connect to either synchronous or asynchronous memory devices. This allows the core to be connected to synchronous logic or memory within the FPGA or to external asynchronous memory blocks. The interface supports a standard bus request and grant protocol and provides a WAIT input, allowing the core to interface to slow memory devices. This allows the core to share system memory rather than have its own dedicated memory block. Core1553BBC Operation A bus controller is responsible for sending data bus commands, participating in data transfers, receiving status responses, and monitoring the bus system. The system CPU will create message lists in the BC memory, as illustrated in Figure 3. When started, the BC works its way through the message lists. The Core1553B transmits the specified 1553B command and data words, and receives the 1553B status word and associated data words and writes them to the BC memory. During this process, the BC monitors all possible 1553B error conditions. If an RT does not respond correctly, the BC will retry the message on both the original bus and the alternate bus. Instruction List Message Block Data Block INSTRUCTION PARAMETER INSTRUCTION PARAMETER INSTRUCTION PARAMETER MSGCMD CW (RTRT RX) CW (RTRT TX) DATAPTR SW (RTRT TX) SW (RTRT RX) TSW 32 Data Words Figure 3 • Message Lists v4.0 3 Core1553BBC MIL-STD-1553B Bus Controller Core1553BBC Device Requirements The Core1553BBC can be implemented in several Actel FPGA devices. Table 1 shows typical utilization figures for the Core1553BBC implemented in these devices. Table 1 • Device Utilization Cells or Tiles Family Fusion ProASIC3/E ProASIC PLUS Combinatorial 1773 1773 2250 1072 1072 1115 1098 Sequential 558 558 560 584 584 589 598 Total 2331 2331 2810 1656 1656 1704 1696 Device AFS600 A3PE600 APA150-STD AX500-STD RTAX250-STD A54SX32A-STD RT54SX32S-STD Utilization 17% 17% 46% 20% 9% 56% 57% Axcelerator RTAX-S SX-A RTSX-S The Core1553BBC clock rate can be programmed to 12, 16, 20, or 24 MHz. All Actel device families listed in Table 1 easily meet this performance requirement. or Axcelerator When implemented in ProASIC devices, the Core1553BBC can connect directly to the internal FPGA memory blocks, eliminating the need for external memories. PLUS MIL-STD-1553B Bus Overview The MIL-STD-1553B bus is a differential serial bus used in military and space equipment. It is comprised of multiple redundant bus connections and communicates at 1MB per second. The bus has a single active bus controller (BC) and up to 31 remote terminals (RTs). The BC manages all data transfers on the bus using the command and status protocol. The bus controller initiates every transfer by sending a command word and data if required. The selected RT will respond with a status word and data if required. The 1553B command word contains a five-bit RT address, a transmit or receive bit, a five-bit sub-address and a fivebit word count. This allows for 32 RTs on the bus. However, since RT address 31 is used to indicate a broadcast transfer, only 31 RTs may be connected. Each RT has 30 sub-addresses reserved for data transfers. The other two sub-addresses (0 and 31) are reserved for mode codes. Data transfers contain up to (32) 16-bit data words. Mode code command words are used for bus control functions such as synchronization. Core1553BBC Verification and Compliance Core1553BBC is based upon the Actel Core1553BRT, which has been fully verified against the RT validation Test Plan (MIL-HDBK-1553A, Appendix A). This ensures that the 1553B encoders and decoders are fully compliant to the 1553B specification. The actual bus controller function has been extensively verified in both simulation and hardware. Core1553BBC has been implemented on an A54SX32A-STD part connected to external transceivers and memory. 4 v4.0 Core1553BBC MIL-STD-1553B Bus Controller Message Types The 1553B bus supports ten message transfer types, allowing basic point-to-point and broadcast BC to RT data transfers, mode code messages, and direct RT-to-RT messages. Figure 4 shows the message formats. BC-to-RT Transfer BC Transmit Command Data 0 Data ... Data n Response Time RT Status Word Message Gap BC Next Command RT-to-BC Transfer BC Receive Command Response Time RT Status Word Data 0 Data ... Data n Message Gap BC Next Command RT-to-RT Transfer BC Receive Transmit Command Command BC-to-all-RTs Broadcast BC Transmit Command Data 0 Data ... Data n Message Gap BC Next Command Response Time RT1 Status Word Data 0 Data ... Data n Response Time RT2 Status Word Message Gap BC Next Command RT-to-all RTs Broadcast BC Receive Transmit Command Command Response Time RT Status Word Data 0 Data ... Data n Message Gap BC Next Command Mode Command, No Data BC Mode Command Response Time RT Status Word Message Gap BC Next Command Mode Command, RT Transmit Data BC Mode Command Response Time RT Status Word Mode Data Message Gap BC Next Command Mode Command, RT Receive Data BC Mode Command Mode Data Response Time RT Status Word Message Gap BC Next Command Broadcast Mode Command, No Data BC Mode Command Message Gap BC Next Command Broadcast Mode Command with Data BC Mode Command Mode Data Message Gap BC Next Command Figure 4 • 1553B Message Formats v4.0 5 Core1553BBC MIL-STD-1553B Bus Controller Word Formats There are only three types of words in a 1553B message: a command word (CW), a data word (DW), and a status word (SW). Each 20-bit word consists of a 3-bit sync pattern, 16 bits of data, and a parity bit (Figure 5). Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CW Sync 5 RT Address 1 T/R 5 Sub-address 5 Word Count/Mode Code 1 P DW Sync 16 Data 1 P SW Sync 5 RT Address 1 Message Error 1 Instrumentation 1 Service Request 3 Reserved 1 1 1 Subsystem Flag 1 Dynamic Bus Acceptance 1 Terminal Flag 1 Broadcast Received Figure 5 • 1553B Word Formats I/O Signal Descriptions Table 2 • 1553B Bus Interface Name BUSAINEN BUSAINP BUSAINN BUSBINEN BUSBINP BUSBINN BUSAOUTIN BUSAOUTP BUSAOUTN BUSBOUTIN BUSBOUTP BUSBOUTN Type Out In In Out In In Out Out Out Out Out Out Description Active high output that enables for the A receiver Positive data input from the A receiver Negative data input from the A receiver Active high output that enables for the B receiver Positive data input from the bus to the B receiver Negative data input from the bus to the B receiver Active high transmitter inhibit for the A transmitter Positive data output to the bus A transmitter (is held high when no transmission) Negative data output to the bus A transmitter (is held high when no transmission) Active high transmitter inhibits the B transmitter Positive data output to the bus B transmitter (is held high when no transmission) Negative data output to the bus B transmitter (is held high when no transmission) 6 v4.0 Parity Busy Core1553BBC MIL-STD-1553B Bus Controller Table 3 • Control and Status Signals Name CLK RSTINn INTOUT MEMFAIL Type In In Out Out Description Master clock input (either 12 MHz, 16 MHz, 20 MHz, or 24 MHz) Reset input (active low) Interrupt Request (active high). The CPU is required to read the internal status register to find the reason for the interrupt. It is cleared by the CPU writing to the interrupt register. This goes high if the core fails to read or write data to the backend interface within the required time. This can be caused by the backend not asserting MEMGNTn fast enough or asserting MEMWAITn for too long. It is cleared by the CPU writing to the interrupt register. This is high when the core is active, i.e. processing a message list. External flag input used by the condition codes within the bus controller BUSY EXTFLAG Out In CPU Interface The CPU interface allows access to the Core1553BBC internal registers and direct access to the backend memory. This interface is synchronous to the clock (Table 4). Table 4 • CPU Interface Signals Name CPUCSn CPUWRn[1:0] Type In In Description CPU chip select input (active low) CPU write input (active low). Two write inputs are provided for processors that support byte operations. When CPUWRn[1] is '0,' data bits [15:8] are written. When CPUWRn[0] is '0,' data bits [7:0] are written. CPU read input (active low) CPU wait output (active low) indicates that the CPU should hold CPURDn or CPUWRn active while the core completes the read or write operation. CPUWAITn is not asserted when the internal CPU registers are accessed. When accessing the backend interface through the core, CPUWAIT will be activated for a minimum of four clock cycles for read operations and three for write operations. CPUWAITn is asserted for extra clock cycles if the backend interface delays asserting MEMGNTn or asserts MEMWAITn. Timing is shown in the Figure 12 on page 24 and Figure 13 on page 25. Selects whether the CPU accesses internal registers or backend memory. '0': Accesses internal registers, register number is specified on CPUADDR[2:0] '1': Accesses the backend memory CPU address input CPU data output CPU data input Data bus enable (active high). This signal is high when the core is providing data output on the CPUDOUT bus. It is intended for a tristate enable function. CPURDn CPUWAITn In Out CPUMEM In CPUADDR[15:0] CPUDOUT[15:0] CPUDIN[15:0] CPUDEN In Out In Out v4.0 7 Core1553BBC MIL-STD-1553B Bus Controller Backend Interface The backend interface supports both synchronous operation and asynchronous operation to backend devices. Synchronous operation directly supports the use of internal FPGA memory blocks. Asynchronous operation allows connection to standard external memory devices. Table 5 • Backend Signals Name MEMREQn Type Description Out Memory Request (active low) output. The BC holds MEMREQn active if it requires additional memory access cycles to take place immediately after the current memory cycle. This occurs during the intermessage gap. Memory Grant (active low) input. This input should be synchronous to CLK and needs to meet the internal register setup time. This input may be held low if the core has continuous access to the RAM. Memory Write (active low). When MEMWRn[1] is '0,' D[15:8] is written. When MEMWRn[0] is '0,' D[7:0] is written. Synchronous mode: This output indicates that data will be written on the rising clock edge. If MEMWAITn is asserted, the MEMWRn pulse will be extended until MEMWAITn becomes inactive. Asynchronous mode: This output will be low for a minimum of one clock period and can be extended by the MEMWAITn input. The address and data are valid one clock cycle before MEMWRn is active and held for one clock cycle after MEMWRn goes inactive. Memory Read (active low) Synchronous mode: This output indicates that data is read on the next rising clock edge. If MEMWAITn is active, then the data will be sampled on the rising clock edge on which MEMWAITn becomes inactive. This signal is intended as the read signal for synchronous RAMS. Asynchronous mode: This output will be low for a minimum of one clock period and can be extended by the MEMWAITn input. The address is valid one clock cycle before MEMRDn is active and held for one clock cycle after MEMRDn goes inactive. The data is sampled as MEMRDn goes high. Memory Chip Select (active low). This output has the same timing as MEMADDR. Memory Wait (active low) indicates that the backend is not ready, and the core should extend the read or write strobe period. This input should be synchronous to CLK and needs to meet the internal register setup time. It can be permanently held high. Memory address output Memory data output Memory data input Control signal enable (active high). This signal is high when the core is requesting the memory bus and has been granted control. It is intended to enable any tristate drivers that may be implemented on the memory control and address lines. Data bus enable (active high). This signal is high when the core is requesting the memory bus has been granted control and is waiting to write data. It is intended to enable any bidirectional drivers that may be implemented on the memory data bus. MEMGNTn MEMWRn[1:0] In Out MEMRDn Out MEMCSn MEMWAITn Out In MEMADDR[15:0] MEMDOUT[15:0] MEMDIN[15:0] MEMCEN Out Out In Out MEMDEN Out The backend interface must allow the bus controller access to the memory when requested. The memory access time from MEMREQn low to completion of the access cycle MEMRDn and MEMWRn high varies depending on the BC setup. When the CPU is allowed to access the memory through the bus controller (CPUMEMEN active), the memory access time is reduced (Table 6 on page 9). If the backend fails to allow the bus controller access to the memory in the required time, the bus controller will assert its MEMFAIL output and stop operation. 8 v4.0 Core1553BBC MIL-STD-1553B Bus Controller Miscellaneous I/O Several inputs are used to modify the core functionality to simplify integration in the application. These inputs should be tied to logic '0' or logic '1' as appropriate (Table 7). Table 6 • Memory Access Requirements CPUMEMEN 0 0 0 0 1 1 1 1 CLK Speed MHz 12 16 20 24 12 16 20 24 Memory Access Time 9.58µs 9.68µs 9.75µs 9.79µs 4.58µs 4.68µs 4.75µs 4.79µs Table 7 • Miscellaneous I/O Name ASYNCIF CPUMEMEN Type In In Description When '1,' the backend interface is in asynchronous mode. When '0,' the backend interface is in synchronous mode. When '1,' the CPU interface has access to the backend memory. When '0,' the CPU cannot access the backend memory through the core. This must be set to '0' if the core shares the CPU memory, i.e. the CPU and memory buses are connected to the same system bus. Bus Controller Registers The bus controller has nine internal registers used to control the bus controller operation and provide status information (Table 8). Table 8 • Bus Controller Registers Address 000 000 001 010 Name CONTROL STATUS SETUP LISTPTR Type W R RW RW Size [3:0] [15:0] [15:0] [15:0] Function Allows the CPU to control the BC Provides status information BC setup register Current LISTPTR value. The address of the current instruction being executed. At the start of operation, the CPU should set this to the point at the first instruction. This value will automatically step through the BC instruction list. Current MSGPTR value. Provides the address of the message block being processed. BC internal clock value This 16-bit value counts up at a 1µs, 4µs, 8µs, or 32µs rate. This gives a maximum timer value of 2 seconds. The CPU may directly load the counter. Asynchronous list pointer Provides a pointer to a list of messages that will be processed when started by the ASYNC message list bit in the control register. 011 100 MSGPTR CLOCK R RW [15:0] [15:0] 101 ASYNCPTR RW [15:0] v4.0 9 Core1553BBC MIL-STD-1553B Bus Controller Table 8 • Bus Controller Registers Address 110 Name STACKPTR Type RW Size [15:0] Function BC stack pointer This is the internal stack pointer register; it is used for the CALL and RETURN instructions. When the bus controller is started, the STACKPTR is set to FFFF. The upper eight bits are fixed to FF, and the lower eight bits will count down and up. This allows up to 255 addresses to be stored in the stack memory. Interrupt Register 111 INTERRUPT RW [15:0] Table 9 • Setup Register Bits 15 Name FORCEORUN Type RW Reset 0 Function '1': If a BC-RT message with a word count between 1 and 31 is carried out, the BC will transmit for greater than 680µs. This will cause the transmitter timer to trigger and the BC to shutdown. '0': Normal operation Enables the internal CLOCK to count '0': Internal CLOCK will not count '1': Internal CLOCK enabled The clock is automatically enabled by the WAITC instruction. Tells the core what the external clock frequency is 00: 12 MHz 01: 16 MHz 10: 20 MHz 11: 24 MHz Sets how the retry system works '0': Retries on the same bus for the number of times set by the reties setting in the message block, then on the alternate bus for the number of times set by the alternate bus reties in the message block. '1': Reties alternates between the two buses. The total number of retries is the number of reties plus alternative bus retries as set in the message block. Enables the external interrupt pin '1': The INTPENDING bit will drive the INTOUT pin '0': The INTOUT pin is held at a '0' '1': Sets the CLOCK register to 0000 when the BC is started '0': The CLOCK register is not reset when the BC is started '1': Sets the STACKPTR register to FFFF when the BC is started '0': The STACKPTR register is not reset when the BC is started. This allows the BC to be restarted when previously stopped. Sets the rate at which the TIMER and CLOCK count 00: 1µs 01: 4µs 10: 8µs 11: 32µs Sets the default minimum inter-message GAP 00: 4µs 01: 8µs 10: 16µs 11: 32µs Note: The actual inter-message GAP is a function of the memory access times. Typically, six memory accesses need to take place in the inter-message gap. 14 CLOCKEN RW 0 13:12 CLKFREQ RW 01 11 RETRYMODE WR 0 10 INTENABLE RW 0 9 8 AUTOCLOCK AUTOSTACK RW RW 1 1 7:6 CLKRATE RW 00 5:4 IMG RW 00 10 v4.0 Core1553BBC MIL-STD-1553B Bus Controller Table 9 • Setup Register (Continued) Bits 3:2 Name RESPTIME Type RW Reset 01 Function Sets the maximum time that the BC will wait for an RT to respond 00: 12µs 01: 16µs 10: 20µs 11: 24µs Reserved, return 00 1:0 Reserved R 00 Table 10 • Control Register Bits 3 Name ASYNC Type W Function Writing a '1' causes the bus controller to jump to process the asynchronous instruction list pointed to by the ASYNCPTR register at the end of the current message. When a RETAS instruction is found, the bus controller returns to the original instruction list. An ASYNC instruction can be issued while the bus controller is both active and inactive. Writing a '1' stops the bus controller immediately; both normal and asynchronous message operation will be aborted. Writing a '1' stops the bus controller at the end of the current message. Writing a '1' starts the bus controller. The bus controller cannot be started when an asynchronous message is active. 2 1 0 ABORT STOP START W W W Table 11 • Status Register Bits 15:8 7:6 5 4 3 2 1 Name VERSION Reserved LOOPFAIL FRAMEOK FLAG ASYNC BUSINUSE Type R R R R R R R Function Indicates the Core1553BBC code revision Core release notes provide latest version numbers. Reserved, set to 00 Indicates that a loopback failure occurred in the current frame Indicates that all the messages in the current frame have completed successfully and no system action is required Indicates the value of the flag condition stored by the STOREFLAG instruction Asynchronous message requested or in progress. This bit is cleared by the RETAS instruction. When it is active, the bus controller cannot be started. Indicates which bus is in use 0: Bus A 1: Bus B BC is Active 0 ACTIVE R v4.0 11 Core1553BBC MIL-STD-1553B Bus Controller Table 12 • Interrupt Register Bits 15 14:8 Name INTPENDING INTVECT Type RW RW Function When set, the BC has an interrupt pending. This bit is set if any of the INTVECT bits are set. Interrupt Reason The CPU writing a '1' to the bit clears the bit. 14 13 12 11 10 9 BC has completed the message list, HALT instruction executed INTREQ instruction executed Memory access failure. This bit also directly drives the MEMFAIL output. Asynchronous message is completed, RETAS instruction is executed. Transmitter shutdown is set when the core detects that it has been transmitting continuously on the bus for greater than 700µs. When set, the BC disables its transmitter. Stack pointer overflow or underflow is set if the BC attempts to push more than 256 return addresses onto the stack or pop of a non-existent address from the stack. The BC stops operation when this occurs. Corrupt instruction list or data table. Illegal command written to the control register, e.g. start instruction while an asynchronous message is active. The BC stops operation when this occurs. 8 7:0 USERVECT R Provides the user-supplied interrupt reason as set by the instruction parameter 12 v4.0 Core1553BBC MIL-STD-1553B Bus Controller Bus Controller Operation After power-up, the bus controller waits while the CPU sets up the bus controller memory and registers. The memory contains an instruction list, message blocks, and data blocks. Once the instruction list, message blocks, and data blocks are setup, the CPU starts the bus controller. The bus controller works its way through all the message blocks until it reaches the end of the instruction list (Figure 6). The instruction list contains a list of pointers to message blocks. The message block contains the command words transmitted on the 1553B bus and status words received from the 1553B bus. It also contains a pointer to a data block. The data block contains the data transmitted on the 1553B bus, or the data received from the 1553B bus. Instruction List INSTRUCTION PARAMETER INSTRUCTION PARAMETER INSTRUCTION PARAMETER Message Block MSGCMD CW (RTRT RX) CW (RTRT TX) DATAPTR SW (RTRT TX) SW (RTRT RX) TSW Data Block 32 Data Words Figure 6 • BC Memory Usage Instruction List The instruction list contains pairs of words: an instruction and a parameter. Core1553BBC supports a broad set of instructions allowing branching and sub-routine calls with condition code support. This allows complex instruction lists to be supported. The instruction contains a 4-bit OPCODE and a 5-bit condition code field (Table 13 and Table 14). Table 13 • Instruction Word 15:13 Reserved 12:8 CONDCODE 7:4 Reserved 3:0 OPCODE All of the OPCODES support the condition code field. If the condition is TRUE, then the OPCODE is carried out; otherwise, the BC continues to the next instruction. For RT-to-RT messages, the condition code will be true if the bit is set in either status word or not set in either status word (Table 15 on page 14). Table 14 • Supported Instructions OPCODE Function Condition Code Parameter 0000 0001 0010 0011 0100 0101 NOP DOMSG JUMP INTR HALT DELAY N/A Yes Yes Yes Yes Yes N/A Message Block Address New Instruction Address User interrupt value (Lower eight bits) User interrupt value (Lower eight bits) Timer value (Lower eight bits) Description No operation, jumps to next message Process the message block Jumps to the new message list address Force a BC interrupt Stop the BC Loads the timer with the parameter and waits until the timer reaches zero v4.0 13 Core1553BBC MIL-STD-1553B Bus Controller Table 14 • Supported Instructions (Continued) OPCODE Function Condition Code Parameter 0110 0111 1000 1001 1010 LOADC WAITC CALL RET RETAS Yes Yes Yes Yes Yes Clock value Clock value New Instruction Address N/A N/A Description Loads the BC clock Waits until the BC clock reaches the specified value Jumps to the new message list address and pushes the return address onto the stack Gets a return instruction address from the stack and jumps to it Gets a return instruction address from the stack and jumps to it. Also clears the ASYNC bit in the status register allowing further ASYNC messages to be accepted. Stores the selected flag so that it may be tested at a later stage. The condition code field indicates which flag to store. Will halt operation and set the illegal OPCODE interrupt 1011 Others STOREF Illegal Yes N/A N/A N/A Table 15 • Condition Codes Condition Code Function Description 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 10000 10001 10010 10011 10100 10101 10110 ALWAYS RESP GBR TF DBA SSF BUSY BR SR ME SWE SWAB ASYNC EXT SFLAG NEVER NORESP NGBR NTF NDBA NSSF NBUSY Always perform the associated instruction Performs the instruction if there was a response to the previous message Performs the instruction if the previous message was successful Performs the instruction if the Terminal Flag was set in the last received status word Perform the instruction if the Dynamic Bus Acceptance flag was set in the last received status word Performs the instruction if the Sub-system Flag was set in the last received status word Performs the instruction if the Busy bit was set in the last received status word Performs the instruction if the Broadcast Received bit was set in the last received status word Performs the instruction if the Service Request bit was set in the last received status word Performs the instruction if the Message Error bit was set in the last received status word Performs the instruction if the RT address field is incorrect, the instrumentation bit is set, or any of the reserved bits was set in the last received status word Performs the instruction if any bits are set in the last received status word (ignoring the RT address field) Performs the instruction if asynchronous message processing is active Performs the instruction if the External flag input is active '1' Performs the instruction if the previously stored flag bit was set Never performs the associated instruction Performs the instruction if there was no response to the previous message Performs the instruction if the previous message was unsuccessful Performs the instruction if the Terminal Flag was not set in the last received status word Performs the instruction if the Dynamic Bus Acceptance flag was not set in the last received status word Performs the instruction if the Sub-System Flag was not set in the last received status word Performs the instruction if the Busy bit was not set in the last received status word 14 v4.0 Core1553BBC MIL-STD-1553B Bus Controller Table 15 • Condition Codes (Continued) Condition Code Function Description 10111 11000 11001 11010 11011 11100 11101 11110 Others 0xxxx Others 1xxxx NBR NSR NME NSWE NOSWAB NASYNC NEXT NSFLAG Illegal Illegal Performs the instruction if the Broadcast Received bit was not set in the last received status word Performs the instruction if the Service Request bit was not set in the last received status word Performs the instruction if the Message Error bit was not set in the last received status word Performs the instruction if the RT address field is correct and the instrumentation bit is not set, and none of the reserved bits are set in the last received status word Performs the instruction if no bits (ignoring the RT address field) are set in the last received status word Performs the instruction if asynchronous message processing is not active Performs the instruction if the External flag input is inactive '0' Performs the instruction if the previously stored flag bit was not set Equivalent to NEVER Equivalent to ALWAYS v4.0 15 Core1553BBC MIL-STD-1553B Bus Controller Message Block An 8-word message block controls each message. The BC reads the 1553B command words from the message block and will write the received status words back to message block. Message blocks must be positioned on an 8-word memory boundary (Table 16). Table 16 • Message Block Offset 0 Contents MSGCMD Written by Description CPU Type of 1553B Message 15:10 Inter-message GAP (IMG) after this message, 0 to 63µs. When 000000, it uses the inter-message gap as set by the BC setup register. Longer IMG values can be achieved by using the DELAY instruction between messages. The actual IMG may be llonger than when set by this register. The BC needs to perform up to six memory accesses during the IMG period. If the backend memory responds slowly, then the IMG may increase '0': Normal Operation '1': The CLOCK value at the mid-point of the data word sync is used as the data for the synchronize with data mode code. Bus to use '0': Bus A '1': Bus B Retries on Alternate Bus 0 to 3 Retries on Bus 0 to 3 0000 0001 0110 0010 0011 0101 1000 1110 1010 1101 Others 1 2 3 CW RTRT TX CW DATAPTR CPU CPU CPU or BC 0 1 6 2 3 5 8 E A D Illegal BC-to-RT RT-to-BC Mode Code with no data Mode Code RT RX with data Mode Code RT TX with data RT-to-RT Broadcast BC-to-RT Broadcast Mode Code RT with no data Broadcast Mode Code RX with data Broadcast RT-to-RT 9 8: 7:6 5:4 3:0 1553B Command Word. For RT-to-RT messages, this is the RX command word RT-to-RT TX 1553B Command Word Data Messages Mode Code Messages Pointer to memory location containing the 32-word data buffer. Must be on a 32-word boundary, i.e. bits 4:0 are 00000 Mode code data word 4 5 SW RTRT RX SW BC BC Received status word. For RT-to-RT messages this is the status word from the TX RT Received status word from the RX RT for RT-to-RT messages 16 v4.0 Core1553BBC MIL-STD-1553B Bus Controller Table 16 • Message Block (Continued) Offset 6 Contents TSW Written by Description BC Message Transfer Status Word. Provides status information on the message block. The CPU should clear this field when setting up the message block 15 Message Okay '1': Message completed okay with no errors. May have been retried. '0': Message failed after all retries completed No response from RT RT Signaled Message Error 1553B Error occurred, encoding, parity, too many words, etc. Number of retry attempts to transmit the message (0-6) Unexpected bit set in the status word Got the RT-to-RT RX status word Got the status word, for RT-to-RT got the TX status word Number or data words transmitted or received. Note: '000000' indicates 0 and '100000' indicates 32 Not Used 14 13 12 11:9 8 7 6 5:0 7 Reserved – 15:0 v4.0 17 Core1553BBC MIL-STD-1553B Bus Controller Detailed Operation Flow Table 17 shows the operations the core goes through in processing a message list containing two messages. The first message is a BC-to-RT transfer of three words, and the second is an RT-to-BC transfer of three words. Table 17 • Typical Operation Time Memory Accesses Read first Instruction code Read first Instruction parameter Read first MSGCMD Read first CW Wait until the Inter-message gap expired Read the DATAPTR Read the 1st DW Read the 2nd DW Read the 3rd DW Transmit the 1st data word Transmit the 2nd data word Transmit the 3rd data word Wait for the RT Response Time Write the SW to memory Write the TSW to memory Read second Instruction code Read second instruction parameter Read second MSGCMD Read second CW Wait until the Inter-message gap expired Read the DATAPTR Wait for the RT Response Time Transmit the command word RT responds with SW Write the SW to memory Write the 1st DW to memory Write the 2nd DW to memory Write the 2nd DW to memory Write the TSW to memory Read third Instruction code (HALT) Generate the complete interrupt RT sends 1st data word RT sends 2nd data word RT sends 3rd data word RT responds with SW Transmit the command word Operation 1553B Activity 18 v4.0 Core1553BBC MIL-STD-1553B Bus Controller Error Conditions Core1553BBC monitors bus errors and in most cases will perform automatic retry operations if recovery is possible (Table 18). Table 18 • Error Conditions Error Condition Group Signaling Error 1553B signaling error, parity, Manchester error, too Message is retried many or to few words, or incorrect SYNC type 1553B Loopback Failure. Can occur if an RT responds Message is retried late, causing the RT response and following command Loopback bit set in BC status word to corrupt each other on the bus BC continues to process messages Transmitter Overrun. Internal timer detects the BC has BC controller aborts and asserts the transmitter transmitted for greater than 688µs. shutdown interrupt Memory Memory Access Failure Stack Overflow or Underflow Status Word Terminal Flag in SW Sub-system Flag in SW Service Request Flag in SW Broadcast bit is SW Busy Flag in SW Message Error bit in SW Other SW bit RT Response Miscellaneous No or Late Response BC controller aborts and asserts the memory failure interrupt BC controller aborts and asserts the stack overflow interrupt Unexpected bit in 1553B status bit set in the TSW. Message is not retried. Action Message is retried Message is retried Message is retried Corrupt Instruction List BC controller aborts and asserts the corrupt instruction Illegal OPCODE list interrupt. Message block MSGCMD message type bits [3:0] mismatch the provided command word Retries do not correct the error Message Okay bit in TSW not set Retry Fails CPU Interface Start or second asynchronous message command issued Command is ignored and an illegal command interrupt while an asynchronous message is active is generated. Loop Back Tests The Core1553BBC performs loopback testing on all of its transmissions; the transmit data is fed back into the receiver and each transmitted word is compared to the original. If an error is detected, the transmitter shutdown bit is set in the BC status register. All instructions make use of the condition codes. The condition codes cover error conditions, 1553B status word values, and an external input. Core1553BBC supports CALL and RETURN instructions with the aid of a stack that allows for 255 return addresses to be stored. The stack occupies the top 256 words of memory. To support message timing and minor/major frame timing, Core1553BBC has a built-in real-time clock (16bit) and timer (8-bit) that can be used to synchronize message timing. The real time clock and timer have a programmable resolution of 1µs, 4µs, 8µs, or 32µs. Messages can be programmed to be sent at an absolute time or relative to the end of the previous message. Message Sequence Control Core1553BBC message sequence control enables it to automatically sequence messages without CPU intervention. It supports conditional jumps and subroutine calls as well as time control functions. v4.0 19 Core1553BBC MIL-STD-1553B Bus Controller Asynchronous Messages Core1553BBC supports asynchronous messages. While idle, or when a normal message list is being processed, the CPU can initiate the core to jump to a secondary (asynchronous) message list and process these messages. When complete, the core will go back to the original message list. The asynchronous message list can be started directly by the CPU by writing to the control register. When the current message completes, the core pushes the current LISTPTR address on the stack and loads the LISTPTR with the value specified in the ASYNCPTR. It will execute these instructions until a RETAS instruction is found. At this point, the LISTPTR is reloaded from the stack and the bus controller enters the idle state or resumes the original instruction list. While the asynchronous message list is being processed, the START instruction and further asynchronous events are disabled. They are re-enabled by the RETAS instruction. message gap; this specifies the delay to the next message. Finally, the WAITC and DELAY instructions can be used to insert extra delays between messages. The actual IMG gap is also a function of the backend memory access system. There is a six-cycle overhead required between each message to read and write to the message block. These six memory accesses directly effect the inter-message gap. The actual IMG will be the largest of the duration of these six memory cycles or the programmed IMG value. Bus Transceivers Core1553BBC needs a 1553B transceiver to drive the 1553B bus. Core1553BBC is designed to directly interface to common MIL-STD-1553 transceivers, such as the DDC BU-63147 and the Aeroflex ACT4402. When using ProASICPLUS or Axcelerator, level translators are required to connect the 5V output levels of the 1553B transceivers to the 3.3V input levels of the FPGA. In addition to the transceiver, a pulse transformer is required for interfacing to the 1553B bus. Figure 7 on page 21, Figure 8 on page 22, and Figure 9 on page 23 show the connections required from the Core1553BBC to the transceivers and then to the bus via the pulse transformers. Retry Operations Core1553BBC supports an automatic retry system that retries messages that fail automatically. On detecting an error that can be retried, the BC immediately retries the message. Each message can be retried up to six times. The Core1553BBC can be programmed to retry up to three times on the original bus, then retry up to three times on the alternative bus, or to simply retry initially on the alternative bus and then switch buses after each attempt. Development System A complete 1553B Bus controller development system is also available. The Actel part number is “Core1553BBC Eval Board." The development system implements a PCI to 1553B bus controller on a single PCB using an Actel A54SX32A FPGA. The PCI target interface uses the Actel CorePCI66 PCI target interface core. Inter-Message Gap (IMG) Control Core1553BBC provides several ways to control the 1553B inter-message gaps. First, a default IMG is programmed into the Core1533BBC control register. Secondly every message block can be programmed with its own inter- 20 v4.0 Core1553BBC MIL-STD-1553B Bus Controller Memory 64K*16 Memory Access Backend Interface Pulse Transformer 1553B Control PCI Interface PCI Target Interface Core1553BBC Actel FPGA Development PCB Figure 7 • Core1553BBC Development System v4.0 CPU Interface Pulse Transceiver Transformer 21 Core1553BBC MIL-STD-1553B Bus Controller Typical BC System Core1553BBC requires a master CPU to set up the data tables. The CPU needs to be able to access the internal core registers as well as the backend memory. Core1553BBC can be configured in two ways with the CPU shared memory and with its own memory. When configured with its own memory, only the CPU port needs to be connected to the CPU. The CPU accesses the backend memory via Core1553BBC. This configuration also supports using an internal FPGA memory connected to the core and removes the need for external bus arbitration on the CPU bus. Alternatively, the core can share the CPU memory as shown in Figure 9 on page 23. In this case, both the backend memory and CPU interfaces are connected to the CPU bus. The core provides control lines that allow the memory and CPU interfaces to share the same toplevel I/O pins. When in this configuration, the core needs to read or write the memory it uses MEMREQn and MEMGNTn signals to arbitrate for the CPU bus before completing the cycle. Backend Interface Memory BUSAINEN BUSAINP BUSAINN BUSAOUTINH BUSAOUTP BUSAOUTN RCVSTBA RXDAIN RXDAIN TXINHA TXDAIN TXDAIN Transceiver Pulse Transformer CPU CPU Interface BUSBINEN BUSBINP BUSBIN BUSAOUTINH BUSBOUTP BUSBOUTN RCVSTBA RXDBIN RXDBIN TXINHA TXDBIN TXDBIN Pulse Transformer Core1553BBC Actel FPGA Figure 8 • Core1553BBC with Its Own Memory 22 v4.0 Core1553BBC MIL-STD-1553B Bus Controller Backend Interface Memory BUSAINEN BUSAINP BUSAINN BUSAOUTINH BUSAOUTP BUSAOUTN BUSBINEN BUSBINP BUSBIN BUSAOUTINH BUSBOUTP BUSBOUTN RCVSTBA RXDAIN RXDAIN TXINHA TXDAIN TXDAIN Transceiver RCVSTBA RXDBIN RXDBIN TXINHA TXDBIN TXDBIN Pulse Transformer CPU Core1553BBC Actel FPGA Figure 9 • Core1553BBC Using Shared Memory CPU Interface Bus Arbritator Pulse Transformer v4.0 23 Core1553BBC MIL-STD-1553B Bus Controller Specifications CPU Interface Timing CPUCSN CPURDN CPUADDR CPUMEM Tpd CPUDOUT CPUDEN CPUWAITN Figure 10 • CPU Interface Register Read Cycle ADDR Tpd Data CLK CPUCSN CPUWRN[1:0] CPUADDR CPUMEM CPUDIN CPUWAITN Write Done ADDR Data Figure 11 • CPU Interface Register Write Cycle CLK CPUCSN CPURDN CPUADDR CPUMEM CPUDOUT CPUDEN Tpd CPUWAITN Figure 12 • CPU Interface Memory Read Cycle ADDR Data Tpd 24 v4.0 Core1553BBC MIL-STD-1553B Bus Controller CLK CPUCSN CPUWRN CPUADDR CPUMEM CPUDIN Tpd CPUWAITN Figure 13 • CPU Interface Memory Write Cycle ADDR Data Write Tpd CPUWAITn will be driven low for a minimum of three (3) clock cycles for write cycles, four (4) for read cycles, and the number of clock cycles the memory backend delays the assertion of MEMGNTn and asserts MEMWAITn. CPUWAITn is driven low by CPURDn/CPUWRn becoming active and returns high on the falling clock edge after data is valid. CLK The CPU interface signals are internally synchronized to the Core1553BBC master clock. If these inputs are asynchronous, then CPUCSn, CPUADDR, and CPUDATA should be valid/invalid before CPUWRn, and remain valid after CPUWRn. CPUWRn must be active for at least one clock cycle. Tiack INTOUT CPURDN Figure 14 • Interrupt Timing Memory Timing CLK MEMREQn Tsu MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR Tsu MEMDIN MEMRDn Tsu MEMWAITn Tsu Figure 15 • Asynchronous Memory Read Cycle v4.0 25 Core1553BBC MIL-STD-1553B Bus Controller CLK MEMREQn Tsu MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn Tsu MEMWAITn Figure 16 • Asynchronous Memory Write Cycle Tsu CLK MEMREQn Tsu MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn MEMADDR Tsu MEMDIN Tsu MEMWAITn Figure 17 • Synchronous Memory Read Cycle Tsu CLK MEMREQn Tsu MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn Tsu MEMWAITn Figure 18 • Synchronous Memory Write Cycle Tsu 26 v4.0 Core1553BBC MIL-STD-1553B Bus Controller CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn MEMADDR Tsu MEMDIN MEMWAITn Figure 19 • Synchronous Memory Read Cycle with MEMGNTn Active CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn MEMWAITn Figure 20 • Synchronous Memory Write Cycle with MEMGNTn Active CLK Timeout MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn/WRn MEMWAITn MEMFAIL Figure 21 • Memory Grant Time-out v4.0 27 Core1553BBC MIL-STD-1553B Bus Controller CLK Timeout MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn/WRn Tsu MEMWAITn MEMFAIL Figure 22 • Memory Wait Time-out Clock Requirements To meet the 1553B transmission bit rate requirements, the Core1553BBC clock input must be 12, 16, 20, or 24 MHz with a tolerance of ±0.01%. Ordering Information Core1553BBC can be ordered through your local Actel sales representative. It should be ordered using the following number scheme: Core1553BBC-XX, where XX is (Table 19): Table 19 • Ordering Codes XX EV SN AN SR AR UR Description Evaluation Version Netlist for single-use on Actel devices Netlist for unlimited use on Actel devices RTL for single-use on Actel devices RTL for unlimited use on Actel devices RTL for unlimited use and not restricted to Actel devices The Evaluation board can also be ordered using the order code "Core1553BBC Eval Board." 28 v4.0 Core1553BBC MIL-STD-1553B Bus Controller List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v 4. 0 ) v3.0 The "Supported Families" section has been updated to include Fusion. Table 1 was updated to include Fusion data. v2.0 The "Supported Families" section has been updated to include ProASIC3/E. Table 1 was updated to include ProASIC3/E data. Page 1 4 1 4 Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. v4.0 29 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) 1276 401 450 Fax +44 (0) 1276 401 490 Actel Japan www.jp.actel.com EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Actel Hong Kong www.actel.com.cn Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 51700015-2/12.05