23LC512-E/SN

23A512/23LC512 512-Kbit SPI Serial SRAM with SDI and SQI Interface Device Selection Table VCC Range Temp. Ranges Dual I/O (SDI) Quad I/O (SQI) Max. Clock Frequency 23A512 1.7V-2.2V I, E Yes Yes 20 MHz(1) SN, ST, P 23LC512 2.5V-5.5V I, E Yes Yes 20 MHz(1) SN, ST, P Part Number Note 1: Packages 16 MHz for E-temp. Features Description • SPI-Compatible Bus Interface: - 20 MHz Clock rate - SPI/SDI/SQI mode • Low-Power CMOS Technology: - Read Current: 3 mA at 5.5V, 20 MHz - Standby Current: 4 A at +85°C • Unlimited Read and Write Cycles • Zero Write Time • 64K x 8-bit Organization: - 32-byte page • Byte, Page and Sequential mode for Reads and Writes • High Reliability • Temperature Ranges Supported: - Industrial (I): -40C to +85C - Extended (E): -40C to +125C The Microchip Technology Inc. 23A512/23LC512 are 512-Kbit Serial SRAM devices. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Additionally, SDI (Serial Dual Interface) and SQI (Serial Quad Interface) is supported if your application needs faster data rates. This device also supports unlimited reads and writes to the memory array. Package Types (not to scale) SOIC/TSSOP/PDIP • RoHS Compliant Packages • 8-Lead PDIP • 8-Lead SOIC • 8-Lead TSSOP CS 1 8 SO/SIO1 2 7 HOLD/SIO3 SIO2 3 6 SCK VSS 4 5 SI/SIO0 VCC Pin Function Table Name CS Function Chip Select Input SO/SIO1 Serial Output/SDI/SQI Pin SIO2 SQI Pin VSS Ground SI/SIO0 Serial Input/SDI/SQI Pin SCK Serial Clock HOLD/SIO3 Hold/SQI Pin VCC Power Supply  2012-2022 Microchip Technology Inc. and its subsidiaries DS20005155C-page 1 23A512/23LC512 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +0.3V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature under bias .............................................................................................................-40°C to +125°C † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. Sym. Characteristic Industrial (I): Extended (E): TA = -40°C to +85°C TA = -40°C to +125°C Min. Typ. Max. Units Test Conditions D001 VCC Supply voltage 1.7 2.5 — 2.2 5.5 V 23A512 23LC512 D002 VIH High-level input voltage 0.7 VCC — VCC + 0.3 V — D003 VIL Low-level input voltage -0.3 — 0.2 VCC 0.1 VCC V 23A512 23LC512 D004 VOL Low-level output voltage — — 0.2 V IOL = 1 mA D005 VOH High-level output voltage VCC - 0.5 — — V IOH = -400 A D006 ILI Input leakage current — — ±1 A CS = VCC, VIN = VSS OR VCC D007 ILO Output leakage current — — ±1 A CS = VCC, VOUT = VSS OR VCC D008 ICC Read Operating current — — 1 3 10 10 mA mA FCLK = 20 MHz; SO = O, 2.2V FCLK = 20 MHz; SO = O, 5.5V — 1 4 A — — 12 A — 4 10 A — — 20 A D009 ICCS Standby current CS = VCC = 2.2V, Inputs tied to VCC or VSS, I-Temp CS = VCC = 2.2V, Inputs tied to VCC or VSS, E-Temp CS = VCC = 5.5V, Inputs tied to VCC or VSS, I-Temp CS = VCC = 5.5V, Inputs tied to VCC or VSS, E-Temp D010 CINT Input capacitance — — 7 pF VCC = 5.0V, f = 1 MHz, TA = 25°C (Note 1) D011 VDR RAM data retention voltage — 1.0 — V (Note 2) Note 1: 2: 3: This parameter is periodically sampled and not 100% tested. This is the limit to which VCC can be lowered without losing RAM data. This parameter is periodically sampled and not 100% tested. Typical measurements taken at room temperature. DS20005155C-page 2  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C Extended (E): TA = -40°C to +125°C AC CHARACTERISTICS Param. Sym. No. Characteristic Min. Max. Units Test Conditions 1 FCLK Clock frequency — 20 16 MHz I-Temp E-Temp 2 TCSS CS setup time 25 32 — ns I-Temp E-Temp 3 TCSH CS hold time 50 — ns — 4 TCSD CS disable time 25 32 — ns I-Temp E-Temp 5 Tsu Data setup time 10 — ns — 6 THD Data hold time 10 — ns — 7 TR CLK rise time — 20 ns (Note 1) 8 TF CLK fall time — 20 ns (Note 1) 9 THI Clock high time 25 32 — ns I-Temp E-Temp 10 TLO Clock low time 25 32 — ns I-Temp E-Temp 11 TCLD Clock delay time 25 32 — ns I-Temp E-Temp 12 TV Output valid from clock low — 25 32 ns I-Temp E-Temp 13 THO Output hold time 0 — ns (Note 1) 14 TDIS Output disable time — 20 ns — 15 THS HOLD setup time 10 — ns — 16 THH HOLD hold time 10 — ns — 17 THZ HOLD low to output High-Z 10 — ns — 18 THV HOLD high to output valid — 50 ns — Note 1: This parameter is periodically sampled and not 100% tested. TABLE 1-3: AC TEST CONDITIONS AC Waveform: Input pulse level Input rise/fall time CL = 30 pF 0.1 VCC to 0.9 VCC 5 ns — Timing Measurement Reference Level: Input 0.5 VCC Output 0.5 VCC  2012-2022 Microchip Technology Inc. and its subsidiaries DS20005155C-page 3 23A512/23LC512 FIGURE 1-1: HOLD TIMING CS 16 15 16 15 SCK 17 SO n+2 SI n+2 n+1 n 18 High-Impedance n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING (SPI MODE) 4 CS 2 7 8 3 11 SCK 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING (SPI MODE) CS 9 3 10 SCK 12 SO SI DS20005155C-page 4 13 MSB out 14 LSB out Don’t Care  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 23A512/23LC512 is an 512Kbit Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. In addition, the 23A512/ 23LC512 is also capable of operating in SDI/SQI high speed SPI mode. The 23A512/23LC512 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSB first, LSB last. 2.2 Modes of Operation The 23x512 has three modes of operation that are selected by setting bits 7 and 6 in the MODE register. The modes of operation are Byte, Page and Burst. Byte Operation – is selected when bits 7 and 6 in the MODE register are set to 00. In this mode, the read/ write operations are limited to only one byte. The Command followed by the 16-bit address is clocked into the device and the data to/from the device is transferred on the next eight clocks (Figure 2-1, Figure 2-2). If operating in Sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (FFFFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin. 2.4 Write Sequence Prior to any attempt to write data to the 23A512/ 23LC512, the device must be selected by bringing CS low. Once the device is selected, the Write command can be started by issuing a WRITE instruction, followed by the 16-bit address, and then the data to be written. A write is terminated by the CS being brought high. If operating in Page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. The Address Pointer is automatically incremented. This operation can continue for the entire page (32 bytes) before data will start to be overwritten. If operating in Sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the device. The internal Address Pointer is automatically incremented. When the Address Pointer reaches the highest address (FFFFh), the address counter rolls over to (0000h). This allows the operation to continue indefinitely, however, previous data will be overwritten. Page Operation – is selected when bits 7 and 6 in the MODE register are set to 10. The 23x512 has 2048 pages of 32 bytes. In this mode, the read and write operations are limited to within the addressed page (the address is automatically incremented internally). If the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page (Figure 2-3, Figure 2-4). Sequential Operation – is selected when bits 7 and 6 in the MODE register are set to 01. Sequential operation allows the entire array to be written to and read from. The internal address counter is automatically incremented and page boundaries are ignored. When the internal address counter reaches the end of the array, the address counter will roll over to 0x0000 (Figure 2-5, Figure 2-6). 2.3 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 23A512/23LC512 followed by the 16-bit address. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin.  2012-2022 Microchip Technology Inc. and its subsidiaries DS20005155C-page 5 23A512/23LC512 TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Hex Code Description READ 0000 0011 0x03 Read data from memory array beginning at selected address WRITE 0000 0010 0x02 Write data to memory array beginning at selected address EDIO 0011 1011 0x3B Enter Dual I/O access EQIO 0011 1000 0x38 Enter Quad I/O access RSTIO 1111 1111 0xFF Reset Dual and Quad I/O access RDMR 0000 0101 0x05 Read Mode Register WRMR 0000 0001 0x01 Write Mode Register FIGURE 2-1: BYTE READ SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 0 SI 0 0 0 0 16-bit Address 0 1 1 15 14 13 12 2 1 0 Data Out High-Impedance 7 SO FIGURE 2-2: 6 5 4 3 2 1 0 BYTE WRITE SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 0 1 0 15 14 13 12 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 16-bit Address Data Byte 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO DS20005155C-page 6  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 FIGURE 2-3: PAGE READ SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 16-bit Address 0 1 2 1 15 14 13 12 1 0 Page X, Word Y Page X, Word Y High-Impedance SO 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 SCK SI Page X, Word Y+1 7 SO 6 FIGURE 2-4: 5 4 3 2 1 Page X, Word 0 Page X, Word 31 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 PAGE WRITE SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK SI 0 0 Page X, Word Y 16-bit Address Instruction 0 1 2 0 15 14 13 12 1 0 7 6 5 4 3 2 1 0 Page X, Word Y CS 32 33 34 35 36 37 38 39 SCK Page X, Word Y+1 SI 7 6 5 4 3 2 1 Page X, Word 31 0  2012-2022 Microchip Technology Inc. and its subsidiaries 7 6 5 4 3 2 Page X, Word 0 1 0 7 6 5 4 3 2 1 0 DS20005155C-page 7 23A512/23LC512 FIGURE 2-5: SEQUENTIAL READ SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 16-bit Address 0 1 2 1 15 14 13 12 1 0 Page X, Word Y 7 SO 6 5 4 3 2 1 0 CS SCK SI Page X, Word 31 SO 7 6 5 4 3 2 Page X+1, Word 0 1 0 7 6 5 4 3 2 1 Page X+1, Word 1 0 7 6 5 4 3 2 1 0 CS SCK SI Page X+1, Word 31 SO 7 DS20005155C-page 8 6 5 4 3 2 Page X+n, Word 1 1 0 7 6 5 4 3 2 Page X+n, Word 31 1 0 7 6 5 4 3 2 1 0  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 FIGURE 2-6: SEQUENTIAL WRITE SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 Data Byte 1 2 0 15 14 13 12 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 Data Byte 3 1 0  2012-2022 Microchip Technology Inc. and its subsidiaries 7 6 5 4 3 2 Data Byte n 1 0 7 6 5 4 3 2 1 0 DS20005155C-page 9 23A512/23LC512 2.5 Read Mode Register Instruction (RDMR) The mode bits indicate the operating mode of the SRAM. The possible modes of operation are: 0 0 = Byte mode The Read Mode Register instruction (RDMR) provides access to the MODE register. The MODE register may be read at any time. The MODE register is formatted as follows: TABLE 2-2: 1 0 = Page mode 0 1 = Sequential mode (default operation) 1 1 = Reserved Bits 0 through 5 are reserved and should always be set to ‘0’. MODE REGISTER 7 6 5 4 3 2 1 0 W/R W/R – – – – – – 0 0 0 0 0 0 MODE MODE See Figure 2-7 for the RDMR timing sequence. W/R = writable/readable FIGURE 2-7: READ MODE REGISTER TIMING SEQUENCE (RDMR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 0 High-Impedance SO DS20005155C-page 10 1 0 1 Data from MODE Register 7 6 5 4 3 2  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 2.6 Write Mode Register Instruction (WRMR) The Write Mode Register instruction (WRMR) allows the user to write to the bits in the MODE register as shown in Table 2-2. This allows for setting of the Device Operating mode. Several of the bits in the MODE register must be cleared to ‘0’. See Figure 2-8 for the WRMR timing sequence. FIGURE 2-8: WRITE MODE REGISTER TIMING SEQUENCE (WRMR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 Data to MODE Register 0 0 0 1 7 6 5 4 3 2 High-Impedance SO 2.7 Power-On State The 23A512/23LC512 powers on in the following state: • The device is in low-power Standby mode (CS = 1) • A high-to-low-level transition on CS is required to enter active state  2012-2022 Microchip Technology Inc. and its subsidiaries DS20005155C-page 11 23A512/23LC512 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Name PIN FUNCTION TABLE SOIC/ PDIP TSSOP Function CS 1 Chip Select Input SO/SIO1 2 Serial Data Output/SDI/SQI Pin SIO2 3 SQI Pin VSS 4 Ground SI/SIO0 5 Serial Data Input/SDI/SQI Pin SCK 6 Serial Clock Input HOLD/SIO3 7 Hold/SQI Pin VCC 8 Power Supply 3.1 Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. When the device is deselected, SO goes to the highimpedance state, allowing multiple parts to share the same SPI bus. After power-up, a low level on CS is required, prior to any sequence being initiated. 3.2 Serial Output (SO) The SO pin is used to transfer data out of the 23A512/ 23LC512. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 3.3 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock. 3.4 3.6 Serial Clock (SCK) The SCK is used to synchronize the communication between a host and the 23A512/23LC512. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 3.7 Hold Function (HOLD) The HOLD pin is used to suspend transmission to the 23A512/23LC512 while in the middle of a serial sequence without having to re-transmit the entire sequence over again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin should be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The 23A512/ 23LC512 must remain selected during this sequence. The SI and SCK levels are “don’t cares” during the time the device is paused and any transitions on these pins will be ignored. To resume serial communication, HOLD should be brought high while the SCK pin is low, otherwise serial communication will not be resumed until the next SCK high-to-low transition. The SO line will tri-state immediately upon a high-to low transition of the HOLD pin, and will begin outputting again immediately upon a subsequent lowto-high transition of the HOLD pin, independent of the state of SCK. Hold functionality is not available when operating in SQI mode. Serial Dual Interface Pins(SIO0, SIO1) The SIO0 and SIO1 pins are used for SDI mode of operation. Functionality of these I/O pins is shared with SO and SI. 3.5 Serial Quad Interface Pins (SIO0 – SIO3) The SIO0 through SIO3 pins are used for SQI mode of operation. Because of the shared functionality of these pins the HOLD feature is not available when using SQI mode. DS20005155C-page 12  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 3.8 SPI/SDI and SQI Pin Designations SPI Mode: CS 1 8 Vcc SO 2 7 HOLD NC 3 6 SCK Vss 4 5 SI SDI Mode: CS 1 8 Vcc SIO1 2 7 HOLD NC 3 6 SCK Vss 4 5 SIO0 SQI Mode: Note: CS 1 8 Vcc SIO1 2 7 SIO3 SIO2 3 6 SCK Vss 4 5 SIO0 Pin 3 should not be left floating when using SPI/SDI mode.  2012-2022 Microchip Technology Inc. and its subsidiaries DS20005155C-page 13 23A512/23LC512 4.0 DUAL AND QUAD SERIAL MODE 4.1 The 23A512/23LC512 supports Serial Dual Input (SDI) mode of operation. To enter SDI mode the EDIO command must be clocked in (Figure 4-1). It should be noted that if the MCU resets before the SRAM, the user will need to determine the serial mode of operation of the SRAM and reset it accordingly. Byte read and write sequence in SDI mode is shown in Figure 4-2 and Figure 4-3. The 23A512/23LC512 also supports SDI (Serial Dual) and SQI (Serial Quad) mode of operation when used with compatible host devices. As a convention for SDI mode of operation, two bits are entered per clock using the SIO0 and SIO1 pins. Bits are clocked MSB first. For SQI mode of operation, four bits of data are entered per clock, or one nibble per clock. The nibbles are clocked MSB first. FIGURE 4-1: Dual Interface Mode ENTER SDI MODE (EDIO) FROM SPI MODE CS 0 1 2 3 0 1 1 4 5 6 7 SCK SI 0 1 0 1 1 High-Impedance SO 4.2 Quad Interface Mode In addition to the Serial Dual Interface (SDI) mode of operation Serial Quad Interface (SQI) is also supported. In this mode the HOLD functionality is not available. To enter SQI mode the EQIO command must be clocked in (Figure 4-4). DS20005155C-page 14  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 FIGURE 4-2: BYTE READ MODE SDI CS 0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 8 SCK 1 14 12 10 0 0 0 SIO0 Instruction 0 0 SIO1 8 6 2 6 0 Dummy Byte 16-Bit Address 1 15 13 11 9 0 4 7 5 4 2 0 Data Out 7 3 1 5 3 1 Note: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high. Note: The first byte read after the address will be a dummy byte. FIGURE 4-3: BYTE WRITE MODE SDI CS 0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 8 SCK SIO0 0 0 0 0 14 12 10 Instruction SIO1 Note: 0 0 0 8 6 4 2 0 6 7 5 2 0 Data In 16-Bit Address 1 15 13 11 9 4 3 1 7 5 3 1 Page and Sequential mode are similar in that additional bytes can be clocked in before CS is brought high.  2012-2022 Microchip Technology Inc. and its subsidiaries DS20005155C-page 15 23A512/23LC512 FIGURE 4-4: ENTER SQI MODE (EQIO) FROM SPI MODE CS 0 1 2 3 0 1 1 4 5 6 7 SCK 0 SI 1 0 0 0 7 8 9 High-Impedance SO 4.3 Exit SDI or SQI Mode To exit from SDI mode, the RSTIO command must be issued. The command must be entered in the current device configuration, either SDI or SQI, see Figure 4-7 and Figure 4-8. FIGURE 4-5: BYTE READ MODE SQI CS 0 4 1 2 3 0 1 12 8 4 0 4 0 0 1 13 9 5 1 5 1 SIO2 0 0 14 10 6 2 6 2 SIO3 0 0 15 11 7 3 7 3 5 6 SCK SIO0 SIO1 Instruction 16-Bit Address Dummy Byte Data Out Note: Page and Sequential mode is similar in that additional bytes can be clocked out before CS is brought high. Note: The first byte read after the address will be a dummy byte. DS20005155C-page 16  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 FIGURE 4-6: BYTE WRITE MODE SQI CS 0 4 1 2 3 0 1 12 8 4 0 4 0 4 0 0 1 13 9 5 1 5 1 5 1 SIO2 0 0 14 10 6 2 6 2 6 2 SIO3 0 0 15 11 7 3 7 3 7 3 5 6 7 9 8 SCK SIO0 SIO1 Instruction Note: 16-Bit Address Data N Data N+1 Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high. FIGURE 4-7: RESET SDI MODE (RSTIO) – FROM SDI MODE CS 0 1 2 3 SIO0 1 1 1 1 SIO1 1 1 1 1 SCK  2012-2022 Microchip Technology Inc. and its subsidiaries DS20005155C-page 17 23A512/23LC512 FIGURE 4-8: RESET SDI/SQI MODE (RSTIO) – FROM SQI MODE CS 0 1 SIO0 1 1 SIO1 1 1 SIO2 1 1 SIO3 1 1 SCK DS20005155C-page 18  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-Lead PDIP Example: XXXXXXXX T/XXXNNN YYWW 23A512 I/P e3 13F 2208 8-Lead SOIC (3.90 mm) Example: XXXXXXXT XXXXYYWW NNN 23A512I SN e3 2208 13F Example: 8-Lead TSSOP 3LAI XXXT YYWW NNN Part Number 23A512 23LC512 Note: 2208 13F 1st Line Marking Codes PDIP SOIC TSSOP 23A512 23A512 3AAT 23LC512 23LC512T 3LAT T = Temperature grade (I, E) Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) RoHS-compliant JEDEC® designator for Matte Tin (Sn) Note: For very small packages with no room for the RoHS-compliant JEDEC® designator e3, the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2012-2022 Microchip Technology Inc. and its subsidiaries DS20005155C-page 19 23A512/23LC512 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E A2 A C PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2 DS20005155C-page 20  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e 2 e 2 e e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness b1 Upper Lead Width b Lower Lead Width eB Overall Row Spacing § MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2  2012-2022 Microchip Technology Inc. and its subsidiaries DS20005155C-page 21 23A512/23LC512 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E 2X 0.10 C A–B 2X 0.10 C A–B NOTE 1 2 1 e NX b 0.25 B C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C 4X ș1 ș2 h R1 h R H L SEE VIEW C VIEW A–A c ș (L1) 4X ș1 VIEW C Microchip Technology Drawing No. C04-057-SN Rev H Sheet 1 of 2 DS20005155C-page 22  2012-2022 Microchip Technology Inc. and its subsidiaries 23A512/23LC512 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L Footprint L1 c Lead Thickness b Lead Width Lead Bend Radius R Lead Bend Radius R1 Foot Angle ș Mold Draft Angle ș1 Lead Angle ș2 MIN – 1.25 0.10 0.25 0.40 0.17 0.31 0.07 0.07 0° 5° 0° MILLIMETERS NOM 8 1.27 BSC – – – 6.00 BSC 3.90 BSC 4.90 BSC – – 1.04 REF – – – – – – – MAX 1.75 0.25 0.50 1.27 0.25 0.51 – – 8° 15° 8° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev H Sheet 2 of 2  2012-2022 Microchip Technology Inc. and its subsidiaries DS20005155C-page 23 23A512/23LC512 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 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