24AA02E48/24AA025E48/
24AA02E64/24AA025E64
2K I2C Serial EEPROMs with EUI-48™ or EUI-64™ Node Identity
Device Selection Table
VCC
Range
Max. Clock
Frequency
Temp. Ranges
Cascadable
Page Size
Node
Address
1.7V-5.5V
400 kHz(1)
I
No
8-Byte
EUI-48™
24AA025E48
1.7V-5.5V
400 kHz
(1)
I
Yes
16-Byte
EUI-48™
24AA02E64
1.7V-5.5V
400 kHz(1)
I
No
8-Byte
EUI-64™
1.7V-5.5V
(1)
I
Yes
16-Byte
EUI-64™
Part Number
24AA02E48
24AA025E64
Note 1:
400 kHz
100 kHz for VCC 4,000V
More than 1 Million Erase/Write Cycles
Data Retention >200 Years
Factory Programming Available
Available Packages:
- 8-lead SOIC and 5-lead SOT-23
(24AA02E48/24AA02E64)
- 8-lead SOIC and 6-lead SOT-23
(24AA025E48/24AA025E64)
RoHS Compliant
Available for Extended Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
2008-2018 Microchip Technology Inc.
Note:
24AA02XEXX is used in this document as
a generic part number for the
24AA02E48/24AA025E48/24AA02E64/2
4AA025E64 devices.
Packages (24AA02E48/24AA02E64)
SOT-23
SCL
1
Vss
2
SDA
3
SOIC
NC
5
4
Vcc
NC
1
8
VCC
NC
2
7
NC
NC
3
6
SCL
VSS
4
5
SDA
Packages (24AA025E48/24AA025E64)
SOT-23
SOIC
SCL
1
6
VCC
VSS
2
5
A0
SDA
3
4
A1
A0
1
8
VCC
A1
2
7
NC
A2
3
6
SCL
VSS
4
5
SDA
DS20002124H-page 1
24AA02E48/24AA025E48/24AA02E64/24AA025E64
Block Diagram
A0(1) A1(1) A2(1)
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
SDA SCL
VCC
VSS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
Note 1: Pins A0, A1 and A2 are not available on
the 24AA02E48/24AA02E64.
2008-2018 Microchip Technology Inc.
DS20002124H-page 2
24AA02E48/24AA025E48/24AA02E64/24AA025E64
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
Automotive (E):
DC CHARACTERISTICS
Param.
No.
D1
Symbol
Characteristic
VIH
High-Level Input Voltage
Low-Level Input Voltage
TA = -40°C to +85°C, VCC = +1.7V to +5.5V
TA = -40°C to +125°C, VCC = +1.7V to +5.5V
Min.
Typ.
Max.
Units
0.7 VCC
—
—
V
Conditions
—
—
0.3 VCC
V
0.05 VCC
—
—
V
Note
Low-Level Output Voltage
—
—
0.40
V
IOL = 3.0 mA, VCC = 2.5V
ILI
Input Leakage Current
—
—
±1
µA
VIN = VSS or VCC
D6
ILO
Output Leakage Current
—
—
±1
µA
VOUT = VSS or VCC
D7
CIN,
COUT
Pin Capacitance
(all inputs/outputs)
—
—
10
pF
VCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
D8
ICCWRITE Operating Current
—
0.1
3
mA
VCC = 5.5V, SCL = 400 kHz
D9
ICCREAD
D10
ICCS
D2
VIL
D3
VHYS
D4
VOL
D5
Note:
Hysteresis of Schmitt
Trigger Inputs
Standby Current
—
0.05
1
mA
—
0.01
1
µA
Industrial (I)
SDA = SCL = VCC
—
0.01
5
µA
Automotive (E)
SDA = SCL = VCC
This parameter is periodically sampled and not 100% tested.
2008-2018 Microchip Technology Inc.
DS20002124H-page 3
24AA02E48/24AA025E48/24AA02E64/24AA025E64
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
Automotive (E):
AC CHARACTERISTICS
Param.
Symbol
No.
1
FCLK
2
THIGH
3
TLOW
4
TR
5
TF
Characteristic
Clock Frequency
Clock High Time
Clock Low Time
SDA and SCL Rise Time
(Note 1)
SDA and SCL Fall Time
6
THD:STA Start Condition Hold Time
7
TSU:STA
8
THD:DAT Data Input Hold Time
9
TSU:DAT Data Input Setup Time
Start Condition Setup Time
11
TAA
12
TBUF
13
TOF
Typ.
Max.
Units
—
—
400
kHz
2.5V VCC 5.5V
—
—
100
kHz
1.7V VCC 2.5V
600
—
—
ns
2.5V VCC 5.5V
4000
—
—
ns
1.7V VCC 2.5V
1300
—
—
ns
2.5V VCC 5.5V
4700
—
—
ns
1.7V VCC 2.5V
—
—
300
ns
2.5V VCC 5.5V (Note 1)
—
—
1000
ns
1.7V VCC 2.5V (Note 1)
—
—
300
ns
Note 1
600
—
—
ns
2.5V VCC 5.5V
4000
—
—
ns
1.7V VCC 2.5V
600
—
—
ns
2.5V VCC 5.5V
4700
—
—
ns
1.7V VCC 2.5V
0
—
—
ns
Note 2
100
—
—
ns
2.5V VCC 5.5V
250
—
—
ns
1.7V VCC 2.5V
600
—
—
ns
2.5V VCC 5.5V
—
—
ns
1.7V VCC 2.5V
—
—
900
ns
2.5V VCC 5.5V
—
—
3500
ns
1.7V VCC 2.5V
Bus Free Time: Bus time
must be free before a new
transmission can start
1300
—
—
ns
2.5V VCC 5.5V
4700
—
—
ns
1.7V VCC 2.5V
Output Fall Time from VIH
Minimum to VIL Maximum
—
—
250
ns
2.5V VCC 5.5V
—
—
250
ns
1.7V VCC 2.5V
Notes 1 and 3
Output Valid from Clock
(Note 2)
14
TSP
Input Filter Spike
Suppression
(SDA and SCL pins)
—
—
50
ns
15
TWC
Write Cycle Time (byte or
page)
—
—
5
ms
Endurance
1M
—
—
16
Note 1:
2:
3:
4:
Conditions
4000
TSU:STO Stop Condition Setup Time
10
Min.
TA = -40°C to +85°C, VCC = +1.7V to +5.5V
TA = -40°C to +125°C, VCC = +1.7V to +5.5V
cycles 25°C (Note 4)
= total capacitance of one bus line in pF.
Not 100% tested.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
CB
2008-2018 Microchip Technology Inc.
DS20002124H-page 4
24AA02E48/24AA025E48/24AA02E64/24AA025E64
FIGURE 1-1:
BUS TIMING DATA
5
4
2
3
SCL
7
SDA
In
8
10
9
6
14
12
11
SDA
Out
FIGURE 1-2:
BUS TIMING START/STOP
D3
SCL
6
7
10
SDA
Start
2008-2018 Microchip Technology Inc.
Stop
DS20002124H-page 5
24AA02E48/24AA025E48/24AA02E64/24AA025E64
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
SOIC
5-Pin SOT-23
6-Pin SOT-23
A0
1
—
5
Chip Address Input(1)
A1
2
—
4
Chip Address Input(1)
A2
3
—
—
Chip Address Input(1)
VSS
4
2
2
Ground
Description
SDA
5
3
3
Serial Address/Data I/O
SCL
6
1
1
Serial Clock
NC
7
5
—
Not Connected
VCC
8
4
6
+1.7V to 5.5V Power Supply
Note 1:
2.1
PIN FUNCTION TABLE
Chip address inputs A0, A1 and A2 are not connected on the 24AA02E48/24AA02E64.
Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an
open-drain terminal, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.2
Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.3
A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 pins are not used by the
24AA02E48/24AA02E64. They may be left floating or
tied to either VSS or VCC.
For the 24AA025E48/24AA025E64, the levels on the
A0, A1 and A2 inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true. For the 6-lead SOT-23
package, pin A2 is not connected and its corresponding
bit in the slave address should always be set to ‘0’.
Up to eight 24AA025E48/24AA025E64 devices (four
for the SOT-23 package) may be connected to the
same bus by using different Chip Select bit
combinations. These inputs must be connected to
either VSS or VCC.
2008-2018 Microchip Technology Inc.
DS20002124H-page 6
24AA02E48/24AA025E48/24AA02E64/24AA025E64
3.0
FUNCTIONAL DESCRIPTION
The 24AA02XEXX supports a bidirectional, 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, while a
device receiving data is defined as a receiver. The bus
has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access
and generates the Start and Stop conditions, while the
24AA02XEXX works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 4-1:
(A)
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
4.4
The 24AA02XEXX does not generate any
Acknowledge bits
if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24AA02XEXX) will leave the
data line high to enable the master to generate the Stop
condition.
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SCL
SDA
2008-2018 Microchip Technology Inc.
Data
Allowed
to Change
Stop
Condition
DS20002124H-page 7
24AA02E48/24AA025E48/24AA02E64/24AA025E64
5.0
DEVICE ADDRESSING
FIGURE 5-1:
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists of a four-bit control code. For the
24AA02XEXX, this is set as ‘1010’ binary for read and
write operations. For the 24AA02E48/24AA02E64 the
next three bits of the control byte are “don’t cares”.
For the 24AA025E48/24AA025E64, the next three bits
of the control byte are the Chip Select bits (A2, A1, A0).
The Chip Select bits allow the use of up to eight
24AA025E48/24AA025E64 devices on the same bus
and are used to select which device is accessed. The
Chip Select bits in the control byte must correspond to
the logic levels on the corresponding A2, A1 and A0
pins for the device to respond. These bits are in effect
the three Most Significant bits of the word address.
CONTROL BYTE
ALLOCATION
Read/Write Bit
Chip
Select
Bits
Control Code
S
1
0
1
0
A2* A1* A0* R/W ACK
Slave Address
Acknowledge Bit
Start Bit
Note:
* Bits A0, A1 and A2 are “don’t cares” for
the 24AA02E48/24AA02E64.
For the 6-pin SOT-23 package, the A2 address pin is
not available. During device addressing, the A2 Chip
Select bit should be set to ‘0’.
5.1
The last bit of the control byte defines the operation to
be performed. When set to ‘1’, a read operation is
selected. When set to ‘0’, a write operation is selected.
Following the Start condition, the 24AA02XEXX monitors the SDA bus, checking the device type identifier
being transmitted and, upon a ‘1010’ code, the slave
device outputs an Acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the
24AA02XEXX will select a read or write operation.
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 24AA025E48/24AA025E64
devices on the same bus. In this case, software can
use A0 of the control byte as address bit A8, A1 as
address bit A9 and A2 as address bit A10. It is not
possible to sequentially read across device
boundaries.
Operation
Control
Code
Chip Select
R/W
Read
1010
Chip Address
1
Write
1010
Chip Address
0
FIGURE 5-2:
Contiguous Addressing Across
Multiple Devices
For
the
SOT-23
package,
up
to
four
24AA025E48/24AA025E64 devices can be added for
up to 8K bits of address space. In this case, software
can us A0 of the control byte as address bit A8, and
A1 as address bit A9. It is not possible to sequentially
read across device boundaries.
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
1
0
1
0 A2* A1* A0* R/W
Control
Code
Note:
Address Low Byte
A
7
•
•
•
•
•
•
A
0
Chip
Select
bits
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
2008-2018 Microchip Technology Inc.
DS20002124H-page 8
24AA02E48/24AA025E48/24AA02E64/24AA025E64
6.0
WRITE OPERATION
6.1
Byte Write
Following the Start condition from the master, the
device code (four bits), the chip address (three bits)
and the R/W bit which is a logic-low, is placed onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow once it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the word address and will be written into the Address
Pointer of the 24AA02XEXX. After receiving another
Acknowledge signal from the 24AA02XEXX, the
master device will transmit the data word to be written
into the addressed memory location. The
24AA02XEXX acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and, during this time, the 24AA02XEXX will
not generate Acknowledge signals (Figure 6-1).
6.2
The
higher-order
five
bits
(four
for
the
24AA025E48/24AA025E64) of the word address
remain constant. If the master should transmit more
than
eight
words
(16
for
the
24AA025E48/24AA025E64) prior to generating the
Stop condition, the address counter will roll over and the
previously received data will be overwritten. As with the
byte write operation, once the Stop condition is received
an internal write cycle will begin (Figure 6-2).
Note:
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA02XEXX in the same
way as in a byte write. However, instead of generating
a Stop condition, the master transmits up to eight data
bytes to the 24AA02XEXX, which are temporarily
stored in the on-chip page buffer and will be written into
memory once the master has transmitted a Stop
condition. Upon receipt of each word, the three
lower-order Address Pointer bits (four for the
24AA025E48/24AA025E64) are internally incremented
by one.
FIGURE 6-1:
Write Protection
The upper half of the array (80h-FFh) is permanently
write-protected. Write operations to this address range
are inhibited. Read operations are not affected.
The remaining half of the array (00h-7Fh) can be
written to and read from normally.
BYTE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
1
0
1
Word
Address
S
T
O
P
Data
0 A2* A1*A0* 0
Bus Activity
Note:
6.3
Page write operations are limited to
writing bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Chip
Select
Bits
P
A
C
K
A
C
K
A
C
K
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
2008-2018 Microchip Technology Inc.
DS20002124H-page 9
24AA02E48/24AA025E48/24AA02E64/24AA025E64
FIGURE 6-2:
PAGE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S 1 0 1 0 A2 A1 A0 0
Bus Activity
Note:
Control
Byte
Word
Address (n)
Data (n + 1)
Data (n)
S
T
O
P
Data (n + 7)
* * *
P
A
C
K
A
C
K
Chip
Select
Bits
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
2008-2018 Microchip Technology Inc.
A
C
K
A
C
K
A
C
K
DS20002124H-page 10
24AA02E48/24AA025E48/24AA02E64/24AA025E64
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally timed write cycle and ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a write command (R/W = 0). If the device is still
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next read or write
command. See Figure 7-1 for a flow diagram of this
operation.
FIGURE 7-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
2008-2018 Microchip Technology Inc.
DS20002124H-page 11
24AA02E48/24AA025E48/24AA02E64/24AA025E64
8.0
READ OPERATION
8.3
Sequential Read
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
Sequential reads are initiated in the same way as a
random read, except that once the 24AA02XEXX
transmits the first data byte, the master issues an
acknowledge as opposed to a Stop condition in a
random read. This directs the 24AA02XEXX to transmit
the next sequentially addressed 8-bit word (Figure 8-3).
8.1
To provide sequential reads, the 24AA02XEXX
contains an internal Address Pointer that is
incremented by one upon completion of each operation. This Address Pointer allows the entire memory
contents to be serially read during one operation.
Current Address Read
The 24AA02XEXX contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address ‘n’, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to ‘1’, the
24AA02XEXX issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer, but generate a Stop condition, and the
24AA02XEXX discontinues transmission (Figure 8-1).
8.2
8.4
Noise Protection
The 24AA02XEXX employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24AA02XEXX as part of a write
operation. Once the word address is sent, the master
generates a Start condition following the acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a ‘1’.
The 24AA02XEXX will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but generate a Stop
condition, and the 24AA02XEXX will discontinue
transmission (Figure 8-2).
FIGURE 8-1:
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
SDA Line
S 1
Bus Activity
Note:
Control
Byte
0
1
S
T
O
P
Data (n)
0 A2* A1*A0* 1
Chip
Select
Bits
P
A
C
K
N
o
A
C
K
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
2008-2018 Microchip Technology Inc.
DS20002124H-page 12
24AA02E48/24AA025E48/24AA02E64/24AA025E64
FIGURE 8-2:
RANDOM READ
Bus Activity
Master
S
T
A
R
T
S
T
A
R
T
Word
Address (n)
Control
Byte
* * *
Chip
Select
Bits
Bus Activity
Note:
FIGURE 8-3:
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Data (n)
* **
S 1 0 1 0 A2A1A0 0
SDA Line
Control
Byte
S 1 0 1 0 A2A1A0 1
A
C
K
A
C
K
Chip
Select
Bits
P
A
C
K
N
o
A
C
K
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + x)
P
1
A
C
K
A
C
K
A
C
K
A
C
K
N
o
A
C
K
2008-2018 Microchip Technology Inc.
DS20002124H-page 13
24AA02E48/24AA025E48/24AA02E64/24AA025E64
9.0
PRE-PROGRAMMED EUI-48™
OR EUI-64™ NODE ADDRESS
The 24AA02XEXX is programmed at the factory with a
globally unique node address stored in the upper half
of the array and permanently write-protected. The
remaining 1,024 bits are available for application use.
FIGURE 9-1:
MEMORY ORGANIZATION
9.1.1
ORGANIZATIONALLY UNIQUE
IDENTIFIERS (OUIs)
Each OUI provides roughly 16M (224) addresses. Once
the address pool for an OUI is exhausted, Microchip
will acquire a new OUI from IEEE to use for
programming this model. For more information on past
and current OUIs see “Organizationally Unique
Identifiers For Preprogrammed EUI-48 and EUI-64
Address Devices” Technical Brief (DS90003187).
00h
Note:
Standard
EEPROM
80h
Write-Protected
Node Address Block
9.1.2
FFh
9.1
EUI-48™ Node Address
(24AAXXXE48)
The 6-byte EUI-48™ node address value of the
24AAXXXE48 is stored in array locations 0xFA through
0xFF, as shown in Figure 9-2. The first three bytes are
the Organizationally Unique Identifier (OUI) assigned
to Microchip by the IEEE Registration Authority. The
remaining three bytes are the Extension Identifier, and
are generated by Microchip to ensure a globally
unique, 48-bit value.
FIGURE 9-2:
Description
The OUI will change as addresses are
exhausted. Customers are not guaranteed to receive a specific OUI and should
design their application to accept new
OUIs as they are introduced.
EUI-64™ SUPPORT USING THE
24AAXXXE48
The pre-programmed EUI-48 node address of the
24AAXXXE48 can easily be encapsulated at the
application level to form a globally unique, 64-bit node
address for systems utilizing the EUI-64 standard. This
is done by adding 0xFFFE between the OUI and the
Extension Identifier, as shown below.
Note:
As an alternative, the 24AAXXXE64
features an EUI-64 node address that can
be used in EUI-64 applications directly
without the need for encapsulation,
thereby simplifying system software. See
Section 9.2 “EUI-64™ Node Address
(24AAXXXE64)” for details.
EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (24AAXXXE48)
24-bit Extension
Identifier
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
FAh
04h
A3h
12h
34h
56h
FFh
Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56
Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56
2008-2018 Microchip Technology Inc.
DS20002124H-page 14
24AA02E48/24AA025E48/24AA02E64/24AA025E64
EUI-64™ Node Address
(24AAXXXE64)
9.2
The 8-byte EUI-64™ node address value of the
24AAXXXE64 is stored in array locations 0xF8 through
0xFF, as shown in Figure 9-3. The first three bytes are
the Organizationally Unique Identifier (OUI) assigned
to Microchip by the IEEE Registration Authority. The
remaining five bytes are the Extension Identifier, and
are generated by Microchip to ensure a globally
unique, 64-bit value.
Note:
In conformance with IEEE guidelines,
Microchip will not use the values 0xFFFE
and 0xFFFF for the first two bytes of the
EUI-64 Extension Identifier. These two
values are specifically reserved to allow
applications to encapsulate EUI-48
addresses into EUI-64 addresses.
FIGURE 9-3:
Description
EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (24AAXXXE64)
40-bit Extension
Identifier
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
F8h
04h
A3h
12h
34h
56h
78h
90h
FFh
Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90
2008-2018 Microchip Technology Inc.
DS20002124H-page 15
24AA02E48/24AA025E48/24AA02E64/24AA025E64
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
8-Lead SOIC (3.90 mm)
Example
XXXXXXXT
XXXXYYWW
NNN
24A2E48I
SN e31625
13F
5-Lead SOT-23 (1-Line Marking)
Example
XXNN
2K3F
6-Lead SOT-23 (1-Line Marking)
Example
XXNN
HS3F
5-Lead SOT-23 (2-Line Marking)
Example
XXXXY
WWNNN
AAAB6
251L7
6-Lead SOT-23 (2-Line Marking)
Example
XXXXY
WWNNN
AAAC6
251L7
1st Line Marking Code
Part Number
SOT-23
I-Temp.
SOIC
E-Temp.
I-Temp.
E-Temp.
(1,2)
AABLY(3)
24A2E48I
24A2E48E
24AA025E48
(1,2)
HSNN
AABMY(3)
4A25E48I
4A25E48E
24AA02E64
AAABY(3)
AABNY(3)
24A2E64I
24A2E64E
24AA025E64
AAACY(3)
AABPY(3)
4A25E64I
4A25E64E
24AA02E48
Note 1:
2:
3:
2KNN
NN = Alphanumeric traceability code
These parts use the 1-line SOT-23 marking format
These parts use the 2-line SOT-23 marking format
2008-2018 Microchip Technology Inc.
DS20002124H-page 16
24AA02E48/24AA025E48/24AA02E64/24AA025E64
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
*Standard OTP marking consists of Microchip part number, year code, week code, and
traceability code.
Note:
Note:
For very small packages with no room for the JEDEC® designator
e3 , the marking will only appear on the outer carton or reel label.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2008-2018 Microchip Technology Inc.
DS20002124H-page 17
24AA02E48/24AA025E48/24AA02E64/24AA025E64
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2
2008-2018 Microchip Technology Inc.
DS20002124H-page 18
24AA02E48/24AA025E48/24AA02E64/24AA025E64
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2
2008-2018 Microchip Technology Inc.
DS20002124H-page 19
24AA02E48/24AA025E48/24AA02E64/24AA025E64
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev B
2008-2018 Microchip Technology Inc.
DS20002124H-page 20
24AA02E48/24AA025E48/24AA02E64/24AA025E64
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A A2
0.20 C
SEATING PLANE
A
SEE SHEET 2
C
A1
SIDE VIEW
Microchip Technology Drawing C04-028D [OT] Sheet 1 of
2008-2018 Microchip Technology Inc.
DS20002124H-page 21
24AA02E48/24AA025E48/24AA02E64/24AA025E64
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
Dimension Limits
Number of Pins
N
e
Pitch
e1
Outside lead pitch
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
E
Overall Width
E1
Molded Package Width
D
Overall Length
L
Foot Length
Footprint
L1
I
Foot Angle
c
Lead Thickness
b
Lead Width
MIN
0.90
0.89
-
0.30
0°
0.08
0.20
MILLIMETERS
NOM
6
0.95 BSC
1.90 BSC
2.80 BSC
1.60 BSC
2.90 BSC
0.60 REF
-
MAX
1.45
1.30
0.15
0.60
10°
0.26
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091D [OT] Sheet 2 of
2008-2018 Microchip Technology Inc.
DS20002124H-page 22
24AA02E48/24AA025E48/24AA02E64/24AA025E64
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
C
Contact Pad Spacing
X
Contact Pad Width (X5)
Contact Pad Length (X5)
Y
Distance Between Pads
G
Distance Between Pads
GX
Overall Width
Z
MIN
MILLIMETERS
NOM
0.95 BSC
2.80
MAX
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091A [OT]
2008-2018 Microchip Technology Inc.
DS20002124H-page 23
24AA02E48/24AA025E48/24AA02E64/24AA025E64
6-Lead Plastic Small Outline Transistor (OT, OTY) [SOT-23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.15 C A-B
D
e1
A
D
E
2
E1
E
E1
2
2X
0.15 C D
2X
0.20 C A-B
e
6X b
B
0.20
C A-B D
TOP VIEW
C
A
A2
SEATING PLANE
6X
A1
0.10 C
SIDE VIEW
R1
L2
R
c
GAUGE PLANE
L
Ĭ
(L1)
END VIEW
Microchip Technology Drawing C04-028C (OT) Sheet 1 of 2
2008-2018 Microchip Technology Inc.
DS20002124H-page 24
24AA02E48/24AA025E48/24AA02E64/24AA025E64
6-Lead Plastic Small Outline Transistor (OT, OTY) [SOT-23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Leads
e
Pitch
Outside lead pitch
e1
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Foot Length
L
Footprint
L1
Seating Plane to Gauge Plane
L1
φ
Foot Angle
c
Lead Thickness
Lead Width
b
MIN
0.90
0.89
0.00
0.30
0°
0.08
0.20
MILLIMETERS
NOM
6
0.95 BSC
1.90 BSC
1.15
2.80 BSC
1.60 BSC
2.90 BSC
0.45
0.60 REF
0.25 BSC
-
MAX
1.45
1.30
0.15
0.60
10°
0.26
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-028C (OT) Sheet 2 of 2
2008-2018 Microchip Technology Inc.
DS20002124H-page 25
24AA02E48/24AA025E48/24AA02E64/24AA025E64
6-Lead Plastic Small Outline Transistor (OT, OTY) [SOT-23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
GX
Y
Z
C G
G
SILK SCREEN
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
C
Contact Pad Spacing
X
Contact Pad Width (X3)
Y
Contact Pad Length (X3)
G
Distance Between Pads
Distance Between Pads
GX
Z
Overall Width
MIN
MILLIMETERS
NOM
0.95 BSC
2.80
MAX
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2028B (OT)
2008-2018 Microchip Technology Inc.
DS20002124H-page 26
24AA02E48/24AA025E48/24AA02E64/24AA025E64
APPENDIX A:
REVISION HISTORY
Revision A (12/08)
Initial release of this document.
Revision B (01/09)
Removed preliminary status.
Revision C (03/10)
Added new sections 2.0 through 9.0.
Revision D (05/10)
Added 24AA025E48 part number and 6-lead SOT-23
package.
Revision E (04/13)
Added 24AA02E64 and 24AA025E64 part numbers.
Revision F (10/14)
Added E-temp. option to part numbers.
Revision G (08/16)
Added new OUI (54-10-EC) to list.
Revision H (02/18)
Added detailed description of OUIs.
2008-2018 Microchip Technology Inc.
DS20002124H-page 27
24AA02E48/24AA025E48/24AA02E64/24AA025E64
NOTES:
2008-2018 Microchip Technology Inc.
DS20002124H-page 28
24AA02E48/24AA025E48/24AA02E64/24AA025E64
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the website
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2008-2016 Microchip Technology Inc.
DS20002124H-page 29
24AA02E48/24AA025E48/24AA02E64/24AA025E64
NOTES:
2008-2016 Microchip Technology Inc.
DS20002124H-page 30
24AA02E48/24AA025E48/24AA02E64/24AA025E64
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
(1)
X
/XX
[X]
PART NO.
a) 24AA02E48-I/SN:
2 Kbit,
8-byte
page,
Serial EEPROM with
Temperature Package
Device
Tape and Reel
EUI-48 Node Identity,
Range
Option
1.7V, Industrial Temperature, SOIC package.
2
Device:
24AA02E48
= 1.7V, 2 Kbit I C Serial EEPROM
b) 24AA02E48T-I/OT: 2 Kbit,
8-byte
page,
with EUI-48™ Node Identity
Serial EEPROM with
24AA025E48 = 1.7V, 2 Kbit I2C Serial EEPROM with
EUI-48 Node Identity,
EUI-48™ Node Identity and Address
1.7V, Tape and Reel,
Pins
Industrial Temperature,
24AA02E64
= 1.7V, 2 Kbit I2C Serial EEPROM
SOT-23 package.
with EUI-64™ Node Identity
c) 24AA025E48-I/SN: 2 Kbit, 16-byte page,
24AA025E64 = 1.7V, 2 Kbit I2C Serial EEPROM with
Serial EEPROM with
EUI-64™ Node Identity and Address
EUI-48 Node Identity, X,
Pins
1.7V, Cascadable, Industrial Temperature, SOIC
Tape and
Blank = Standard packaging (tube or tray)
package.
Reel Option: T
= Tape and Reel(1)
d) 24AA02E64-I/SN:
2 Kbit,
8-byte
page,
Serial EEPROM with
EUI-64 Node Identity,
Temperature I
= -40°C to +85°C
1.7V, Industrial TemperaRange:
E
= -40°C to +125°C
ture, SOIC package.
e) 24AA02E64T-I/OT: 2 Kbit,
8-byte
page,
Package:
SN
= Plastic SOIC (3.90 mm body), 8-lead
Serial EEPROM with
OT
= SOT-23 (Tape and Reel only)
EUI-64 Node Identity,
1.7V, Tape and Reel,
Industrial Temperature,
SOT-23 package.
f) 24AA025E64-I/SN: 2 Kbit, 16-byte page,
Serial EEPROM with
EUI-64 Node Identity,
1.7V, Cascadable, Industrial Temperature, SOIC
package.
g) 24AA025E48T-E/SN: 2 Kbit, 16-byte page,
Serial EEPROM with
EUI-48 Node Identity,
1.7V, Cascadable, Tape
and Reel, Automotive
Temperature, SOIC package.
h) 24AA02E48-E/SN: 2 Kbit,
8-byte
page,
Serial EEPROM with
EUI-48 Node Identity,
1.7V, Automotive Temperature, SOIC package.
i) 24AA025E48T-E/OT: 2 Kbit, 16-byte page,
Serial EEPROM with EUI48 Node Identity, 1.7V,
Cascadable, Tape and
Reel, Automotive Temperature, SOT-23 package.
Note 1:
2008-2018 Microchip Technology Inc.
Tape and Reel identifier only appears in
the catalog part number description.
This identifier is used for ordering purposes and is not printed on the device
package. Check with your Microchip
Sales Office for package availability
with the Tape and Reel option.
DS20002124H-page 31
24AA02E48/24AA025E48/24AA02E64/24AA025E64
NOTES:
2008-2018 Microchip Technology Inc.
DS20002124H-page 32
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, InterChip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,
RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
© 2008-2018, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-2735-3
== ISO/TS 16949 ==
2008-2018 Microchip Technology Inc.
DS20002124H-page 33
Worldwide Sales and Service
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2008-2018 Microchip Technology Inc.
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DS20002124H-page 34
10/25/17