24AA02HT-I/MS

24AA02H/24LC02BH 2K I2C Serial EEPROM with Half-Array Write-Protect Device Selection Table Part Number VCC Range 24AA02H 1.7-5.5 24LC02BH 2.5-5.5 Note 1: Max. Clock Frequency 400 Temp. Ranges Available Packages I LT, MNY, MS, OT, P, SN, ST I, E LT, MNY, MS, OT, P, SN, ST kHz(1) 400 kHz 100 kHz for VCC 4,000V • More than 1 Million Erase/Write Cycles • Data Retention >200 Years • Factory Programming Available • RoHS Compliant • Temperature Ranges: - Industrial (I): -40°C to +85°C - Extended (E): -40°C to +125°C • Automotive AEC-Q100 Qualified The Microchip Technology Inc. 24XX02H(1) is a 2 Kbit Electrically Erasable PROM (EEPROM). The device is organized as one block of 256 x 8-bit memory with a two-wire serial interface. Its low-voltage design permits operation down to 1.7V with standby and active currents of only 1 A and 1 mA, respectively. The 24XX02H also has a page write capability for up to 8 bytes of data. Packages • 8-Lead MSOP, 8-Lead PDIP, 8-Lead SOIC, 8-Lead TDFN, 8-Lead TSSOP, 5-Lead SC70 and 5-Lead SOT-23  2008-2021 Microchip Technology Inc. Note 1: 24XX02H is used in this document as a generic part number for the 24AA02H/ 24LC02BH devices. Package Types SOIC, TSSOP PDIP, MSOP A0 1 8 VCC A0 1 8 VCC A1 2 7 WP A1 2 7 WP A2 3 6 SCL A2 3 6 SCL VSS 4 5 SDA VSS 4 5 SDA SOT-23/SC-70 SCL 1 Vss 2 SDA 3 Note: 5 TDFN WP A0 1 A1 2 4 Vcc A2 3 VSS 4 8 VCC 7 WP 6 SCL 5 SDA Pins A0, A1 and A2 are not used by the 24XX02H (no internal connections). DS20002105B-page 1 24AA02H/24LC02BH Block Diagram HV Generator WP I/O Control Logic Memory Control Logic XDEC EEPROM Array Page Latches I/O SCL YDEC SDA VCC VSS  2008-2021 Microchip Technology Inc. Sense Amp. R/W Control DS20002105B-page 2 24AA02H/24LC02BH 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V Storage temperature ............................................................................................................................... -65°C to +150°C Ambient temperature with power applied................................................................................................ -40°C to +125°C ESD protection on all pins  4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. Symbol No. Characteristic D1 — A0, A1, A2, SCL, SDA and WP pins: D2 VIH High-level input voltage D3 VIL Low-level input voltage D4 VHYS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) D5 VOL Low-level output voltage D6 ILI Input leakage current D7 ILO Output leakage current D8 CIN, COUT Pin capacitance (all inputs/outputs) D9 D10 Note: Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V Extended (E): VCC = +2.5V to 5.5V Min. Max. Units — — — — 0.7 x VCC — V — TA = -40°C to +85°C TA = -40°C to +125°C Conditions — 0.3 x VCC V — 0.05 X VCC — V (Note) — 0.40 V IOL = 3.0 ma @ VCC = 4.5V IOL = 2.1 ma @ VCC = 2.5V — ±1 A VIN = VSS or VCC, WP = VSS — ±1 A VOUT = VSS or VCC — 10 pF VCC = 5.0V (Note) TA = 25°C, f = 1 MHz ICC Read Operating current — 1 mA VCC = 5.5V, SCL = 400 kHz ICC Write — 3 mA VCC = 5.5V — 1 A VCC = 5.5V, SCL = SDA = VCC WP = VSS, A0, A1, A2 = VSS ICCS Standby current This parameter is periodically sampled and not 100% tested.  2008-2021 Microchip Technology Inc. DS20002105B-page 3 24AA02H/24LC02BH TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V Extended (E): VCC = +2.5V to 5.5V AC CHARACTERISTICS Param. Symbol No. Characteristic Min. Max. Units TA = -40°C to +85°C TA = -40°C to +125°C Conditions 1 FCLK Clock frequency — — 100 400 kHz kHz 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 2 THIGH Clock high time 4000 600 — — ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 3 TLOW Clock low time 4700 1300 — — ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 4 TR SDA and SCL rise time (Note 1) — — 1000 300 ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 5 TF SDA and SCL fall time (Note 1) — — 1000 300 ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 6 THD:STA Start condition hold time 4000 600 — — ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 7 TSU:STA Start condition setup time 4700 600 — — ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 8 THD:DAT Data input hold time 0 — ns (Note 2) 9 TSU:DAT 250 100 — — ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 10 TSU:STO Stop condition setup time 4000 600 — — ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 11 TSU:WP WP setup time 4000 600 — — ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 12 THD:WP WP hold time 4700 600 — — ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 13 TAA Output valid from clock (Note 2) — — 3500 900 ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 1300 4700 — — ns ns 1.7V  VCC < 2.5V 2.5V  VCC  5.5V 16 TSP Input filter spike suppression (SDA and SCL pins) — 50 ns (Note 1 and Note 3) 17 TWC Write cycle time (byte or page) — 5 ms — 18 — Endurance 1,000,000 — cycles Data input setup time 25°C, VCC = 5.5V, Page mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization.  2008-2021 Microchip Technology Inc. DS20002105B-page 4 24AA02H/24LC02BH FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA In 3 4 D4 2 8 10 9 6 16 14 13 SDA Out WP  2008-2021 Microchip Technology Inc. (protected) (unprotected) 11 12 DS20002105B-page 5 24AA02H/24LC02BH 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Name PDIP SOIC TSSOP TDFN MSOP SOT23 SC-70 Description A0 1 1 1 1 1 — — Not Connected A1 2 2 2 2 2 — — Not Connected A2 3 3 3 3 3 — — Not Connected VSS 4 4 4 4 4 2 2 Ground SDA 5 5 5 5 5 3 3 Serial Address/Data I/O SCL 6 6 6 6 6 1 1 Serial Clock WP 7 7 7 7 7 5 5 Write-Protect Input VCC 8 8 8 8 8 4 4 Power Supply Note: 2.1 The exposed pad on the TDFN package can be connected to VSS or left floating. A0, A1, A2 The A0, A1 and A2 pins are not used by the 24XX02H. They may be left floating or tied to either VSS or VCC. 2.2 Serial Address/Data Input/Output (SDA) SDA is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an opendrain terminal, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz). 2.4 Write-Protect (WP) The WP pin must be connected to either VSS or VCC. If tied to VSS, normal memory operation is enabled (read/write the entire memory 00-FF). If tied to VCC, write operations are inhibited. Half of the memory will be write-protected (80h-FFh). Read operations are not affected. For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating Start and Stop conditions. 2.3 Serial Clock (SCL) The SCL input is used to synchronize the data transfer to and from the device.  2008-2021 Microchip Technology Inc. DS20002105B-page 6 24AA02H/24LC02BH 3.0 FUNCTIONAL DESCRIPTION The 24XX02H supports a bidirectional, two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a host device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX02H works as client. Both host and client can operate as transmitter or receiver, but the host device determines which mode is activated. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between Start and Stop conditions is determined by the host device and is, theoretically, unlimited (although only the last eight will be stored when doing a write operation). When an overwrite does occur, it will replace data in a First-In-First-Out (FIFO) principle. 4.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The host device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: Bus Not Busy (A) Both data and clock lines remain high. 4.2 4.4 The 24XX02H does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the acknowledge-related clock pulse. Moreover, setup and hold times must be taken into account. During reads, a host must signal an end of data to the client by not generating an Acknowledge bit on the last byte that has been clocked out of the client. In this case, the client (24XX02H) will leave the data line high to enable the host to generate the Stop condition. A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. FIGURE 4-1: (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA  2008-2021 Microchip Technology Inc. Data Allowed to Change Stop Condition DS20002105B-page 7 24AA02H/24LC02BH 5.0 DEVICE ADDRESSING A control byte is the first byte received following the Start condition from the host device. The control byte consists of a four-bit control code. For the 24XX02H, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are “don’t cares” for the 24XX02H. The combination of the 4-bit control code and the next three bits are called the client address. The last bit of the control byte is the Read/Write (R/W) bit and it defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’, a write operation is selected. Following the Start condition, the 24XX02H monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving a valid client address and the R/W bit, the client device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX02H will select a read or write operation. The next byte received defines the address of the first data byte within the selected block (Figure 5-2). The word address byte uses all eight bits. FIGURE 5-2: Operation Control Code Block Select R/W Read 1010 Block Address 1 1010 Block Address 0 Write FIGURE 5-1: CONTROL BYTE ALLOCATION Read/Write Bit Block Select Bits Control Code S 1 0 1 0 x x x R/W ACK Client Address Acknowledge Bit Start Bit x = “don’t care” ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte 1 0 1 Control Code 0 x x Word Address Byte x R/W A7 • • • • • • A0 Block Select Bits x = “don’t care”  2008-2021 Microchip Technology Inc. DS20002105B-page 8 24AA02H/24LC02BH 6.0 WRITE OPERATION 6.1 Byte Write 6.2 Following the Start condition from the host, the device code (4 bits), the block address (3 bits, “don’t cares”) and the R/W bit which is a logic low, is placed onto the bus by the host transmitter. This indicates to the addressed client receiver that a byte with a word address will follow once it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the host is the word address and will be written into the Address Pointer of the 24XX02H. After receiving another Acknowledge signal from the 24XX02H, the host device will transmit the data word to be written into the addressed memory location. The 24XX02H acknowledges again and the host generates a Stop condition. This initiates the internal write cycle and, during this time, the 24XX02H will not generate Acknowledge signals (Figure 6-1). Page Write The write-control byte, word address and the first data byte are transmitted to the 24XX02H in the same way as in a byte write. However, instead of generating a Stop condition, the host transmits up to eight data bytes to the 24XX02H, which are temporarily stored in the onchip page buffer and will be written into memory once the host has transmitted a Stop condition. Upon receipt of each word, the four lower-order Address Pointer bits, which form the byte counter, are internally incremented by one. The higher-order five bits of the word address remain constant. If the host should transmit more than eight words prior to generating the Stop condition, the Address Pointer will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 6-2). Note: 6.3 Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page-size’) and end at addresses that are integer multiples of page size – 1. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Write Protection The WP pin allows the user to write-protect half of the array (80h-FFh) when the pin is tied to VCC. If the pin is tied to VSS, the write protection is disabled. FIGURE 6-1: BYTE WRITE Bus Activity Host S T A R T SDA Line S Control Byte 1 0 1 0 Bus Activity x = “don’t care”  2008-2021 Microchip Technology Inc. x Word Address x x Block Select Bits S T O P Data 0 P A C K A C K A C K DS20002105B-page 9 24AA02H/24LC02BH FIGURE 6-2: PAGE WRITE Bus Activity Host S T A R T SDA Line S 10 1 0 xx x0 Bus Activity x = don’t care Control Byte Block Select Bits  2008-2021 Microchip Technology Inc. Word Address (n) Data (n) S T O P Data (n + 7) Data (n + 1) P A C K A C K A C K A C K A C K DS20002105B-page 10 24AA02H/24LC02BH 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the host, the device initiates the internally-timed write cycle and ACK polling can then be initiated immediately. This involves the host sending a Start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, no ACK will be returned. If the cycle is complete, the device will return the ACK and the host can then proceed with the next read or write operation. See Figure 7-1 for a flow diagram of this operation. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation  2008-2021 Microchip Technology Inc. DS20002105B-page 11 24AA02H/24LC02BH 8.0 READ OPERATION 8.3 Sequential Read Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the client address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. Sequential reads are initiated in the same way as a random read, except that once the 24XX02H transmits the first data byte, the host issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24XX02H to transmit the next sequentiallyaddressed 8-bit word (Figure 8-3). 8.1 To provide sequential reads, the 24XX02H contains an internal Address Pointer that is incremented by one upon completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. Current Address Read The 24XX02H contains an Address Pointer that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the client address with R/W bit set to ‘1’, the 24XX02H issues an acknowledge and transmits the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition, and the 24XX02H discontinues transmission (Figure 8-1). 8.2 8.4 Noise Protection The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. Random Read Random read operations allow the host to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24XX02H as part of a write operation. Once the word address is sent, the host generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The host then issues the control byte again, but with the R/W bit set to a ‘1’. The 24XX02H will then issue an acknowledge and transmit the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition, and the 24XX02H will discontinue transmission (Figure 8-2). FIGURE 8-1: CURRENT ADDRESS READ Bus Activity Host S T A R T SDA Line S 1 Bus Activity x = “don’t care”  2008-2021 Microchip Technology Inc. Control Byte 0 1 0 x x S T O P Data (n) x Block Select Bits 1 P A C K N o A C K DS20002105B-page 12 24AA02H/24LC02BH FIGURE 8-2: RANDOM READ Bus Activity Host S T A R T Control Byte S T A R T Word Address (n) S 10 10x xx0 SDA Line Block Select Bits Bus Activity Control Byte S 1 01 0x xx 1 A C K A C K Block Select Bits P A C K x = “don’t care” FIGURE 8-3: Bus Activity Host SDA Line Bus Activity S T O P Data (n) N o A C K SEQUENTIAL READ Control Byte Data (n) Data (n + 1) Data (n + 2) S T O P Data (n + x) P 1 A C K  2008-2021 Microchip Technology Inc. A C K A C K A C K N o A C K DS20002105B-page 13 24AA02H/24LC02BH 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC (3.90 mm) XXXXXXXT XXXXYYWW NNN 8-Lead TSSOP Example: 24LC02BH I/P e3 13F 0527 Example: 24LC02BHI SN e3 0527 13F Example: 4L2H I527 13F 8-Lead MSOP Example: 4L2BHI 13013F 5-Lead SOT-23 Example: 2Q3F 5-Lead SC-70 XXNN  2008-2021 Microchip Technology Inc. Example: C43F DS20002105B-page 14 24AA02H/24LC02BH Example: 8-Lead 2x3 TDFN AD4 527 13 XXX YWW NN 1st Line Marking Codes Part Number SOT-23 TDFN TSSOP MSOP 4A2H 4A02HT(1) 2MNN(2) — 4L2H 4L2BHT(1) 2QNN(2) 2RNN(2) 24AA02 24LC02B I Temp. E Temp. I Temp. AD1 AD4 SC-70 E Temp. I Temp. E Temp. — C5NN(2) — AD5 C4NN(2) C6NN(2) Note 1: T = Temperature grade (I, E) 2: NN = Alphanumeric traceability code Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) JEDEC® designator for Matte Tin (Sn) *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. Note: Note: For very small packages with no room for the JEDEC® designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2008-2021 Microchip Technology Inc. DS20002105B-page 15 24AA02H/24LC02BH 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2  2008-2021 Microchip Technology Inc. DS20002105B-page 16 24AA02H/24LC02BH 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e 2 e 2 e e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness b1 Upper Lead Width b Lower Lead Width eB Overall Row Spacing § MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2  2008-2021 Microchip Technology Inc. DS20002105B-page 17 24AA02H/24LC02BH 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E 2X 0.10 C A–B 2X 0.10 C A–B NOTE 1 2 1 e B NX b 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H SEE VIEW C VIEW A–A 0.23 L (L1) VIEW C Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2  2008-2021 Microchip Technology Inc. DS20002105B-page 18 24AA02H/24LC02BH 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L Footprint L1 Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2  2008-2021 Microchip Technology Inc. DS20002105B-page 19 24AA02H/24LC02BH 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev F  2008-2021 Microchip Technology Inc. DS20002105B-page 20 24AA02H/24LC02BH /HDG3ODVWLF7KLQ6KULQN6PDOO2XWOLQH67PP%RG\>76623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ' $ % 1 '$780$ '$780% ( (   & % $  ;E  H & % $ 7239,(: $  & & 6($7,1* 3/$1( $ $ $ ;  & $ 6,'(9,(: + F / / 9,(:$$ 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY&6KHHWRI  2008-2021 Microchip Technology Inc. DS20002105B-page 21 24AA02H/24LC02BH /HDG3ODVWLF7KLQ6KULQN6PDOO2XWOLQH67PP%RG\>76623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 1 H 3LWFK 2YHUDOO+HLJKW $ 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' )RRW/HQJWK / )RRWSULQW / F /HDG7KLFNQHVV )RRW$QJOH E /HDG:LGWK 0,1        ƒ  0,//,0(7(56 120  %6&    %6&    5()  ƒ  0$;        ƒ  Notes:  3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD  'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRU SURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH  'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(