24AA128/24LC128/24FC128
128K I2C Serial EEPROM
Device Selection Table
Part Number
VCC Range
24AA128
1.7V-5.5V
24LC128
2.5V-5.5V
24FC128
1.7V-5.5V
Note 1:
2:
Max. Clock Frequency Temp. Ranges
Available Packages
400 kHz(1)
I
400 kHz
I, E
SN, SM, ST, MF, MNY, MS, P
I
SN, SM, ST, MF, MNY, MS, P
1 MHz(2)
SN, SM, ST, MF, MNY, MS, P, CSP
100 kHz for VCC < 2.5V.
400 kHz for VCC < 2.5V.
Features
Packages
• Single Supply with Operation down to 1.7V for
24AA128/24FC128 devices, 2.5V for 24LC128
Devices
• Low-Power CMOS Technology:
- Write current 3 mA, maximum
- Standby current 1 µA, maximum (I-temp.)
• Two-Wire Serial Interface, I2C Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz, 400 kHz and 1 MHz Compatibility
• Page Write Time: 5 ms, Maximum
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection > 4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 years
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges:
- Industrial (I):
-40C to +85C
- Extended (E)
-40C to +125C
• 8-Lead SOIC, 8-Lead SOIJ, 8-Lead TSSOP,
8-Lead DFN, 8-Lead TDFN, 8-Lead MSOP,
8-Lead PDIP and 8-Ball CSP
Description
The Microchip Technology Inc. 24XX128(1) is a 16K x
8 (128 Kbit) Serial Electrically Erasable PROM
(EEPROM), capable of operation across a broad voltage range (1.7V to 5.5V). It has been developed for
advanced, low-power applications such as personal
communications or data acquisition. This device also
has a page write capability of up to 64 bytes of data.
This device is capable of both random and sequential
reads up to the 128K boundary. Functional address
lines allow up to eight devices on the same bus, for up
to 1 Mbit address space.
Note 1: 24XX128 is used in this document as a
generic part number for the 24AA128/
24LC128/24FC128 devices.
• Automotive AEC-Q100 Qualified
Package Types
A1
2
A2
3
VSS
4
8
VCC
A0
1
7
WP
A1
2
6
SCL
A2
3
5
SDA
VSS
4
8-Lead DFN/TDFN
(Top View)
8
VCC
A0 1
7
WP
A1 2
6
SCL
5
SDA
A2 3
VSS
4
8-Ball CSP
(Top View)
VCC A1 A0
8 VCC
24XX128
1
8-Lead SOIC/SOIJ/TSSOP
(Top View)
24XX128
A0
24XX128
8-Lead PDIP/MSOP(1)
(Top View)
7 WP
6 SCL
5 SDA
1
WP
6
4
2
7
5
3
A2
8
SDA SCL VSS
Note 1: Pins A0 and A1 are no-connects for the MSOP package only.
2010-2019 Microchip Technology Inc.
DS20001191T-page 1
24AA128/24LC128/24FC128
Block Diagram
A0 A1 A2 WP
I/O
Control
Logic
Memory
Control
Logic
HV Generator
XDEC
EEPROM
Array
Page Latches
I/O
SCL
YDEC
SDA
VCC
VSS
DS20001191T-page 2
Sense Amp.
R/W Control
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC............................................................................................................................................................................. 6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................ -40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V TA = -40°C to +85°C
Extended (E):
VCC = +2.5V to 5.5V TA = -40°C to 125°C
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
Conditions
D1
VIH
High-level input voltage
0.7 VCC
—
V
—
D2
VIL
Low-level input voltage
—
0.3 VCC
V
VCC 2.5V
—
0.2 VCC
V
VCC < 2.5V
0.05 VCC
—
V
VCC 2.5V (Note)
D3
VHYS
Hysteresis of Schmitt Trigger
inputs (SDA, SCL pins)
D4
VOL
Low-level output voltage
—
0.40
V
IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
D5
ILI
Input leakage current
—
±1
A
VIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D6
ILO
Output leakage current
—
±1
A
VOUT = VSS or VCC
D7
CIN,
COUT
Pin capacitance
(all inputs/outputs)
—
10
pF
VCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
D8
ICC Read Operating current
—
400
A
VCC = 5.5V, SCL = 400 kHz
D9
ICCS
ICC Write
Note:
Standby current
—
3
mA
VCC = 5.5V
—
1
A
SDA = SCL = VCC = 5.5V
A0, A1, A2, WP = VSS, I-Temp
—
5
A
SDA = SCL = VCC = 5.5V
A0, A1, A2, WP = VSS, E-Temp
This parameter is periodically sampled and not 100% tested.
2010-2019 Microchip Technology Inc.
DS20001191T-page 3
24AA128/24LC128/24FC128
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V TA = -40°C to +85°C
Extended (E):
VCC = +2.5V to 5.5V TA = -40°C to 125°C
AC CHARACTERISTICS
Param.
Symbol
No.
1
2
3
4
FCLK
THIGH
TLOW
TR
Characteristic
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
(Note 1)
5
TF
6
THD:STA Start condition hold time
7
TSU:STA Start condition setup time
Min.
Max.
Units
Conditions
—
100
kHz
1.7V VCC 2.5V
—
400
kHz
2.5V VCC 5.5V
—
400
kHz
1.7V VCC 2.5V (24FC128)
—
1000
kHz
2.5V VCC 5.5V (24FC128)
4000
—
ns
1.7V VCC 2.5V
600
—
ns
2.5V VCC 5.5V
600
—
ns
1.7V VCC 2.5V (24FC128)
500
—
ns
2.5V VCC 5.5V (24FC128)
4700
—
ns
1.7V VCC 2.5V
1300
—
ns
2.5V VCC 5.5V
1300
—
ns
1.7V VCC 2.5V (24FC128)
500
—
ns
2.5V VCC 5.5V (24FC128)
—
1000
ns
1.7V VCC 2.5V
—
300
ns
2.5V VCC 5.5V
—
300
ns
1.7V VCC 5.5V (24FC128)
—
300
ns
All except, 24FC128
—
100
ns
1.7V VCC 5.5V (24FC128)
4000
—
ns
1.7V VCC 2.5V
600
—
ns
2.5V VCC 5.5V
600
—
ns
1.7V VCC 2.5V (24FC128)
250
—
ns
2.5V VCC 5.5V (24FC128)
4700
—
ns
1.7V VCC 2.5V
600
—
ns
2.5V VCC 5.5V
600
—
ns
1.7V VCC 2.5V (24FC128)
250
—
ns
2.5V VCC 5.5V (24FC128)
8
THD:DAT Data input hold time
0
—
ns
(Note 2)
9
TSU:DAT Data input setup time
250
—
ns
1.7V VCC 2.5V
100
—
ns
2.5V VCC 5.5V
10
TSU:STO Stop condition setup time
100
—
ns
1.7V VCC 5.5V (24FC128)
4000
—
ns
1.7 V VCC 2.5V
600
—
ns
2.5 V VCC 5.5V
600
—
ns
1.7V VCC 2.5V (24FC128)
250
—
ns
2.5 V VCC 5.5V (24FC128)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s website
at www.microchip.com.
DS20001191T-page 4
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V TA = -40°C to +85°C
Extended (E):
VCC = +2.5V to 5.5V TA = -40°C to 125°C
AC CHARACTERISTICS
Param.
Symbol
No.
11
12
13
14
15
TSU:WP
THD:WP
TAA
TBUF
TOF
Characteristic
WP setup time
WP hold time
Output valid from clock
(Note 2)
Bus Free Time: The time the
bus must be free before a
new transmission can start
Output fall time from VIH
minimum to VIL maximum
CB 100 pF
Min.
Max.
Units
Conditions
4000
—
ns
1.7V VCC 2.5V
600
—
ns
2.5V VCC 5.5V
600
—
ns
1.7V VCC 5.5V (24FC128)
4700
—
ns
1.7V VCC 2.5V
1300
—
ns
2.5V VCC 5.5V
1300
—
ns
1.7V VCC 5.5V (24FC128)
—
3500
ns
1.7V VCC 2.5V
—
900
ns
2.5V VCC 5.5V
—
900
ns
1.7V VCC 2.5V (24FC128)
—
400
ns
2.5V VCC 5.5V (24FC128)
4700
—
ns
1.7V VCC 2.5V
1300
—
ns
2.5V VCC 5.5V
1300
—
ns
1.7V VCC 2.5V (24FC128)
500
—
ns
2.5V VCC 5.5V (24FC128)
10 + 0.1CB
250
ns
All except, 24FC128 (Note 1)
—
250
ns
24FC128 (Note 1)
16
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
All except, 24FC128
(Notes 1 and 3)
17
TWC
Write Cycle Time
(byte or page)
—
5
ms
—
—
Endurance
1,000,000
—
18
cycles 25°C, 5.5V, Page Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s website
at www.microchip.com.
2010-2019 Microchip Technology Inc.
DS20001191T-page 5
24AA128/24LC128/24FC128
FIGURE 1-1:
BUS TIMING DATA
5
SCL
SDA
IN
7
3
6
4
D3
2
8
10
9
16
14
13
SDA
OUT
WP
DS20001191T-page 6
(protected)
(unprotected)
11
12
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
A0
PIN FUNCTION TABLE
SOIC
SOIJ
TSSOP
DFN(1)
TDFN(1)
MSOP
PDIP
CSP
Function
1
1
1
1
1
—
1
3
User Configurable Chip Select
A1
2
2
2
2
2
—
2
2
User Configurable Chip Select
A2
3
3
3
3
3
3
3
5
User Configurable Chip Select
VSS
4
4
4
4
4
4
4
8
Ground
SDA
5
5
5
5
5
5
5
6
Serial Address/Data I/O
SCL
6
6
6
6
6
6
6
7
Serial Clock
WP
7
7
7
7
7
7
7
4
Write-Protect Input
8
8
8
8
8
8
8
1
Power Supply
VCC
Note 1:
2.1
The exposed pad on the DFN/TDFN package can be connected to VSS or left floating.
A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX128 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Note:
For the MSOP package only, pins A0 and
A1 are not connected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either VCC or VSS.
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4
Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
In most applications, the chip address inputs A0, A1
and A2 are hardwired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2010-2019 Microchip Technology Inc.
DS20001191T-page 7
24AA128/24LC128/24FC128
3.0
FUNCTIONAL DESCRIPTION
The 24XX128 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions while the
24XX128 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
4.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (although only the last 64 will be
stored when doing a write operation). When an
overwrite does occur, it will replace data in a
First-In First-Out (FIFO) principle.
4.5
Note:
Bus Not Busy (A)
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
FIGURE 4-1:
SCL
(A)
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse, which is associated with this Acknowledge
bit.
Both data and clock lines remain high.
4.2
Data Valid (D)
The 24XX128 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the Acknowledge-related clock pulse. Moreover, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by not generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX128) will leave the data line high to enable
the master to generate the Stop condition.
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SDA
DS20001191T-page 8
Data
Allowed
to Change
Stop
Condition
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
FIGURE 4-2:
SCL
SDA
ACKNOWLEDGE TIMING
1
2
3
4
5
Acknowledge
Bit
6
7
Data from transmitter
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
2010-2019 Microchip Technology Inc.
8
9
1
2
3
Data from transmitter
Receiver must release the SDA line
at this point, allowing the Transmitter
to can continue sending data.
DS20001191T-page 9
24AA128/24LC128/24FC128
5.0
DEVICE ADDRESSING
FIGURE 5-1:
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists of a 4-bit control code. For the 24XX128, this
is set as ‘1010’ binary for read and write operations.
The next three bits of the control byte are the Chip
Select bits (A2, A1, A0). The Chip Select bits allow the
use of up to eight 24XX128 devices on the same bus
and are used to select which device is accessed. The
Chip Select bits in the control byte must correspond to
the logic levels on the corresponding A2, A1 and A0
pins for the device to respond. These bits, in effect, are
the three Most Significant bits of the word address. The
combination of the 4-bit control code and the next three
bits are called the slave address.
For the MSOP package, the A0 and A1 pins are not
connected. During device addressing, the A0 and A1
Chip Select bits (Figures 5-1 and 5-2) should be set to
‘0’. Only two 24XX128 MSOP packages can be
connected to the same bus.
The last bit of the control byte is the Read/Write (R/W)
bit and it defines the operation to be performed. When
set to a ‘1’, a read operation is selected. When set to a
‘0’, a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 5-2). Because only A13…A0 are used, the
upper two address bits are “don’t care” bits. The upper
address bits are transferred first, followed by the Less
Significant bits.
Following the Start condition, the 24XX128 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX128 will select a read
or write operation.
FIGURE 5-2:
0
1
Read/Write Bit
Chip Select
Bits
Control Code
S
1
0
1
0
A2
A1
A0 R/W ACK
Slave Address
Start Bit
5.1
Acknowledge Bit
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 1 Mbit
by adding up to eight 24XX128 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A14; A1 as address bit A15; and A2
as address bit A16. It is not possible to sequentially
read across device boundaries.
For the MSOP package, up to two 24XX128 devices
can be added for up to 256 Kbit of address space. In
this case, software can use A2 of the control byte as
address bit A16. Bits A0 (A14) and A1 (A15) of the
control byte must always be set to logic ‘0’ for the
MSOP.
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
1
CONTROL BYTE
FORMAT
0
A
2
Control
Code
DS20001191T-page 10
A
1
Chip
Select
Bits
Address High Byte
A
0 R/W
x
x
A A A A
13 12 11 10
Address Low Byte
A
9
A
8
A
7
•
•
•
•
•
•
A
0
x = “don’t care” bit
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
6.0
WRITE OPERATIONS
6.1
Byte Write
once the master has transmitted a Stop condition.
Upon receipt of each word, the six lower Address
Pointer bits, which form the byte counter, are internally
incremented by one. If the master should transmit more
than 64 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX128. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX128, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX128 acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX128 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command. After a byte
write command, the internal address counter will point
to the address location following the one that was just
written.
Note:
6.2
Note:
When doing a write of less than 64 bytes
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
6.3
Page Write
Bus Activity
Master
SDA Line
Write Protection
The WP pin allows the user to write-protect the entire
array (0000-3FFF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
The write control byte, word address, and the first data
byte are transmitted to the 24XX128 in much the same
way as in a byte write. The exception is that instead of
generating a Stop condition, the master transmits up to
63 additional bytes, which are temporarily stored in the
on-chip page buffer, and will be written into memory
FIGURE 6-1:
Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
page size – 1. If a page write
command attempts to write across a
physical page boundary, the result is
that the data wraps around to the
beginning of the current page (overwriting data previously stored there),
instead of being written to the next
page, as might be expected. It is,
therefore, necessary for the application software to prevent page write
operations that would attempt to cross
a page boundary.
BYTE WRITE
S
T
A
R
T
Control
Byte
Address
High Byte
AA
S1010A
2 10 0
Bus Activity
2010-2019 Microchip Technology Inc.
Address
Low Byte
S
T
O
P
Data
xx
A
C
K
P
A
C
K
A
C
K
A
C
K
x = “don’t care” bit
DS20001191T-page 11
24AA128/24LC128/24FC128
FIGURE 6-1:
Bus Activity
Master
SDA Line
PAGE WRITE
S
T
A
R
T
Control
Byte
Address
High Byte
AAA
S10102 1 00
Bus Activity
Address
Low Byte
S
T
O
P
Data Byte 63
Data Byte 0
xx
A
C
K
P
A
C
K
A
C
K
A
C
K
A
C
K
x = “don’t care” bit
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a write command (R/W = 0). If the device is still busy
with the write cycle, then no ACK will be returned. If no
ACK is returned, the Start bit and control byte must be
resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
DS20001191T-page 12
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
8.0
READ OPERATION
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XX128 as part of a write operation (R/W bit set to
‘0’). Once the word address is sent, the master generates a Start condition following the Acknowledge. This
terminates the write operation, but not before the internal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24XX128 will then issue an Acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a Stop condition, which
causes the 24XX128 to discontinue transmission
(Figure 8-2). After a random read command, the
internal address counter will point to the address
location following the one that was just read.
Read operations are initiated in much the same way as
write operations with the exception that the R/W bit of
the control byte is set to one. There are three basic
types of read operations: current address read, random
read and sequential read.
8.1
Current Address Read
The 24XX128 contains an address counter that maintains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX128 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX128 discontinues transmission (Figure 8-1).
FIGURE 8-1:
SDA Line
S 1 0 1 0 A AA 1
2 1 0
P
A
C
K
FIGURE 8-2:
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX128 transmits
the first data byte, the master issues an Acknowledge
(as opposed to the Stop condition used in a random
read). This Acknowledge directs the 24XX128 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will not generate an Acknowledge
but will generate a Stop condition.
S
T
O
P
Data
Byte
Control
Byte
Bus Activity
N
O
To provide sequential reads, the 24XX128 contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation. The internal Address
Pointer will automatically roll over from address 3FFF
to address 0000 if the master acknowledges the byte
received from the array address 3FFF.
A
C
K
RANDOM READ
S
T
A
R
T
Bus Activity
Master
SDA Line
8.3
CURRENT ADDRESS
READ
S
T
A
R
T
Bus Activity
Master
Random Read
Control
Byte
S1010AAA0
2 1 0
Bus Activity
x = “don’t care” bit
2010-2019 Microchip Technology Inc.
Address
High Byte
A
C
K
xx
S
T
A
R
T
Address
Low Byte
A
C
K
A
C
K
Control
Byte
S 1 0 1 0 A A A1
2 1 0
S
T
O
P
Data
Byte
A
C
K
N
O
A
C
K
P
DS20001191T-page 13
24AA128/24LC128/24FC128
FIGURE 8-3:
Bus Activity
Master
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
P
SDA Line
Bus Activity
DS20001191T-page 14
S
T
O
P
Data (n + x)
Data (n + 2)
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead SOIC (3.90 mm)
XXXXXXXX
XXXXYYWW
NNN
8-Lead SOIJ (5.28 mm)
Example:
24LC128I
SN e3 0510
017
Example:
XXXXXXXX
XXXXXXXX
YYWWNNN
24LC128
I/SM e3
0510017
8-Lead TSSOP
Example:
XXXX
XYWW
NNN
8-Lead DFN-S
XXXXXXX
XXXXXXX
YYWW
NNN
8-Lead 2x3 TDFN
XXX
YWW
NN
2010-2019 Microchip Technology Inc.
4LC
I510
017
Example:
24LC128
I/MF
0510
017
Example:
A84
510
I7
DS20001191T-page 15
24AA128/24LC128/24FC128
Package Marking Information (Continued)
8-Lead MSOP
Example:
XXXXXX
4L128I
YWWNNN
051017
8-Lead PDIP (300 mil)
Example:
24AA128
I/P e3 017
0510
XXXXXXXX
XXXXXNNN
YYWW
8-Lead Chip Scale
Example:
XXXXXXX
YYWWNNN
24AA128
0810017
1st Line Marking Codes
Part Number
TSSOP
MSOP
SOIC
SOIJ
PDIP
DFN
TDFN
I-Temp
CSP
E-Temp
4AC
4A128T(1)
24AA128T(1)
24AA128
24AA128
24AA128
A81
—
24LC128
4LC
(1)
4L128T
24LC128T(1)
24LC128
24LC128
24LC128
A84
A85
—
24FC128
4FC
4F128T(1)
24FC128T(1)
24FC128
24FC128
24FC128
A8A
—
—
24AA128
24AA128
Note 1: T = Temperature grade (I, E)
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
* Standard OTP marking consists of Microchip part number, year code, week code
and traceability code.
Note:
For very small packages with no room for the JEDEC® designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20001191T-page 16
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
2010-2019 Microchip Technology Inc.
DS20001191T-page 17
24AA128/24LC128/24FC128
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
DS20001191T-page 18
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev E
2010-2019 Microchip Technology Inc.
DS20001191T-page 19
24AA128/24LC128/24FC128
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001191T-page 20
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2019 Microchip Technology Inc.
DS20001191T-page 21
24AA128/24LC128/24FC128
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001191T-page 22
2010-2019 Microchip Technology Inc.
24AA128/24LC128/24FC128
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