24AA256UIDT-I/SN

24AA256UID 256K I2C Serial EEPROM with EUI-48™, EUI-64™ and Unique 32-Bit Serial Number Device Selection Table Part Number 24AA256UID Note 1: VCC Range Max. Clock Frequency Temp. Ranges Page Size EUI-48™ EUI-64™ Unique ID Length 1.7V-5.5V 400 kHz(1) I 64-byte Yes Yes 32-bit 100 kHz for VCC < 2.5V. Features Description • Preprogrammed 32-Bit Serial Number: - Unique across all UID-family EEPROMs - Scalable to 48-bit, 64-bit, 128-bit, 256-bit, and other lengths • Preprogrammed Globally Unique, 48-bit or 64-bit Node Address: - Compatible with EUI-48™ and EUI-64™ • Codes Stored in Permanently Write-Protected Upper 1/8th of EEPROM Array • Single Supply with Operation Down to 1.7V • Low-Power CMOS Technology: - Active current 400 µA, typical - Standby current 100 nA, typical • 2-Wire Serial Interface, I2C Compatible • Cascadable up to Eight Devices • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kHz and 400 kHz Clock Compatibility • Page Write Time 5 ms Maximum • Self-Timed Erase/Write Cycle • 64-Byte Page Write Buffer • ESD Protection >4000V • More than One Million Erase/Write Cycles • Data Retention >200 years • Packages Include 8-lead PDIP, SOIC and TSSOP • RoHS Compliant • Temperature Ranges: - Industrial (I): -40°C to +85°C The Microchip Technology Inc. 24AA256UID is a 32K x 8 (256 Kbit) Serial Electrically Erasable PROM with preprogrammed EUI-48 and EUI-64 node addresses and a 32-bit Unique ID, capable of operation across a broad voltage range (1.7V to 5.5V). This device also has a page write capability of up to 64 bytes of data. This device is available in the standard 8-pin plastic DIP, SOIC and TSSOP packages.  2013-2018 Microchip Technology Inc. Block Diagram A0 A1A2 I/O Control Logic Memory Control Logic HV Generator EEPROM Array XDEC Page Latches I/O SCL YDEC SDA VCC Sense Amp. R/W Control VSS Package Types 1 A1 2 A2 3 VSS 4 SOIC/TSSOP 8 VCC A0 1 7 NC A1 2 6 SCL A2 3 5 SDA VSS 4 24AA256UID A0 24AA256UID PDIP 8 VCC 7 NC 6 SCL 5 SDA DS20005215D-page 1 24AA256UID 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied..................................................................................................-40°C to +85°C ESD protection on all pins........................................................................................................................................ ≥4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V DC CHARACTERISTICS Param. Symbol No. Characteristic Min. Max. Units TA = -40°C to +85°C Conditions D1 VIH High-Level Input Voltage 0.7 VCC — V D2 VIL Low-Level Input Voltage — 0.3 VCC V VCC ≥ 2.5V — 0.2 VCC V VCC < 2.5V 0.05 VCC — V VCC ≥ 2.5V (Note) — 0.40 V IOL = 3.0 mA; VCC = 4.5V — 0.40 V IOL = 2.1 mA; VCC = 2.5V D3 VHYS D4 VOL Hysteresis of Schmitt Trigger Inputs (SDA, SCL pins) Low-Level Output Voltage D5 ILI Input Leakage Current — ±1 µA VIN = VSS or VCC D6 ILO Output Leakage Current — ±1 µA VOUT = VSS or VCC D7 CIN, COUT Pin Capacitance (all inputs/outputs) — 10 pF VCC = 5.0V (Note) TA = 25°C, FCLK = 1 MHz ICCREAD Operating Current — 400 µA VCC = 5.5V, SCL = 400 kHz ICCWRITE — 3 mA VCC = 5.5V — 1 µA TA = -40°C to +85°C SCL = SDA = VCC = 5.5V A0, A1, A2 = VSS D8 D9 Note: ICCS Standby Current This parameter is periodically sampled and not 100% tested.  2013-2018 Microchip Technology Inc. DS20005215D-page 2 24AA256UID TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V AC CHARACTERISTICS Param. Symbol No. Characteristic Min. Max. Units TA = -40°C to +85°C Conditions 1 FCLK Clock Frequency — 100 kHz 1.7V ≤ VCC < 2.5V — 400 kHz 2.5V ≤ VCC ≤ 5.5V 2 THIGH Clock High Time 4000 — ns 1.7V ≤ VCC < 2.5V 600 — ns 2.5V ≤ VCC ≤ 5.5V 3 TLOW Clock Low Time 4700 — ns 1.7V ≤ VCC < 2.5V 1300 — ns 2.5V ≤ VCC ≤ 5.5V 4 TR SDA and SCL Rise Time (Note 1) — 1000 ns 1.7V ≤ VCC < 2.5V — 300 ns 2.5V ≤ VCC ≤ 5.5V 5 TF SDA and SCL Fall Time (Note 1) — 300 ns 4000 — ns 600 — ns 2.5V ≤ VCC ≤ 5.5V 4700 — ns 1.7V ≤ VCC < 2.5V 600 — ns 2.5V ≤ VCC ≤ 5.5V 6 THD:STA Start Condition Hold Time TSU:STA 7 Start Condition Setup Time 1.7V ≤ VCC < 2.5V 8 THD:DAT Data Input Hold Time 0 — ns Note 2 9 TSU:DAT Data Input Setup Time 250 — ns 1.7V ≤ VCC < 2.5V 100 — ns 2.5V ≤ VCC ≤ 5.5V 10 TSU:STO Stop Condition Setup Time 4000 — ns 1.7V ≤ VCC < 2.5V 600 — ns 2.5V ≤ VCC ≤ 5.5V — 3500 ns 1.7 V ≤ VCC < 2.5V 11 TAA 12 TBUF Output Valid from Clock (Note 2) — 900 ns 2.5 V ≤ VCC ≤ 5.5V Bus Free Time: Bus time must be free before a new transmission can start 4700 — ns 1.7V ≤ VCC < 2.5V 1300 — ns 2.5V ≤ VCC ≤ 5.5V 10 + 0.1CB 250 ns Note 1 Notes 1 and 3 13 TOF Output Fall Time from VIH minimum to VIL maximum CB ≤ 100 pF 14 TSP Input Filter Spike Suppression (SDA and SCL pins) — 50 ns 15 TWC Write Cycle Time (byte or page) — 5 ms 1,000,000 — 16 Endurance Note 1: 2: 3: 4: cycles Page mode, 25°C, 5.5V (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s website at www.microchip.com.  2013-2018 Microchip Technology Inc. DS20005215D-page 3 24AA256UID FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA IN D3 2 3 8 9 4 10 6 14 11 12 SDA OUT  2013-2018 Microchip Technology Inc. DS20005215D-page 4 24AA256UID 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: 2.1 PIN FUNCTION TABLE Name 8-pin PDIP 8-pin SOIC 8-pin TSSOP A0 1 1 1 User Configurable Chip Select A1 2 2 2 User Configurable Chip Select Function A2 3 3 3 User Configurable Chip Select VSS 4 4 4 Ground SDA 5 5 5 Serial Data SCL 6 6 6 Serial Clock NC 7 7 7 Not Connected VCC 8 8 8 +1.7V to 5.5V A0, A1, A2 Chip Address Inputs 2.2 Serial Data (SDA) The A0, A1 and A2 inputs are used by the 24AA256UID for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz). Up to eight devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed.  2013-2018 Microchip Technology Inc. 2.3 Serial Clock (SCL) This input is used to synchronize the data transfer to and from the device. DS20005215D-page 5 24AA256UID 3.0 FUNCTIONAL DESCRIPTION The 24AA256UID supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions while the 24AA256UID works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus Not Busy (A) Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high, determines a Start condition. All commands must be preceded by a Start condition. 4.3 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device. 4.5 Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24AA256UID does not generate any Acknowledge bits if an internal programming cycle is in progress. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24AA256UID) will leave the data line high to enable the master to generate the Stop condition. Stop Data Transfer (C) A low-to-high transition of the SDA line, while the clock (SCL) is high, determines a Stop condition. All operations must end with a Stop condition.  2013-2018 Microchip Technology Inc. DS20005215D-page 6 24AA256UID FIGURE 4-1: (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA FIGURE 4-2: Data Allowed to Change Stop Condition ACKNOWLEDGE TIMING Acknowledge Bit SCL SDA 1 2 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point, allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.  2013-2018 Microchip Technology Inc. 8 9 1 2 3 Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data. DS20005215D-page 7 24AA256UID 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code. For the 24AA256UID, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24AA256UID devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are, in effect, the three Most Significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to ‘0’, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because only A14…A0 are used, the upper address bits are “don’t cares”. The upper address bits are transferred first, followed by the Less Significant bits. Following the Start condition, the 24AA256UID monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a ‘1010’ code and appropriate device select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24AA256UID will select a read or write operation. FIGURE 5-2: 0 1 Control Code Read/Write Bit Chip Select Bits Control Code S 1 0 1 A2 0 A1 A0 R/W ACK Slave Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 2 Mbit by adding up to eight 24AA256UID devices on the same bus. In this case, software can use A0 of the control byte as address bit A15; A1 as address bit A16; and A2 as address bit A17. It is not possible to sequentially read across device boundaries. ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte 1 CONTROL BYTE FORMAT 0 A 2 A 1 Address High Byte A 0 R/W Chip Select Bits  2013-2018 Microchip Technology Inc. x A A A A A 14 13 12 11 10 Address Low Byte A 9 A 8 A 7 • • • • • • A 0 x = “don’t care” bit DS20005215D-page 8 24AA256UID 6.0 WRITE OPERATIONS 6.1 Byte Write Following the Start condition from the master, the control code (four bits), the Chip Select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the Address Pointer of the 24AA256UID. The next byte is the Least Significant Address Byte. After receiving another Acknowledge signal from the 24AA256UID, the master device will transmit the data word to be written into the addressed memory location. The 24AA256UID acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and during this time, the 24AA256UID will not generate Acknowledge signals (Figure 6-1). Note: 6.2 When doing a write of less than 64 bytes, the data in the rest of the page is refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, and for this reason endurance is specified per page. 6.3 Write Protection The upper eighth of the array (7000h-7FFFh) is permanently write-protected. Write operations to this address range are inhibited. Read operations are not affected. The remainder of the array (0000h-6FFFh) can be written to and read from normally. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is, therefore, necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Page Write The write control byte, word address and the first data byte are transmitted to the 24AA256UID in much the same way as in a byte write. The exception is that instead of generating a Stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer, and will be written into memory once the master has transmitted a Stop condition. Upon receipt of each word, the six lower Address Pointer bits are internally incremented by one. If the master should transmit more than 64 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2).  2013-2018 Microchip Technology Inc. DS20005215D-page 9 24AA256UID FIGURE 6-1: BYTE WRITE SDA Line S T A R T Bus Activity AA S1 0 10A 2 10 0 Bus Activity Master Control Byte Bus Activity Master SDA Line Bus Activity Address Low Byte S T O P Data P x A C K A C K A C K A C K x = “don’t care” bit FIGURE 6-2: Address High Byte PAGE WRITE S T A R T Control Byte Address High Byte AAA S101 02 1 00 x = “don’t care” bit  2013-2018 Microchip Technology Inc. Address Low Byte Data Byte 0 S T O P Data Byte 63 P x A C K A C K A C K A C K A C K DS20005215D-page 10 24AA256UID 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for the flow diagram. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? NO YES Next Operation  2013-2018 Microchip Technology Inc. DS20005215D-page 11 24AA256UID 8.0 READ OPERATION 8.2 Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is done by sending the word address to the 24AA256UID as part of a write operation (R/W bit set to ‘0’). Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to ‘1’. The 24AA256UID will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, but generate a Stop condition, which causes the 24AA256UID to discontinue transmission (Figure 8-2). After a random Read command, the internal address counter will point to the address location following the one that was just read. Read operations are initiated in much the same way as write operations, with the exception that the R/W bit of the control byte is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24AA256UID contains an address counter that maintains the address of the last word accessed, internally incremented by ‘1’. Therefore, if the previous read access was to address ‘n’ (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to ‘1’, the 24AA256UID issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but generate a Stop condition and the 24AA256UID discontinues transmission (Figure 8-1). FIGURE 8-1: 8.3 S T A R T SDA Line S 1 0 1 0 A AA 1 2 1 0 Control Byte FIGURE 8-2: Bus Activity Master SDA Line P A C K Bus Activity S T O P Data Byte Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24AA256UID transmits the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random read. This acknowledge directs the 24AA256UID to transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge, but a Stop condition. To provide sequential reads, the 24AA256UID contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address 7FFF to address 0000 if the master acknowledges the byte received from the array address 7FFF. CURRENT ADDRESS READ Bus Activity Master Random Read N O A C K RANDOM READ S T A R T Control Byte Address High Byte S1 01 0 AAA0 2 1 0 x A C K Bus Activity S T A R T Address Low Byte Control Byte S 1 0 1 0 A A A1 2 1 0 A C K A C K Data (n + 1) Data (n + 2) S T O P Data Byte P N O A C K A C K x = “don’t care” bit FIGURE 8-3: Bus Activity Master SEQUENTIAL READ Control Byte Data (n) S T O P Data (n + x) P SDA Line Bus Activity A C K  2013-2018 Microchip Technology Inc. A C K A C K A C K N O A C K DS20005215D-page 12 24AA256UID 9.0 PREPROGRAMMED SERIAL NUMBER AND NODE ADDRESSES The 24AA256UID is programmed at the factory with globally unique EUI-48 and EUI-64 node addresses, and a 32-bit serial number stored in the upper eighth of the array and permanently write-protected. The remaining 229,376 bits are available for application use. FIGURE 9-1: MEMORY ORGANIZATION 0000h (User – Writable) 6FFFh 7000h Unused (Read as 0xFF) 7F79h 7F7Ah 7F7Fh Unused (Read as 0xFF) EUI-64™ Node Address 7FB8h 7FBFh Note: 7FFAh 7FFFh Shaded region is permanently write-protected  2013-2018 Microchip Technology Inc. The 24AA256UID features a unique 32-bit serial number stored in array locations 0x7FFC through 0x7FFF, as shown in Figure 9-2. Note: 9.1.1 The 32-bit serial number is unique across all Microchip UID-family serial EEPROM devices. MANUFACTURER AND DEVICE IDENTIFIERS In addition to the serial number, a manufacturer code is stored at location 0x7FFA and a device identifier is stored at 0x7FFB. The manufacturer code is fixed as 0x29. For the 24AA256UID, the device identifier is 0x48. The ‘4’ indicates the I2C family and the ‘8’ indicates a 256 Kbit memory density. EXTENDING THE 32-BIT SERIAL NUMBER For applications that require serial numbers larger than 32 bits, additional data bytes can be used to pad the provided serial number to meet the required length. Any data byte values can be used for padding as the 32-bit serial number ensures the extended serial number remains unique. The padding can be performed in two ways. The first method is to pad the data in software by combining the 32-bit serial number from the 24AA256UID with fixed data. The second method is to extend the number of bytes read from the 24AA256UID to meet the required length. Table 9-1 shows example address ranges and their corresponding serial number lengths. TABLE 9-1: Unused (Read as 0xFF) 32-Bit Serial Number and Identifiers 32-Bit Serial Number 9.1.2 Standard EEPROM EUI-48™ Node Address 9.1 Start Address EXTENDED READ EXAMPLES End Address Serial Number Length 0x7FFC 0x7FFF 32 bits 0x7FFA 0x7FFF 48 bits 0x7FF8 0x7FFF 64 bits 0x7FF0 0x7FFF 128 bits 0x7FE0 0x7FFF 256 bits DS20005215D-page 13 24AA256UID FIGURE 9-2: SERIAL NUMBER PHYSICAL MEMORY MAP EXAMPLE Description Manufacturer Code Device Code Data 29h 48h 9.2 7FFAh 7FFBh EUI-48 Node Address Organizationally Unique Identifiers (OUIs) Each OUI provides roughly 16M (224) addresses. Once the address pool for an OUI is exhausted, Microchip will acquire a new OUI from IEEE to use for programming this model. For more information on past and current OUIs see “Organizationally Unique Identifiers For Preprogrammed EUI-48 and EUI-64 Address Devices” Technical Brief (DS90003187). Note: 34h 56h 78h 7FFEh 7FFFh Serialized The 6-byte EUI-48 node address value is stored in array locations 0x7F7A through 0x7F7F, as shown in Figure 9-3. The first three bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. The remaining three bytes are the Extension Identifier, and are generated by Microchip to ensure a globally unique, 48-bit value. 9.2.0.1 12h Fixed Type Array Address 32-bit Serial Number 7FFCh 7FFDh 9.3 EUI-64 Node Address The 8-byte EUI-64 node address value is stored in array locations 0x7FB8 through 0x7FBF, as shown in Figure 9-4. The first three bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. The remaining five bytes are the Extension Identifier, and are generated by Microchip to ensure a globally unique, 64-bit value. Note: In conformance with IEEE guidelines, Microchip will not use the values 0xFFFE and 0xFFFF for the first two bytes of the EUI-64 Extension Identifier. These two values are specifically reserved to allow applications to encapsulate EUI-48 addresses into EUI-64 addresses. The OUI will change as addresses are exhausted. Customers are not guaranteed to receive a specific OUI and should design their application to accept new OUIs as they are introduced.  2013-2018 Microchip Technology Inc. DS20005215D-page 14 24AA256UID FIGURE 9-3: EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE 24-bit Organizationally Unique Identifier Description Data 00h Array Address 7F7Ah 04h 24-bit Extension Identifier A3h 12h 34h 56h 7F7Fh Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56 FIGURE 9-4: Description EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE 24-bit Organizationally Unique Identifier Data 00h Array Address 7FB8h 04h A3h 40-bit Extension Identifier 12h 34h 56h 78h 90h 7FBFh Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90  2013-2018 Microchip Technology Inc. DS20005215D-page 15 24AA256UID 10.0 PACKAGING INFORMATION 10.1 Package Marking Information* 8-Lead PDIP (300 mil) Example XXXXXXXX T/XXXNNN YYWW 4A256UID I/P e3 017 1632 8-Lead SOIC (150 mil) Example XXXXXXXT XXXXYYWW NNN 4A256IDI SN e3 1632 017 8-Lead TSSOP Example XXXX YYWW NNN AAAP 1632 017 1st Line Marking Code Part Number 24AA256UID Legend: XX...X T Y YY WW NNN e3 PDIP SOIC TSSOP 4A256UID 4A256IDI AAAP Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC® designator for Matte Tin (Sn) * Standard device marking consists of Microchip part number, year code, week code and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. Note: For very small packages with no room for the Pb-free JEDEC® designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2013-2018 Microchip Technology Inc. DS20005215D-page 16 24AA256UID 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2  2013-2018 Microchip Technology Inc. DS20005215D-page 17 24AA256UID 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e 2 e 2 e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness Upper Lead Width b1 b Lower Lead Width Overall Row Spacing eB § e MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2  2013-2018 Microchip Technology Inc. DS20005215D-page 18 24AA256UID 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 2 1 e B NX b 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H SEE VIEW C VIEW A–A 0.23 L (L1) VIEW C Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2  2013-2018 Microchip Technology Inc. DS20005215D-page 19 24AA256UID 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L Footprint L1 Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2  2013-2018 Microchip Technology Inc. DS20005215D-page 20 24AA256UID 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev B  2013-2018 Microchip Technology Inc. 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