24C02C-I/ST

24C02C 2K 5.0V I2C™ Serial EEPROM Features: Description: • Single-Supply with Operation from 4.5V to 5.5V • Low-Power CMOS Technology: - Read current 1 mA, max. - Standby current 5 μA, max. • 2-Wire Serial Interface, I2C™ Compatible • Cascadable up to Eight Devices • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kHz and 400 kHz Clock Compatibility • Fast Page or Byte Write Time 1 ms, typical • Self-Timed Erase/Write Cycle • 16-Byte Page Write Buffer • Hardware Write-Protect for Upper Half of the Array (80h-FFh) • ESD Protection >4,000V • More than 1 Million Erase/Write Cycles • Data Retention >200 Years • Factory Programming Available • Packages Include 8-lead PDIP, SOIC, TSSOP, DFN, TDFN and MSOP • Pb-Free and RoHS Compliant • Temperature ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C The Microchip Technology Inc. 24C02C is a 2K bit Serial Electrically Erasable PROM with a voltage range of 4.5V to 5.5V. The device is organized as a single block of 256 x 8-bit memory with a 2-wire serial interface. Low-current design permits operation with max. standby and active currents of only 5 μA and 1 mA, respectively. The device has a page write capability for up to 16 bytes of data and has fast write cycle times of only 1 ms for both byte and page writes. Functional address lines allow the connection of up to eight 24C02C devices on the same bus for up to 16K bits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP, 8-pin SOIC (3.90 mm), 8-pin 2x3 DFN and TDFN, 8-pin MSOP and TSSOP packages. Block Diagram A0 A1 A2 I/O Control Logic WP HV Generator Memory Control Logic EEPROM Array XDEC SDA SCL Write-Protect Circuitry Vcc YDEC Vss Sense Amp. R/W Control Package Types SOIC, TSSOP PDIP, MSOP A0 1 8 VCC A0 1 8 DFN/TDFN VCC A1 2 A1 2 7 WP A1 2 7 WP A2 3 6 SCL A2 3 6 SCL VSS 4 5 SDA VSS 4 5 SDA © 2008 Microchip Technology Inc. A0 1 A2 3 VSS 4 8 VCC 7 WP 6 SCL 5 SDA DS21202J-page 1 24C02C 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. Sym. Characteristic Electrical Characteristics: Industrial (I): VCC = +4.5V to 5.5V Automotive (E): VCC = +4.5V to 5.5V Min. Max. Units — — — TA = -40°C to +85°C TA = -40°C to +125°C Conditions D1 — A0, A1, A2, SCL, SDA and WP pins: — D2 VIH High-level input voltage 0.7 VCC — V — D3 VIL Low-level input voltage — 0.3 VCC V — D4 VHYS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) 0.05 VCC — V (Note) D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 ma @ VCC = 4.5V D6 ILI Input leakage current — ±1 μA VIN = VSS or VCC, WP = VSS D7 ILO Output leakage current — ±1 μA VOUT = VSS or VCC D8 CIN, COUT Pin capacitance (all inputs/outputs) — 10 pF VCC = 5.0V (Note) TA = 25°C, f = 1 MHz D9 ICC Read Operating current — 1 mA VCC = 5.5V, SCL = 400 kHz ICC Write — 3 mA VCC = 5.5V — 5 μA VCC = 5.5VSCL = SDA = VCC WP = VSS D10 Note: ICCS Standby current This parameter is periodically sampled and not 100% tested. DS21202J-page 2 © 2008 Microchip Technology Inc. 24C02C TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +4.5V to 5.5V Automotive (E): VCC = +4.5V to 5.5V AC CHARACTERISTICS Param. No. Sym. Characteristic Min. Max. Units Conditions 1 FCLK Clock frequency — — 100 400 kHz — (I-temp) 2 THIGH Clock high time 4000 600 — — ns — (I-temp) 3 TLOW Clock low time 4700 1300 — — ns — (I-temp) 4 TR SDA and SCL rise time (Note 1) — — 1000 300 ns — (I-temp) 5 TF SDA and SCL fall time (Note 1) — 300 ns — (I-temp) 6 THD:STA Start condition hold time 4000 600 — — ns — (I-temp) 7 TSU:STA Start condition setup time 4700 600 — — ns — (I-temp) 8 THD:DAT Data input hold time 0 — ns (Note 2) 9 TSU:DAT Data input setup time 250 100 — — ns — (I-temp) 10 TSU:STO Stop condition setup time 4000 600 — — ns — (I-temp) 11 TAA Output valid from clock (Note 2) — — 3500 900 ns — (I-temp) 12 TBUF Bus free time: Time the bus must be free before a new transmission can start 4700 1300 — — ns — (I-temp) 13 TOF Output fall time from VIH minimum to VIL maximum CB ≤ 100 pF 10 + 0.1CB 250 ns (Note 1) 14 TSP Input filter spike suppression (SDA and SCL pins) — 50 ns (Note 3) 15 TWC Write cycle time (byte or page) — 1.5 1 ms — (I-temp) 16 — Endurance 1,000,000 — Note 1: 2: 3: 4: TA = -40°C to +85°C TA = -40°C to +125°C cycles 25°C (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com. © 2008 Microchip Technology Inc. DS21202J-page 3 24C02C FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA IN D4 2 3 8 9 4 10 6 14 11 12 SDA OUT DS21202J-page 4 © 2008 Microchip Technology Inc. 24C02C 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Name PIN FUNCTION TABLE PDIP SOIC TSSOP DFN/TDFN MSOP Function A0 1 1 1 1 1 Address Pin A0 A1 2 2 2 2 2 Address Pin A1 A2 3 3 3 3 3 Address Pin A2 VSS 4 4 4 4 4 Ground SDA 5 5 5 5 5 Serial Address/Data I/O SCL 6 6 6 6 6 Serial Clock WP 7 7 7 7 7 Write-Protect Input VCC 8 8 8 8 8 +4.5 V to 5.5 V Power Supply 2.1 SDA Serial Data This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal; therefore, the SDA bus requires a pullup resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 2.2 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. 2.3 A0, A1, A2 The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight 24C02C devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. 2.4 WP This is the hardware write-protect pin. It must be tied to VCC or VSS. If tied to Vcc, the hardware write protection is enabled. If the WP pin is tied to VSS the hardware write protection is disabled. 2.5 Noise Protection The 24C02C employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 3.8 volts at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. © 2008 Microchip Technology Inc. DS21202J-page 5 24C02C 3.0 FUNCTIONAL DESCRIPTIONS The 24C02C supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device that generates the Serial Clock (SCL), controls the bus access, and generates the Start and Stop conditions, while the 24C02C works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus Not Busy (A) Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first-in firstout fashion. 4.5 Acknowledge Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this Acknowledge bit. Note: The 24C02C does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition (Figure 4-2). A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. DS21202J-page 6 © 2008 Microchip Technology Inc. 24C02C FIGURE 4-1: SCL (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (C) (D) Start Condition Address or Acknowledge Valid (C) (A) SDA FIGURE 4-2: Stop Condition Data Allowed to Change ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 SDA 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. © 2008 Microchip Technology Inc. 8 9 1 2 3 Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data. DS21202J-page 7 24C02C 5.0 DEVICE ADDRESSING A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a four-bit control code; for the 24C02C this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24C02C devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a ‘1’ a read operation is selected, and when set to a ‘0’ a write operation is selected. Following the Start condition, the 24C02C monitors the SDA bus checking the control byte being transmitted. Upon receiving a ‘1010’ code and appropriate Chip Select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24C02C will select a read or write operation. DS21202J-page 8 FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Slave Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The Chip Select bits A2, A1, A0 can be used to expand the contiguous address space for up to 16K bits by adding up to eight 24C02C devices on the same bus. In this case, software can use A0 of the control byte as address bit A9, A1 as address bit A10, and A2 as address bit A11. It is not possible to write or read across device boundaries. © 2008 Microchip Technology Inc. 24C02C 6.0 WRITE OPERATIONS 6.1 Byte Write As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. The write cycle time must be observed even if the write protection is enabled. Following the Start signal from the master, the device code (4 bits), the Chip Select bits (3 bits) and the R/W bit, which is a logic low, is placed onto the bus by the master transmitter. The device will acknowledge this control byte during the ninth clock pulse. The next byte transmitted by the master is the word address and will be written into the Address Pointer of the 24C02C. After receiving another Acknowledge signal from the 24C02C the master device will transmit the data word to be written into the addressed memory location. The 24C02C acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24C02C will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command but no data will be written. The write cycle time must be observed even if the write protection is enabled. 6.2 Note: Page Write The write control byte, word address and the first data byte are transmitted to the 24C02C in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 15 additional data bytes to the 24C02C which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a Stop condition. After the receipt of each word, the four lower order Address Pointer bits are internally incremented by one. The higher order four bits of the word address remains constant. If the master should transmit more than 16 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. FIGURE 6-1: S T A R T SDA Line S The WP pin must be tied to VCC or VSS. If tied to VCC, the upper half of the array (080-0FF) will be writeprotected. If the WP pin is tied to VSS, then write operations to all address locations are allowed. Control Byte Word Address S T O P Data P A C K Bus Activity FIGURE 6-2: SDA Line Write Protection BYTE WRITE Bus Activity Master Bus Activity Master 6.3 Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. A C K A C K PAGE WRITE S T A R T Control Byte Word Address (n) Data n Data n +1 S T O P Data n + 15 S Bus Activity © 2008 Microchip Technology Inc. P A C K A C K A C K A C K A C K DS21202J-page 9 24C02C 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for flow diagram. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation DS21202J-page 10 © 2008 Microchip Technology Inc. 24C02C 8.0 READ OPERATION 8.2 Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24C02C as part of a write operation. After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24C02C will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24C02C discontinues transmission (Figure 8-2). After this command, the internal address counter will point to the address location following the one that was just read. Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 8.1 Current Address Read The 24C02C contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the 24C02C issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24C02C discontinues transmission (Figure 8-1). FIGURE 8-1: 8.3 S T A R T SDA line S Control Byte S T O P Data A C K FIGURE 8-2: To provide sequential reads, the 24C02C contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address FF to address 00. P Bus Activity N O A C K RANDOM READ Bus Activity Master S T A R T Control Byte S T A R T Word Address (n) S S T O P Data (n) P A C K A C K Bus Activity Bus Activity Master Control Byte S SDA line FIGURE 8-3: Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24C02C transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24C02C to transmit the next sequentially addressed 8-bit word (Figure 8-3). CURRENT ADDRESS READ Bus Activity Master Random Read A C K N O A C K SEQUENTIAL READ Control Byte Data n Data n + 1 Data n + 2 S T O P Data n + X P SDA line Bus Activity © 2008 Microchip Technology Inc. A C K A C K A C K A C K N O A C K DS21202J-page 11 24C02C 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC (3.90 mm) XXXXXXXT XXXXYYWW NNN 8-Lead TSSOP Example: 24C02CI SN e3 0527 13F Example: 4C2C TYWW I527 NNN 13F XXXXT YWWNNN 8-Lead 2x3 DFN XXX YWW NN 8-Lead 2x3 TDFN DS21202J-page 12 24C02C I/P e3 13F 0527 XXXX 8-Lead MSOP XXX YWW NN Example: Example: 4C2CI 52713F Example: 2P7 527 13 Example: AP7 527 13 © 2008 Microchip Technology Inc. 24C02C 1st Line Marking Codes Part Number DFN TSSOP 24C02C Note: TDFN MSOP 4C2C 4C2CT I Temp. E Temp. I Temp. E Temp. 2P7 2P8 AP7 AP8 T = Temperature grade (I, E) Legend: XX...X T Y YY WW NNN e3 Note: Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. © 2008 Microchip Technology Inc. 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