24CW320T-I/ST

24CW16X/24CW32X/24CW64X/24CW128X 16K-128K I2C Serial EEPROM with Software Write Protection Family Data Sheet Device Selection Table Part Number Density Page Size VCC Range Package Temp. Ranges 24CW16X 16-Kbit 32-byte 1.6-5.5 SN, OT, ST, MUY I 24CW32X 32-Kbit 32-byte 1.6-5.5 SN, OT, ST, MUY I 24CW64X 64-Kbit 32-byte 1.6-5.5 SN, OT, ST, MUY, CS0, CS1 I 128-Kbit 32-byte 1.6-5.5 SN, OT, ST, MUY, CS0, CS1 I 24CW128X Note: ‘X’ in the part number refers to the preset hardware slave address. Refer to Table 3-2 for additional information. Features • 16/32/64/128-Kbit EEPROM: - Internally organized as one 2048/4096/8192/16384 x 8 bit block - Byte or page writes up to 32 bytes - Byte or sequential reads within a block - Self-timed write cycle (5 ms maximum) • High-Speed I2C Interface: - Industry standard: 1 MHz, 400 kHz and 100 kHz - Output slope control to eliminate ground bounce - Schmitt trigger inputs for noise suppression • Programmable Hardware Slave Address Bits: - Configurable via the Hardware Address Register (HAR) • Versatile Data Protection Options: - Software write protection via the Write Protection Register (WPR) • Operating Voltage Range of 1.6V to 5.5V • Low-Power CMOS Technology: - Write current: 1.0 mA maximum at 5.5V - Read current: 1.0 mA maximum at 5.5V, 1 MHz - Standby Current: 1 µA at 5.5V • High Reliability: - More than one million erase/write cycles - Data retention: >200 years - ESD protection: >4000V • RoHS Compliant Package Types (not to scale) 8-Lead SOIC/TSSOP (Top View) 5-Lead SOT23 (Top View) NC 1 8 VCC NC 2 7 NC SCL 1 NC 3 6 SCL VSS 2 Vss 4 5 SDA SDA 3 4 VCC 8-Pad UDFN (Top View) NC 1 8 VCC NC 2 NC 3 VSS 4 7 NC 4-Ball CSP (CS0)(1) (Top View) 6 SCL 5 SDA 4-Ball CSP (CS1)(2) (Top View) VCC VSS VCC SCL SCL SDA SDA VSS Note 1: CS0 CSP ball pitch is 0.4x0.4 mm. 2: CS1 CSP ball pitch is 0.5x0.4 mm. Pin Function Table Name VSS Function Ground Packages SDA Serial Data Pin • 8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN, 5-Lead SOT-23 and Two 4-Ball CSP options SCL Serial Clock Input VCC Supply Voltage  2018 Microchip Technology Inc. 5 NC DS20005772B-page 1 24CW16X/24CW32X/24CW64X/24CW128X Description The 24CW16X/24CW32X/24CW64X/24CW128X (24CW Series) devices provide 16-128 Kbits of Serial EEPROM utilizing an I2C (2-wire) serial interface. The 24CW Series is organized as 2048/4096/8192/16384 bytes of 8 bits each (2-16 Kbytes). The 24CW Series is optimized for use in consumer and industrial applications, where reliable and dependable nonvolatile memory storage is essential. The 24CW Series allows up to eight devices to share a common I2C (2-wire) bus and is capable of operation across a broad voltage range (1.6V to 5.5V). The 24CW Series contains a pair of programmable Configuration registers which allow certain device behaviors to be modified. These registers are the Write Protection Register and the Hardware Address Register. The Write Protection Register (WPR) controls the valid address ranges of the EEPROM array that can be written. This allows the user to select the write protection behavior to be configured for software write protection. The Hardware Address Register (HAR) controls the three hardware slave address bits. These bits determine which device addresses the 24CW Series will Acknowledge. Because the 24CW Series is a 4-pin device, the cascadable feature is controlled by the HAR. Once the desired software write protection and hardware slave address bits are set, these Configuration registers can be permanently locked, thereby preventing any further changes to the device operation. System Configuration Using Serial EEPROMs VCC VCC RPUP(max) = tR(max) 0.8473  CL RPUP(min) = VCC – VOL(max) IOL SCL SDA I2C MCU Programmed as Slave 0 VSS VSS  2018 Microchip Technology Inc. 24CWXXXX VCC Programmed as Slave 1 SDA SCL VSS 24CWXXXX VCC Programmed as Slave 7 SDA SCL VSS 24CWXXXX VCC SDA SCL DS20005772B-page 2 24CW16X/24CW32X/24CW64X/24CW128X Block Diagram Hardware Address Register Memory System Control Module Power-on Reset Generator VCC EEPROM Array 1 page Row Decoder High-Voltage Generation Circuit Write Protection Register Address Register and Counter Column Decoder SCL Data Register DOUT VSS  2018 Microchip Technology Inc. Data & ACK Input/Output Control DIN Start Stop Detector SDA DS20005772B-page 3 24CW16X/24CW32X/24CW64X/24CW128X 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ................................................................................................................... -0.6V to 6.5V Storage temperature ............................................................................................................................... -65°C to +150°C Ambient temperature under bias...............................................................................................................-40°C to +85°C ESD protection on all pins........................................................................................................................................ >4 kV † NOTICE: Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = 1.6V to 5.5V DC CHARACTERISTICS Param. Symbol No. Characteristic Min. Max. Units D1 VIH High-Level Input Voltage VCC X 0.7 VCC + 0.5 V D2 VIL Low-Level Input Voltage -0.6 VCC X 0.3 V D3 VOL Low-Level Output Voltage TA = -40°C to +85°C Test Conditions — 0.4 V IOL = 2.1 mA, VCC = 3.0V — 0.2 V IOL = 0.15 mA, VCC = 1.8V D4 ILI Input Leakage Current — ±1 µA VIN = VSS or VCC D5 ILO Output Leakage Current — ±1 µA VOUT = VSS or VCC D6 CINT Internal Capacitance (all inputs and outputs) — 7 pF TAMB = +25°C, FCLK = 1 MHz, VCC = 5.5V (Note 1) — 0.3 mA VCC = 1.8V, FCLK = 400 kHz — 1 mA VCC = 5.5V, FCLK = 1 MHz — 1 mA VCC = 5.5V, FCLK = 1 MHz — 0.5 µA SCL = SDA = VCC = 1.8V — 1.0 µA SCL = SDA = VCC = 5.5V D7 ICCREAD Operating Current D8 ICCWRITE Operating Current D9 ICCS Note 1: This parameter is not tested, but is ensured by characterization. Standby Current  2018 Microchip Technology Inc. DS20005772B-page 4 24CW16X/24CW32X/24CW64X/24CW128X TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = 1.6V to 5.5V AC CHARACTERISTICS Param. Symbol No. Characteristic Min. Max. Units TA = -40°C to +85°C: Conditions 1 FCLK Clock Frequency — 1000 kHz 1.6V ≤ VCC ≤ 5.5V 2 THIGH Clock High Time 260 — ns 1.6V ≤ VCC ≤ 5.5V 3 TLOW Clock Low Time 500 — ns 1.6V ≤ VCC ≤ 5.5V 4 TR SDA and SCL Rise Time — 1000 ns 1.6V ≤ VCC ≤ 5.5V (Note 1) TF SDA and SCL Fall Time 1.6V ≤ VCC ≤ 5.5V (Note 1) 5 — 300 ns 6 THD:STA Start Condition Hold Time 260 — ns 1.6V ≤ VCC ≤ 5.5V 7 TSU:STA Start Condition Setup Time 260 — ns 1.6V ≤ VCC ≤ 5.5V 8 THD:DAT Data Input Hold Time 0 — ns (Note 2) 9 TSU:DAT Data Input Setup Time 50 — ns 1.6V ≤ VCC ≤ 5.5V 10 TSU:STO Stop Condition Setup Time 260 — ns 1.6V ≤ VCC ≤ 5.5V 11 TAA 12 TBUF 13 TSP 14 TWC Note 1: The rise/fall times must be less than the specified maximums in order to achieve the maximum clock frequencies specified for FCLK. Please refer to the I2C specification for applicable timings. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. Not 100% tested. CB = total capacitance of one bus line in pF. 2: 3: Output Valid from Clock — 450 ns 1.6V ≤ VCC ≤ 5.5V 500 — ns 1.6V ≤ VCC ≤ 5.5V Input Filter Spike Suppression (SDA and SCL pins) — 50 ns (Note 3) Write Cycle Time (byte or page) — 5 ms Bus Free Time: Bus Time must be Free before a New Transmission can Start FIGURE 1-1: BUS TIMING DATA 5 SCL 7 4 D4 2 3 8 10 9 6 SDA In 13 12 11 SDA Out TABLE 1-3: EEPROM CELL PERFORMANCE CHARACTERISTICS Operation Test Condition Min. Max. Write Endurance(1) Units TA = 25°C, 1.6V VCC 5.5V 1,000,000 — Write Cycles Data Retention(1) TA = 55°C 200 — Years Note 1: Performance is determined through characterization and the qualification process.  2018 Microchip Technology Inc. DS20005772B-page 5 24CW16X/24CW32X/24CW64X/24CW128X 1.1 Power-up Requirements and Reset Behavior During a power-up sequence, the VCC supplied to the 24CW Series should monotonically rise from VSS to the minimum VCC level, as specified in Table 1-1, with a slew rate no faster than 0.1V/µs. 1.1.1 DEVICE RESET To prevent write operations or other spurious events from happening during a power-up sequence, the 24CW Series includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and into Standby mode. TABLE 1-4: The system designer must ensure that instructions are not sent to the device until the VCC supply has reached a stable value greater than, or equal to, the minimum VCC level. Additionally, once the VCC is greater than, or equal to, the minimum VCC level, the master must wait at least TPUP before sending the first command to the device. See Table 1-4 for the values associated with these power-up parameters. If an event occurs in the system where the VCC level supplied to the 24CW Series drops below the maximum VPOR level specified, it is recommended that a full-power cycle sequence be performed by first driving the VCC pin to VSS, waiting at least the minimum TPOFF time and then perform a new power-up sequence in compliance with the requirements defined in Section 1.1 “Power-up Requirements and Reset Behavior”. POWER-UP CONDITIONS Symbol Parameter Min. Max. Units TPUP Time Required after VCC is Stable before the Device can Accept Commands 100 — µs VPOR Power-on Reset Threshold Voltage — 1.5 V TPOFF Minimum Time at VCC = 0V between Power Cycles 1 — ms  2018 Microchip Technology Inc. DS20005772B-page 6 24CW16X/24CW32X/24CW64X/24CW128X 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Name 8-Lead SOIC 8-Lead TSSOP 5-Lead SOT23 8-Lead UDFN(1) 4-Ball CSP (CS0)(2) 4-Ball CSP (CS1)(3) NC 1 1 — 1 — — No Connect NC 2 2 — 2 — — No Connect NC 3 3 — 3 — — No Connect VSS 4 4 2 4 A2 B2 Ground SDA 5 5 3 5 B2 B1 Serial Data SCL 6 6 1 6 B1 A2 Serial Clock NC 7 7 5 7 — — No Connect 8 8 4 8 A1 A1 Device Power Supply VCC Note 1: 2: 3: 2.1 Function The exposed pad on this package can be connected to VSS or left floating. CS0 CSP ball pitch is 0.4x0.4 mm. CS1 CSP ball pitch is 0.5x0.4 mm. Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal, therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz and 2 kΩ for 400 kHz and 1 MHz). 2.2 Serial Clock (SCL) This input is used to synchronize the data transfer from and to the device. For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.  2018 Microchip Technology Inc. DS20005772B-page 7 24CW16X/24CW32X/24CW64X/24CW128X 3.0 MEMORY ORGANIZATION 3.1 EEPROM Organization 3.3 The 24CW Series is internally organized as 64/128/256/512 pages of 32 bytes each, depending on the density. 3.2 Device Configuration Registers The 24CW Series contains two Configuration registers that modulate device operation and/or report on the current status of the device. These registers are: • Write Protection Register (WPR) • Hardware Address Register (HAR) Once the device behavior is set as desired, the Configuration registers can be permanently locked (or set to read-only), thereby preventing any subsequent changes. 3.2.1 WRITE PROTECTION REGISTER The Write Protection Register (WPR) allows for modification of the device write protection behavior. Refer to Section 8.2 “Write Protection Register” for additional information of the WPR. 3.2.2 HARDWARE ADDRESS REGISTER The Hardware Address Register (HAR) allows for modification of the hardware slave address bits in the device address byte that the device will Acknowledge. Refer to Section 8.3 “Hardware Address Register” for additional information on the HAR. TABLE 3-1: Device Addressing Communication with the 24CW Series begins with an 8-bit device address byte, comprised of a 7-bit slave address and a Read/Write Select (R/W) bit. Since multiple slave devices can reside on the serial bus, each slave device must have its own unique device address, programmed in the HAR, so that the master can access each device independently. The 7-bit slave address is constructed using two groups of bits. The first four bits contain the Device Type Identifier, followed by three bits containing the hardware slave address bits. The 24CW Series will respond to only specific Device Type Identifiers, as shown in Section 3.3.1 “Valid Device Address Byte Inputs”. The 3-bit hardware slave address is comprised of bits A2, A1 and A0. These bits can be used to expand the address space by allowing up to eight devices with the same Device Type Identifiers on the bus. These hardware slave address bits must correlate with the values programmed in the HAR. The device will respond to all valid device address byte combinations that it receives. 3.3.1 VALID DEVICE ADDRESS BYTE INPUTS The 24CW Series will respond to the Device Type Identifiers, as shown in Table 3-1. 3.3.1.1 Preset Slave Addresses The 24CW Series is preset with a specific slave address. The preset slave address bits are embedded in the base part number, as shown in Table 3-2. TABLE OF VALID DEVICE ADDRESS BYTES Device Type Identifier Hardware Slave Address Access Region Read/Write Select Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EEPROM 1 0 1 0 A2 A1 A0 R/W Configuration Registers 1 0 1 0 A2 A1 A0 R/W Note: The access region is selected according to bit 7 of the first word address byte. Refer to Section 3.3.2 “Word Address Bytes” for additional information.  2018 Microchip Technology Inc. DS20005772B-page 8 24CW16X/24CW32X/24CW64X/24CW128X TABLE 3-2: 3.3.1.2 DEVICE PRESET SLAVE ADDRESS The eighth bit (bit 0) of the device address byte is the Read/Write Select (R/W) bit. A read operation is initiated if this bit is a logic ‘1’ and a write operation is initiated if this bit is a logic ‘0’. Hardware Slave Address Bits Part Number Series 24CWXXXX Read/Write Select Bit A2 A1 A0 0 0 0 24CWXXX1(1,2) 0 0 1 24CWXXX2(1,2) 0 1 0 Upon the successful comparison of the device address byte, the 24CW Series will respond. If a valid comparison is not made, the device will not respond and return to a standby state. (1,2) 24CWXXX3 0 1 1 3.3.2 24CWXXX4(1,2) 1 0 0 24CWXXX5(1,2) 1 0 1 Two 8-bit word address bytes are transmitted to the device immediately following the device address byte. 24CWXXX6(1,2) 1 1 0 24CWXXX7(1,2) 1 1 1 (1) 24CWXXX0 Note 1: 2: WORD ADDRESS BYTES The first word address byte contains the Most Significant bits (MSbs) of the memory array word address to specify which location in the EEPROM to start reading or writing. Note that the number of word address bits depends on the density. Refer to Table 3-3 for details. ‘XXX’ in the part number varies depending on the density. Contact your local sales representative for hardware slave address availability. When accessing the memory array, it is required that bit 7 of the word address byte be set to a logic ‘0’. When accessing the Configuration registers, it is required that bit 7 of the first word address byte be set to a logic ‘1’. Refer to Table 3-3 for details. Next, the second word address byte is sent to the device which provides the remaining eight bits of the word address (A7 through A0). Refer to Table 3-4 for details. TABLE 3-3: FIRST WORD ADDRESS BYTE Memory Region 16-Kbit EEPROM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 x x x x A10 A9 A8 32-Kbit EEPROM 0 x x x A11 A10 A9 A8 64-Kbit EEPROM 0 x x A12 A11 A10 A9 A8 128-Kbit EEPROM 0 x A13 A12 A11 A10 A9 A8 Configuration Registers 1 x x x x x x x TABLE 3-4: SECOND WORD ADDRESS BYTE Memory Region Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0 32-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0 64-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0 128-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0 x x x x x x x x Configuration Registers(1) Note 1: When accessing the Configuration registers, the second word address byte must be transmitted to the device despite containing only don’t care values.  2018 Microchip Technology Inc. DS20005772B-page 9 24CW16X/24CW32X/24CW64X/24CW128X 4.0 FUNCTIONAL DESCRIPTION The 24CW Series supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24CW Series works as a slave. Both master and slave can operate as a transmitter or receiver, but the master determines which mode is activated. 5.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 5-1). 5.1 Bus Not Busy (A) Both data and clock lines remain high. 5.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 5.3 5.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master. 5.5 Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master must generate an extra clock pulse, which is associated with this Acknowledge bit. See Figure 5-2 for Acknowledge timing. Note: The 24CW Series does not generate any Acknowledge bits if an internal programming cycle is in progress. A device that Acknowledges must pull down the SDA line during the Acknowledge clock pulse, in such a way, that the SDA line is stable low during the high period of the Acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During read operations, the master must signal an end of data to the slave by NOT generating an Acknowledge (NACK) bit on the last byte that has been clocked out of the slave. In this case, the slave (24CW Series) will leave the data line high to enable the master to generate the Stop condition. Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition. FIGURE 5-1: (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA  2018 Microchip Technology Inc. Data Allowed to Change Stop Condition DS20005772B-page 10 24CW16X/24CW32X/24CW64X/24CW128X FIGURE 5-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 Data from Transmitter SDA Standby Mode 3 Receiver must release the SDA line at this point so the transmitter can continue sending data. 5.7 The 24CW Series features a low-power Standby mode which is enabled when any one of the following occurs: Software Reset After an interruption in protocol, power loss or system Reset, any 2-wire device can be protocol reset by clocking SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until SDA is released by the EEPROM will vary. The Software Reset sequence should not take more than nine dummy clock cycles. Note that the Software Reset sequence will not interrupt the internal write cycle and only resets the I2C interface. • A valid power-up sequence is performed (see Section 1.1 “Power-up Requirements and Reset Behavior”). • A Stop condition is received by the device unless it initiates an internal write cycle (see Section 6.0 “Write Operations”). • At the completion of an internal write cycle (see Section 6.0 “Write Operations”). • An unsuccessful match of the Device Type Identifier or hardware slave address in the device address byte occurs (see Section 3.3 “Device Addressing”). • The master does not Acknowledge the receipt of data read out from the device; instead, it sends a NACK response.(see Section 7.0 “Read Operations”). FIGURE 5-3: 2 Data from Transmitter Transmitter must release the SDA line at this point, allowing the receiver to pull the SDA line low, to Acknowledge the previous eight bits of data. 5.6 1 Once the Software Reset sequence is complete, new protocol can be sent to the device by sending a Start condition, followed by the protocol. Figure 5-3 illustrates the Software Reset sequence. In the event that the device is still non-responsive, or remains active on the SDA bus, a power cycle must be used to reset the device (see Section 1.1.1 “Device Reset”). SOFTWARE RESET Dummy Clock Cycles SCL 1 2 3 8 SDA Released by EEPROM 9 Device is Software Reset SDA  2018 Microchip Technology Inc. DS20005772B-page 11 24CW16X/24CW32X/24CW64X/24CW128X 6.0 Upon receipt of the proper device address and word address bytes, the EEPROM will send an Acknowledge. The device will then be ready to receive the first 8-bit data byte. Following the receipt of the data byte, the EEPROM will respond with an Acknowledge. The addressing device, such as a master, must then terminate the write operation with a Stop condition. At that time, the EEPROM will enter an internally self-timed write cycle, which will be completed within TWC, while the data byte is being programmed into the nonvolatile EEPROM. All inputs are disabled during this write cycle and the EEPROM will not respond until the write operation is complete. WRITE OPERATIONS All write operations for the 24CW Series begin with the master sending a Start condition, followed by a device address byte with the R/W bit set to a logic ‘0’, and then by the word address bytes. The data value(s) to be written to the device immediately follows the word address bytes. 6.1 Byte Write The 24CW Series supports the writing of a single 8-bit byte. Selecting a data byte in the 24CW Series requires a two-byte word address with the MSb set to a logic ‘0’. Note that some word address bits are ignored and the number of ignored bits depends on the device density. FIGURE 6-1: If an attempt is made to write to a write-protected portion of the array, no data will be written and the device will immediately accept a new command. BYTE WRITE 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A8 0 SCL Device Address Byte SDA 1 0 1 A2 0 A1 Word Address – Byte 0 A0 0 0 0 MSB A13 A12 A11 A10 A9 x MSB Start by Master ACK from Slave 1 2 3 4 5 6 7 8 9 1 ACK from Slave 2 3 Word Address – Byte 1 A7 A6 A5 A4 A3 A2 4 5 6 7 8 9 D2 D1 D0 0 Data Byte A1 A0 0 MSB D7 D6 D5 D4 D3 MSB ACK from Slave Note 1: 2: 3: ACK from Slave Stop by Master The A13, A12 and A11 word address bits are don’t care bits on the 24CW16X. The A13 and A12 word address bits are don’t care bits on the 24CW32X. The A13 word address bit is a don’t care bit on the 24CW64X.  2018 Microchip Technology Inc. DS20005772B-page 12 24CW16X/24CW32X/24CW64X/24CW128X 6.2 When the incremented word address reaches the page boundary, the address counter will roll over to the beginning of the same page. Page Write A page write operation allows up to 32 bytes to be written in the same write cycle, provided all bytes are in the same page of the memory array. Partial page writes of less than 32 bytes are also allowed. Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at the addresses that are integer multiples of [page size – 1]. If a page write operation attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Note: A page write is initiated the same way as a byte write, but the master does not send a Stop condition after the first data byte is clocked in. Instead, after the EEPROM Acknowledges receipt of the first data byte, the master can transmit up to 31 additional data bytes. The EEPROM will respond with an ACK after each data byte is received. Once all data to be written has been sent to the device, the master must issue a Stop condition (see Figure 6-2). Once the Stop condition is received, an internal write cycle will begin. If an attempt is made to write to a write-protected portion of the array, no data will be written and the device will immediately accept a new command. The lower five bits of the word address are internally incremented following the receipt of each data byte. The higher order address bits are not incremented and retain the memory page location. FIGURE 6-2: PAGE WRITE 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL Device Address Byte SDA Start by Master 1 0 1 Word Address – Byte 0 0 A2 A1 A0 0 0 MSB 0 x A13 A12 A11 A10 A9 A8 0 MSB MSB ACK from Slave 1 2 3 4 5 6 7 8 9 Word Address – Byte 1 1 ACK from Slave 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Data Byte (n+x), Max. of 32 without Roll Over Data Byte (n) A7 A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 MSB MSB MSB ACK from Slave Note 1: 2: 3: ACK from Slave ACK from Slave Stop by Master The A13, A12 and A11 word address bits are don’t care bits on the 24CW16X. The A13 and A12 word address bits are don’t care bits on the 24CW32X. The A13 word address bit is a don’t care bit on the 24CW64X.  2018 Microchip Technology Inc. DS20005772B-page 13 24CW16X/24CW32X/24CW64X/24CW128X 6.3 Write Cycle Timing The length of the self-timed write cycle, or TWC, is defined as the amount of time from the Stop condition that begins the internal write operation, to the Start condition of the first device address byte sent to the 24CW Series that it subsequently responds to with an ACK (see Figure 6-3). During the internally self-timed write cycle, any attempts to read from, or write to, the memory array will not be processed. FIGURE 6-3: SCL WRITE CYCLE TIMING 8 9 9 Data Word n SDA D0 ACK ACK First Acknowledge from the device to a valid device address sequence after write cycle is initiated. The minimum TWC can only be determined through the use of an ACK polling routine. TWC Stop Condition  2018 Microchip Technology Inc. Start Condition Stop Condition DS20005772B-page 14 24CW16X/24CW32X/24CW64X/24CW128X 6.4 Acknowledge Polling Since the device will not Acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write operation has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the device address byte for a write operation (R/W = 0). If the device is still busy with the write cycle, then a NACK will be returned. If a NACK is returned, then the Start bit and device address byte must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write operation. See Figure 6-4 for the flow diagram. Note: If the user is polling after writing to the Hardware Address Register (HAR), the user must send the new hardware slave address to determine whether the write cycle is complete. If the 24CW Series doesn’t ACK the new hardware slave address after the maximum write cycle time (TWC), the write to the HAR was not successful. FIGURE 6-4: ACKNOWLEDGE POLLING FLOW Send Write Operation Send Stop Condition to Initiate Write Cycle Send Start Send Device Address byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation  2018 Microchip Technology Inc. DS20005772B-page 15 24CW16X/24CW32X/24CW64X/24CW128X 6.5 Write Protection The 24CW Series write protection is controlled via the Write Protection Register (WPR). The 24CW Series is segmented into four different memory zones, which allows the user to select which of the zones will be software write-protected. The protection behavior can be made permanent by locking the Configuration registers. For additional information on the Write Protection Register, see Section 8.2 “Write Protection Register”. TABLE 6-1: 24CW SERIES SOFTWARE WRITE PROTECTION Protected Address Range Protection Level 24CW16X 24CW32X 24CW64X 24CW128X Upper 1/4 0600h-07FFh 0C00h-0FFFh 1800h-1FFFh 3000h-3FFFh Upper 1/2 0400h-07FFh 0800h-0FFFh 1000h-1FFFh 2000h-3FFFh Upper 3/4 0200h-07FFh 0400h-0FFFh 0800h-1FFFh 1000h-3FFFh Entire Array 0000h-07FFh 0000h-0FFFh 0000h-1FFFh 0000h-3FFFh  2018 Microchip Technology Inc. DS20005772B-page 16 24CW16X/24CW32X/24CW64X/24CW128X 7.0 A current address read operation will output data according to the location of the internal Address Pointer. This is initiated with a Start condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The device will ACK this sequence and the current address data byte is serially clocked out on the SDA line. All types of read operations will be terminated if the master does not respond with an ACK (it NACKs) during the ninth clock cycle, which will force the device into Standby mode. After the NACK response, the master may send a Stop condition to complete the protocol or it can send a Start condition to begin the next sequence. READ OPERATIONS Read operations are initiated the same way as write operations, with the exception that the Read/Write Select (R/W) bit in the device address byte must be a logic ‘1’. There are three read operations: • Current Address Read • Random Address Read • Sequential Read 7.1 Current Address Read The 24CW Series contains an internal Address Pointer that maintains the word address of the last byte accessed, internally incremented by one. Therefore, if the previous read access was to address ‘n’ (n is any legal address), the next current address read operation would access data from address n+1. FIGURE 7-1: CURRENT ADDRESS READ 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D2 D1 D0 1 SCL Device Address Byte SDA 1 0 1 0 A2 A1 Data Byte (n) A0 1 0 MSB Start by Master  2018 Microchip Technology Inc. D7 D6 D5 D4 D3 MSB ACK from Slave NACK Stop from by Master Master DS20005772B-page 17 24CW16X/24CW32X/24CW64X/24CW128X 7.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address, with the MSb set to logic ‘0’, to the 24CW Series as part of a write operation (R/W bit set to ‘0’). After the word address is sent, the master generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then, the master issues the device address byte again, but with the R/W bit set to a ‘1’. The 24CW Series will then issue an Acknowledge and transmit the 8-bit data byte. The master will not Acknowledge the transfer, but does generate a Stop condition which causes the 24CW Series to discontinue transmission (Figure 7-2). After a random read operation, the internal Address Pointer will point to the last word address location, incremented by one. FIGURE 7-2: RANDOM READ 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL Device Address Byte SDA 1 0 MSB 1 0 A2 A1 A0 0 Start by Master 0 0 x A13 A12 A11 A10 A9 A8 0 A7 A6 A5 A4 A3 A2 A1 A0 0 MSB MSB 2 3 4 5 6 7 8 9 1 2 Device Address Byte 1 Start by Master 0 MSB 1 ACK from Slave ACK from Slave ACK from Slave 1 Note 1: 2: 3: Word Address – Byte 1 Word Address – Byte 0 0 A2 A1 A0 1 3 4 5 6 7 8 9 Data Byte n 0 D7 D6 D5 D4 D3 D2 D1 D0 1 MSB ACK from Slave NACK from Slave Stop by Master The A13, A12 and A11 word address bits are don’t care bits on the 24CW16X. The A13, A12 word address bits are don’t care bits on the 24CW32X. The A13 word address bit is a don’t care bit on the 24CW64X.  2018 Microchip Technology Inc. DS20005772B-page 18 24CW16X/24CW32X/24CW64X/24CW128X 7.3 All types of read operations will be terminated if the master does not respond with an ACK (it NACKs) during the ninth clock cycle, which will force the device into Standby mode. After the NACK response, the master may send a Stop condition to complete the protocol or it can send a Start condition to begin the next sequence. Sequential Read A sequential read is initiated by either a current address read or a random read. After the master receives a data byte, the master responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment the word address and serially clock out the sequential data byte. When the maximum memory address is reached, the internal Address Pointer will automatically roll over from the end of the array to word address, 0000h, if the master Acknowledges the byte received from the end of the array. FIGURE 7-3: SEQUENTIAL READ 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL Device Address Byte SDA 1 0 MSB 1 Word Address – Byte 0 0 A2 A1 A0 0 Start by Master 0 Word Address – Byte 1 0 x A13 A12 A11 A10 A9 A8 0 A7 A6 A5 A4 A3 A2 A1 A0 0 MSB MSB 1 2 3 4 5 6 7 8 9 1 2 Device Address Byte 1 0 MSB 1 3 4 5 6 7 3 0 A2 A1 A0 1 4 5 6 7 9 1 2 0 8 9 3 4 5 6 7 8 9 Data Byte (n+1) D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 MSB MSB ACK from Master ACK from Master ACK from Slave 2 8 Data Byte (n) Start by Master 1 ACK from Slave ACK from Slave ACK from Slave 1 Device Byte (n+2) 2 3 4 5 6 7 8 9 1 Data Byte (n+3) 2 3 4 5 6 7 8 9 Data Byte (n+x) D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 MSB MSB MSB ACK from Master Note 1: ACK from Master Stop by NACK Master from Master The A13, A12 and A11 word address bits are don’t care bits on the 24CW16X. 2: The A13 and A12 word address bit are don’t care bits on the 24CW32X. 3: The A13 word address bit is a don’t care bit on the 24CW64X.  2018 Microchip Technology Inc. DS20005772B-page 19 24CW16X/24CW32X/24CW64X/24CW128X 8.0 CONFIGURATION REGISTERS The 24CW Series device contains a pair of 8-bit Configuration registers which control software write protection and the hardware slave address. If desired, the Configuration registers can be locked so that the registers are set to read-only and can no longer be modified. This makes the current software write protection and hardware slave address scheme permanent. The Configuration registers are accessed sequentially as Byte 0 and Byte 1, as shown in Table 8-1. TABLE 8-1: CONFIGURATION REGISTERS Memory Region Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write Protection Register 0 — WRTE CCLK — WPRE WPB1 WPB0 CRLB Hardware Address Register 1 — HWRE A0CK — — A2 A1 A0 8.1 Accessing the Configuration Registers The value of the Configuration registers can be determined by executing a random read sequence, as shown in Section 8.5 “Reading the Configuration Registers”. Changing the value of the Configuration registers is accomplished with a byte write sequence with the requirements outlined in Section 8.4 “Writing to the Configuration Registers”. Accessing these registers requires the use of ‘1010b’ (Ah) as the Device Type Identifier in the device address byte. Following the Device Type Identifier is the hardware slave address bits for which the values are determined by what is currently programmed in the HAR (see Section 8.3 “Hardware Address Register”). Finally, bit 0 is the Read/Write Select (R/W) bit, where a logic ‘1’ is used for reading and logic ‘0’ is used for writing. See Table 3-1 for additional information.  2018 Microchip Technology Inc. Note: The hardware slave address bit values are initially factory preset but can be changed by the user. These bit values must match the current device configuration to receive an Acknowledge. When accessing the Configuration registers, the word address must be sent to the device. All bits in the word address are ignored, except for the MSb which must be set to logic ‘1’. Refer to Table 3-3 and Table 3-4 for additional information. DS20005772B-page 20 24CW16X/24CW32X/24CW64X/24CW128X 8.2 Write Protection Register The Write Protection Register (WPR) is Byte 0 of the sequential Configuration registers. The Write Protection Register format can be seen in Register 8-1. REGISTER 8-1: WRITE PROTECTION REGISTER – BYTE 0 U-0 W-0 W-0 U-0 R/W R/W R/W R/W — WRTE CCLK — WPRE WPB1 WPB0 CRLB bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 WRTE: Configuration Registers Write bit 1 = Configuration registers are writable 0 = Configuration register writes are ignored bit 5 CCLK: Configuration Registers Check Lock bit Must match the CRLB bit when writing to the Configuration registers. bit 4 Unimplemented: Read as ‘0’ bit 3 WPRE: Write Protection Register Enable bit 1 = Write protection is set by the WPB bits 0 = No software write protection is enabled (Default) bit 2-1 WPB: Write-Protect Block bits If WPRE = 1: 11 = Entire EEPROM is write-protected 10 = Upper 3/4 of EEPROM is write-protected 01 = Upper 1/2 of EEPROM is write-protected 00 = Upper 1/4 of EEPROM is write-protected If WPRE = 0: Unused (Default). bit 0 CRLB: Configuration Registers Lock bit 1 = Configuration registers will become permanently locked 0 = Configuration registers can be written to (Default) x = Bit is unknown Configuration Registers Write bit (WRTE): This bit must be set to a logic ‘1’ in order to write to the Configuration registers. Failure to set the WRTE bit to a logic ‘1’ will cause the device to ignore the write operation. When reading the WPR, the WRTE bit will always read as logic ‘0’. Write-Protect Block bits (WPB): These bits allow four levels of protection for the memory array, provided that the WPRE bit is set to a logic ‘1’. If the WPRE bit is a logic ‘0’, the state of the WPB bits has no impact on device protection. The protected address ranges can be found in Table 8-2. Configuration Registers Check Lock bit (CCLK): This bit must match the CRLB bit when writing the Configuration registers. If the CCLK bit does not match the CRLB, the device will ignore the write operation. When reading the WPR, the CCLK bit will always read as logic ‘0’. Configuration Registers Lock bit (CRLB): This bit is used to permanently lock the current state of the WPR and HAR. A logic ‘0’ indicates that these registers can be modified, whereas a logic ‘1’ indicates that the WPR and HAR have been locked and can no longer be modified. To safeguard against accidental locking of these registers, the CCLK bit must match the CRLB bit sent to the device. If these bits do not match, the device will ignore the write operation. Write Protection Register Enable bit (WPRE): This bit is used to enable or disable the device software write protection feature. A logic ‘0’ will disable the software write protection feature and a logic ‘1’ will enable software write protection.  2018 Microchip Technology Inc. Note: The Configuration registers cannot be unlocked once they are locked. DS20005772B-page 21 24CW16X/24CW32X/24CW64X/24CW128X 8.2.1 SOFTWARE WRITE PROTECTION The EEPROM array in the 24CW Series will be protected from writing in accordance with the WPB bits value as long as the WPRE bit is set to logic ‘1’. If the WPRE bit is set to logic ‘0’, the WPB bits are ignored and no portion of the EEPROM array will be protected. The combination of these three bits creates five possible levels of protection for the device, as seen in Table 8-2. TABLE 8-2: PROTECTED ADDRESS RANGE Protected Address Range Protection Level WPRE WPB1 WPB0 24CW16X 24CW32X 24CW64X 24CW128X None 0 x x None None None None Upper 1/4 1 0 0 0600h-07FFh 0C00h-0FFFh 1800h-1FFFh 3000h-3FFFh Upper 1/2 1 0 1 0400h-07FFh 0800h-0FFFh 1000h-1FFFh 2000h-3FFFh Upper 3/4 1 1 0 0200h-07FFh 0400h-0FFFh 0800h-1FFFh 1000h-3FFFh Entire Array 1 1 1 0000h-07FFh 0000h-0FFFh 0000h-1FFFh 0000h-3FFFh  2018 Microchip Technology Inc. DS20005772B-page 22 24CW16X/24CW32X/24CW64X/24CW128X 8.3 Hardware Address Register The Hardware Address Register (HAR) is Byte 1 of the sequential Configuration registers. The Hardware Address Register format can be seen in Register 8-2. REGISTER 8-2: HARDWARE ADDRESS REGISTER – BYTE 1 U-0 W-0 W-0 U-0 U-0 R/W R/W R/W — HWRE A0CK — — A2 A1 A0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 HWRE: HAR Write Enable bit 1 = Configuration registers are writable 0 = Configuration register writes are ignored bit 5 A0CK: Hardware Slave Address Check A0 bit Must match A0 bit when writing the Configuration registers. bit 4-3 Unimplemented: Read as ‘0’ bit 2 A2: Hardware Slave Address A2 bit 1 = Hardware slave address bit A2 is set to a logic ‘1’ 0 = Hardware slave address bit A2 is set to a logic ‘0’ bit 1 A1: Hardware Slave Address A1 bit 1 = Hardware slave address bit A1 is set to a logic ‘1’ 0 = Hardware slave address bit A1 is set to a logic ‘0’ bit 0 A0: Hardware Slave Address A0 bit 1 = Hardware slave address bit A0 is set to a logic ‘1’ 0 = Hardware slave address bit A0 is set to a logic ‘0’ HAR Write Enable bit (HWRE): When writing to the HAR, this bit must be set to a logic ‘1’. Failure to set the HWRE bit to a logic ‘1’ will cause the device to ignore the write operation. When reading the HAR, the HWRE bit will always read as logic ‘0’. Hardware Slave Address Check A0 bit (A0CK): This bit must match the A0 bit when writing to the Configuration registers. If the A0CK bit does not match the A0 bit, the device will ignore the write operation. When reading the HAR, the A0CK bit will always read as logic ‘0’.  2018 Microchip Technology Inc. x = Bit is unknown Hardware Slave Address bits (A2, A1, A0): The 3-bit hardware slave address is contained in bits A2, A1 and A0 of the HAR. These bits control the valid values in bit 3 through bit 1 (A2, A1, A0) of the device address byte. Details of the device address byte are found in Section 3.3 “Device Addressing”. Note: If multiple 24CW Series devices are on the same bus, each device must have unique hardware slave addresses to be accessed individually, including programming the HAR. Different preset hardware slave addresses are available. Contact your local sales representative for details. DS20005772B-page 23 24CW16X/24CW32X/24CW64X/24CW128X 8.4 After sending a valid WPR byte, the HAR byte can optionally be sent. If the HAR byte is invalid, the operation will abort, the EEPROM will not Acknowledge any data bytes and the device will not execute the internal write cycle. Refer to Section 8.3 “Hardware Address Register” for valid HAR byte values. Writing to the Configuration Registers When writing to the Configuration registers, a byte write sequence must be sent to the device (see Section 6.1 “Byte Write” for additional information). The MSb of the word address must be set to logic ‘1’ in order to write to the Configuration registers. Sending more than the WPR and HAR bytes to the 24CW Series will cause the write cycle to abort and the contents of the WPR and HAR will not be changed. A valid WPR byte must be provided when writing to the Configuration registers. If the WPR byte is invalid, the operation will abort, the EEPROM will not Acknowledge any data bytes and the device will not execute the internal write cycle. Refer to Section 8.2 “Write Protection Register” for valid WPR byte values. FIGURE 8-1: If a polling routine has been implemented and the user writes new data values to the HAR, the user must send the new hardware slave address for the device to Acknowledge. Note: CONFIGURATION REGISTERS WRITE SEQUENCE 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 x 0 SCL Device Address Byte SDA 1 0 MSB 1 Word Address – Byte 1 Word Address – Byte 0 0 A2 A1 A0 0 Start by Master 0 1 x MSB x x x x x x 2 3 4 5 6 7 8 9 1 2 WPR Byte x x x x x 3 4 5 6 ACK from Slave 7 8 9 x 1 D5 x x D2 D1 D0 0 MSB ACK from Slave  2018 Microchip Technology Inc. x HAR Byte 1 D5 x D3 D2 D1 D0 0 MSB x x MSB ACK from Slave ACK from Slave 1 0 Optional ACK from Slave Stop by Master DS20005772B-page 24 24CW16X/24CW32X/24CW64X/24CW128X 8.5 It is not possible to read the contents of the Configuration registers with a current address read sequence. Due to the sequential nature of the Configuration registers, it is not possible to read only the HAR contents. Reading the Configuration Registers When reading the Configuration registers, a random read sequence must be sent to the device (see Section 7.2 “Random Read” for additional information). The MSb of the word address must be set to logic ‘1’ in order to read the Configuration registers. FIGURE 8-2: The 24CW Series will automatically roll over from the HAR (Byte 1) back to the WPR (Byte 0) if the master continues to Acknowledge the data bytes during the read operation. Note: CONFIGURATION REGISTERS READ SEQUENCE 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 x 0 SCL Device Address Byte SDA 1 0 MSB 1 Word Address – Byte 1 Word Address – Byte 0 0 A2 A1 A0 0 Start by Master 0 1 x MSB x x x x x x ACK from Slave 1 2 3 4 5 6 7 8 9 1 0 A2 A1 A0 1 Start by Master  2018 Microchip Technology Inc. x x MSB 1 2 0 0 MSB ACK from Slave x x x x 3 4 5 6 7 8 9 ACK from Slave 1 2 WPR Contents 0 x ACK from Slave Device Address Byte 1 0 MSB 0 0 3 4 5 6 7 8 9 HAR Contents 0 D3 D2 D1 D0 0 0 0 MSB ACK from Master 0 0 0 D2 D1 D0 1 Optional NACK from Master Stop by Master DS20005772B-page 25 24CW16X/24CW32X/24CW64X/24CW128X 8.6 After sending a valid WPR byte, the HAR byte can optionally be sent. If the HAR byte is invalid, the operation will abort, the EEPROM will not Acknowledge any data bytes and the device will not execute the internal write cycle. Refer to Section 8.3 “Hardware Address Register” for valid HAR byte values. Locking the Configuration Registers The locking mechanism of the Configuration registers is controlled through the CLRB bit found in the WPR byte. When locking the Configuration registers, a byte write sequence must be sent to the device (see Section 6.1 “Byte Write” for additional information). The MSb of the word address must be set to logic ‘1’ in order to write to the Configuration registers. Note: It is possible to send only the WPR byte and lock the Configuration registers by omitting the HAR byte and sending a Stop condition after the WPR byte. The Configuration registers cannot be unlocked once they are locked. Sending more than the WPR and HAR bytes to the 24CW Series will cause the write cycle to abort and the contents of the WPR and HAR will not be changed. A valid WPR byte with the CCLK and CRLB bits set to a logic ‘1’ must be provided when locking the Configuration registers. If the WPR byte is invalid, the operation will abort, the EEPROM will not Acknowledge any data bytes and the device will not execute the internal write cycle. Refer to Section 8.2 “Write Protection Register” for valid WPR byte values. FIGURE 8-3: If the HAR byte is omitted, the hardware slave address will be locked with its current values. Note: CONFIGURATION REGISTER LOCK SEQUENCE 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 x 0 SCL Device Address Byte SDA 1 0 MSB 1 Word Address – Byte 0 0 A2 A1 A0 0 Start by Master 0 1 x MSB x x x x x Word Address – Byte 1 x 2 3 4 5 6 7 8 9 1 2 WPR Byte x 1 MSB 1 x x x x x ACK from Slave x D3 D2 D1 1 3 4 5 6 7 8 9 HAR Byte 0 x 1 D5 x x D2 D1 D0 0 MSB ACK from Slave  2018 Microchip Technology Inc. x x MSB ACK from Slave ACK from Slave 1 0 Optional ACK from Slave Stop by Master DS20005772B-page 26 24CW16X/24CW32X/24CW64X/24CW128X 9.0 DEVICE DEFAULT CONDITION The 24CW Series is delivered with the EEPROM array set to logic ‘1’, resulting in FFh data in all locations of the EEPROM memory array. The Write Protection Register (WPR) is set to 00h and the Hardware Address Register (HAR) is preset in accordance with the ordering code selected. For factory preset hardware slave address bits, other than ‘000b’, contact your local sales representative.  2018 Microchip Technology Inc. DS20005772B-page 27 24CW16X/24CW32X/24CW64X/24CW128X 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 8-Lead 3.9 mm SOIC NNN 5-Lead SOT-23 Example 24CW160 SN1751 017 Example AAER18 301A8 8-Lead 4.4 mm TSSOP XXXX YYWW NNN Legend: XX...X Y YY WW NNN * Note: Example AADJ 1751 017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code These packages are RoHs compliant. The JEDEC designator can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2018 Microchip Technology Inc. DS20005772B-page 28 24CW16X/24CW32X/24CW64X/24CW128X Package Marking Information (Continued) Example 8-Lead 2x3 mm UDFN ADH 808 17 4-Ball 0.4x0.4 mm CSP (CS0) Example X NN 6 17 4-Ball 0.5x0.4 mm CSP (CS1) Example X NN 7 1A 1st Line Marking Codes Part Number CSP (CS0)(1) CSP (CS1)(2) SOIC SOT-23 24CW16 Series 24CW160 24CW32 Series 24CW320 24CW64 Series 24CW640 AAEQ AADL ADJ 6 6 24CW128 Series 24CW1280 AAER AADM ADK 7 7 Note 1: 2: TSSOP UDFN AAEN AADJ ADG — — AAEP AADK ADH — — CS0 CSP ball pitch is 0.4x0.4 mm. CS1 CSP ball pitch is 0.5x0.4 mm.  2018 Microchip Technology Inc. DS20005772B-page 29 24CW16X/24CW32X/24CW64X/24CW128X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2018 Microchip Technology Inc. DS20005772B-page 30 24CW16X/24CW32X/24CW64X/24CW128X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2018 Microchip Technology Inc. DS20005772B-page 31 24CW16X/24CW32X/24CW64X/24CW128X      !"#$% &  ! "# $% &"'"" ($)  % *++&&&!  !+$  2018 Microchip Technology Inc. DS20005772B-page 32 24CW16X/24CW32X/24CW64X/24CW128X 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A A2 0.20 C SEATING PLANE A SEE SHEET 2 C A1 SIDE VIEW Microchip Technology Drawing C04-028D [OT] Sheet 1 of  2018 Microchip Technology Inc. DS20005772B-page 33 24CW16X/24CW32X/24CW64X/24CW128X 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c T L L1 VIEW A-A SHEET 1 Units Dimension Limits Number of Pins N e Pitch e1 Outside lead pitch Overall Height A Molded Package Thickness A2 Standoff A1 E Overall Width E1 Molded Package Width D Overall Length L Foot Length Footprint L1 I Foot Angle c Lead Thickness b Lead Width MIN 0.90 0.89 - 0.30 0° 0.08 0.20 MILLIMETERS NOM 6 0.95 BSC 1.90 BSC 2.80 BSC 1.60 BSC 2.90 BSC 0.60 REF - MAX 1.45 1.30 0.15 0.60 10° 0.26 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091D [OT] Sheet 2 of  2018 Microchip Technology Inc. DS20005772B-page 34 24CW16X/24CW32X/24CW64X/24CW128X 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch C Contact Pad Spacing X Contact Pad Width (X5) Contact Pad Length (X5) Y Distance Between Pads G Distance Between Pads GX Overall Width Z MIN MILLIMETERS NOM 0.95 BSC 2.80 MAX 0.60 1.10 1.70 0.35 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091A [OT]  2018 Microchip Technology Inc. DS20005772B-page 35 24CW16X/24CW32X/24CW64X/24CW128X   '( ( )  '** !"' % &  ! "# $% &"'"" ($)  % *++&&&!  !+$ D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 @" !" A!" E#!7  )(" AA8 8 E E EG H  (  G3 K  L J;>? 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