24AA16H/24LC16BH/24FC16H
16K I2C Serial EEPROM with Half-Array Write-Protect
Device Selection Table
Part Number
VCC Range
Max. Clock Frequency
400 kHz
Temp. Ranges
Available Packages
I, E
MS, P, SN, MNY, ST, OT
(1)
24AA16H
1.7V-5.5V
24LC16BH
2.5V-5.5V
400 kHz
I, E
MS, P, SN, MNY, ST, OT
24FC16H
1.7V-5.5V
1 MHz
I, E
SN, OT
Note 1: 100 kHz for VCC < 2.5V.
Features
Packages
• Single Supply with Operation Down to 1.7V for
24AA16H and 24FC16H Devices, 2.5V for
24LC16BH Devices
• Low-Power CMOS Technology:
- Read current 1 mA, maximum
- Standby current 1 μA, maximum (I-temp.)
• Two-Wire Serial Interface, I2C Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz, 400 kHz and 1 MHz Compatibility
• Page Write Time: 5 ms, Maximum
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect for Half-Array
(400h-7FFh)
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
• Automotive AEC-Q100 Qualified
• 8-Lead MSOP, 8-Lead PDIP, 8-Lead SOIC,
8-Lead TDFN, 8-Lead TSSOP and 5-Lead
SOT-23
Description
The Microchip Technology Inc. 24XX16H(1) is a 16-Kbit
Electrically Erasable PROM. The device is organized
as eight blocks of 256 x 8-bit memory with a two-wire
serial interface. Its low-voltage design permits
operation down to 1.7V with standby and active
currents of only 1 μA and 1 mA, respectively. The
24XX16H also has a page write capability for up to
16 bytes of data.
Note 1: 24XX16H is used in this document as a
generic
part
number
for
the
24AA16H/24LC16BH/24FC16H devices.
Package Types
8-Lead MSOP/PDIP
(Top View)
A0(1)
11
88
VCC
A1(1)
22
77
A2(1)
33
66
WP
SCL
VSS
44
55
SDA
Note 1:
8-Lead SOIC/TSSOP
(Top View)
A0(1)
A1(1)
1
8
VCC
2
7
WP
A2(1)
3
6
SCL
VSS
4
5
SDA
5-Lead SOT-23
(Top View)
SCL
1
VSS
2
SDA
3
5
4
8-Lead TDFN
(Top View)
WP
A0(1) 1
8
7
WP
VCC
A1(1) 2
A2(1) 3
VSS 4
6
5
SCL
SDA
VCC
Pins A0, A1 and A2 are not used by the 24XX16H (no internal connections).
2008-2019 Microchip Technology Inc.
DS20002118B-page 1
24AA16H/24LC16BH/24FC16H
Block Diagram
WP
I/O
Control
Logic
Memory
Control
Logic
HV Generator
XDEC
EEPROM
Array
Page Latches
I/O
SCL
YDEC
SDA
VCC
VSS
2008-2019 Microchip Technology Inc.
Sense Amp.
R/W Control
DS20002118B-page 2
24AA16H/24LC16BH/24FC16H
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
Symbol
No.
Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC16BH)
Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC16H)
Characteristic
Min.
Typical
Max.
Units
Conditions
D1
VIH
High-Level Input Voltage
0.7 VCC
—
—
V
D2
VIL
Low-Level Input Voltage
—
—
0.3 VCC
V
D3
VHYS
0.05 VCC
—
—
V
Note
D4
VOL
Low-Level Output
Voltage
—
—
0.40
V
IOL = 3.0 mA, VCC = 2.5V
D5
ILI
Input Leakage Current
—
—
±1
μA
VIN = VSS or VCC
D6
ILO
Output Leakage Current
—
—
±1
μA
VOUT = VSS or VCC
D7
CIN,
COUT
Pin Capacitance
(all inputs/outputs)
—
—
10
pF
VCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
D8
ICCWRITE Operating Current
—
—
3
mA
VCC = 5.5V, SCL = 400 kHz
D9
ICCREAD
—
—
1
mA
VCC = 5.5V, SCL = 400 kHz
D10
ICCS
—
—
1
μA
SDA = SCL = VCC
WP = VSS, I-Temp.
—
—
3
μA
SDA = SCL = VCC
WP = VSS, E-Temp. (24FC16H)
—
—
5
μA
SDA = SCL = VCC
WP = VSS, E-Temp.
(24LC16BH)
Note:
Hysteresis of Schmitt
Trigger Inputs
Standby Current
This parameter is periodically sampled and not 100% tested.
2008-2019 Microchip Technology Inc.
DS20002118B-page 3
24AA16H/24LC16BH/24FC16H
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
Symbol
No.
1
FCLK
2
THIGH
3
TLOW
4
TR
5
TF
Characteristic
Clock Frequency
Clock High Time
Clock Low Time
SDA and SCL Rise Time
SDA and SCL Fall Time
THD:STA Start Condition Hold Time
6
TSU:STA Start Condition Setup
Time
7
8
THD:DAT Data Input Hold Time
9
TSU:DAT Data Input Setup Time
TSU:STO Stop Condition Setup
Time
10
TSU:WP
11
WP Setup Time
THD:WP WP Hold Time
12
13
TAA
Note 1:
2:
3:
4:
Output Valid from Clock
Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC16BH)
Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC16H)
Min.
Max.
Units
Conditions
—
400
kHz
2.5V ≤ VCC ≤ 5.5V
—
100
kHz
1.7V ≤ VCC < 2.5V (24AA16H)
1.7V ≤ VCC ≤ 5.5V (24FC16H)
—
1000
kHz
600
—
ns
2.5V ≤ VCC ≤ 5.5V
4000
—
ns
1.7V ≤ VCC < 2.5V (24AA16H)
260
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H)
1300
—
ns
2.5V ≤ VCC ≤ 5.5V
4700
—
ns
1.7V ≤ VCC < 2.5V (24AA16H)
500
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H)
—
300
ns
2.5V ≤ VCC ≤ 5.5V (Note 1)
—
1000
ns
1.7V ≤ VCC < 2.5V (24AA16H) (Note 1)
—
1000
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H) (Note 1)
—
300
ns
Note 1
600
—
ns
2.5V ≤ VCC ≤ 5.5V
4000
—
ns
1.7V ≤ VCC < 2.5V (24AA16H)
250
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H)
600
—
ns
2.5V ≤ VCC ≤ 5.5V
4700
—
ns
1.7V ≤ VCC < 2.5V (24AA16H)
250
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H)
0
—
ns
Note 2
100
—
ns
2.5V ≤ VCC ≤ 5.5V
250
—
ns
1.7V ≤ VCC < 2.5V (24AA16H)
50
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H)
600
—
ns
2.5V ≤ VCC ≤ 5.5V
4000
—
ns
1.7V ≤ VCC < 2.5V (24AA16H)
250
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H)
600
—
ns
2.5V ≤ VCC ≤ 5.5V
4000
—
ns
1.7V ≤ VCC < 2.5V (24AA16H)
600
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H)
1300
—
ns
2.5V ≤ VCC ≤ 5.5V
4700
—
ns
1.7V ≤ VCC < 2.5V (24AA16H)
600
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H)
—
900
ns
2.5V ≤ VCC ≤ 5.5V (Note 2)
—
3500
ns
1.7V ≤ VCC < 2.5V (24AA16H) (Note 2)
—
450
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H) (Note 2)
Characterized but not 100% tested.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
CB = total capacitance of one bus line in pF.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
2008-2019 Microchip Technology Inc.
DS20002118B-page 4
24AA16H/24LC16BH/24FC16H
AC CHARACTERISTICS (Continued)
Param.
Symbol
No.
14
TBUF
15
TOF
16
Characteristic
Min.
Max.
Units
Bus Free Time: The time
the bus must be free
before a new transmission can start
1300
—
ns
2.5V ≤ VCC ≤ 5.5V
4700
—
ns
1.7V ≤ VCC < 2.5V (24AA16H)
500
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H)
250
ns
2.5V ≤ VCC ≤ 5.5V
(Notes 1, 2 and 3)
—
250
ns
1.7V ≤ VCC < 2.5V (24AA16H)
(Notes 1, 2 and 3)
Input Filter Spike
Suppression
(SDA and SCL pins)
—
50
ns
Note 1
—
100
ns
1.7V ≤ VCC ≤ 5.5V (24FC16H) (Note 1)
Write Cycle Time
(byte or page)
—
5
ms
1,000,000
—
Output Fall Time from VIH 20+0.1CB
Minimum to VIL Maximum
TSP
17
TWC
18
Endurance
Note 1:
2:
3:
4:
cycles 25°C, 5.5V, Page Mode (Note 4)
BUS TIMING DATA
5
SDA
IN
Conditions
Characterized but not 100% tested.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
CB = total capacitance of one bus line in pF.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
FIGURE 1-1:
SCL
Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC16BH)
Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC16H)
7
3
4
D3
2
8
10
9
6
16
14
13
SDA
OUT
WP
2008-2019 Microchip Technology Inc.
(protected)
(unprotected)
11
12
DS20002118B-page 5
24AA16H/24LC16BH/24FC16H
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name
MSOP
PDIP
SOIC
TDFN(1)
TSSOP
SOT-23
A0
1
1
1
1
1
—
Not Connected
A1
2
2
2
2
2
—
Not Connected
A2
3
3
3
3
3
—
Not Connected
VSS
4
4
4
4
4
2
Ground
SDA
5
5
5
5
5
3
Serial Address/Data I/O
SCL
6
6
6
6
6
1
Serial Clock
WP
7
7
7
7
7
5
Write-Protect Input
8
8
8
8
8
4
Power Supply
VCC
Note 1:
2.1
Description
The exposed pad on the TDFN package can be connected to VSS or left floating.
A0, A1, A2
2.3
Serial Clock (SCL)
The A0, A1 and A2 pins are not used by the 24XX16H.
They may be left floating or tied to either VSS or VCC.
The SCL input is used to synchronize the data transfer
to and from the device.
2.2
2.4
Serial Address/Data Input/Output
(SDA)
The SDA input is a bidirectional pin used to transfer
addresses and data into and out of the device. Since
it is an open-drain terminal, the SDA bus requires a
pull-up resistor to VCC (typical 10 kΩ for 100 kHz,
2 kΩ for 400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2008-2019 Microchip Technology Inc.
Write-Protect (WP)
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to VCC, write operations are inhibited. Half of the
memory will be write-protected (400h-7FFh). Read
operations are not affected.
DS20002118B-page 6
24AA16H/24LC16BH/24FC16H
3.0
FUNCTIONAL DESCRIPTION
The 24XX16H supports a bidirectional, two-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, while a
device receiving data is defined as a receiver. The bus
has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access
and generates the Start and Stop conditions, while the
24XX16H works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 4-1:
(A)
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (although only the last sixteen
will be stored when doing a write operation). When an
overwrite does occur, it will replace data based on the
first-in first-out (FIFO) principle.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
4.4
The 24XX16H does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the Acknowledge-related clock pulse.
Moreover, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX16H) will leave the data
line high to enable the master to generate the Stop
condition.
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SCL
SDA
2008-2019 Microchip Technology Inc.
Data
Allowed
to Change
Stop
Condition
DS20002118B-page 7
24AA16H/24LC16BH/24FC16H
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists of a 4-bit control code. For the 24XX16H, this
is set as ‘1010’ binary for read and write operations.
The next three bits of the control byte are the
block-select bits (B2, B1, B0). They are used by the
master device to select which of the eight 256-word
blocks of memory are to be accessed. These bits, in
effect, are the three Most Significant bits of the word
address. It should be noted that the protocol limits the
size of the memory to eight blocks of 256 words,
therefore, the protocol can support only one 24XX16H.
per system. The combination of the 4-bit control code
and the next three bits are called the slave address.
The last bit of the control byte is the Read/Write (R/W)
bit and it defines the operation to be performed. When
set to ‘1’, a read operation is selected. When set to ‘0’,
a write operation is selected. Following the Start
condition, the 24XX16H monitors the SDA bus,
checking the device type identifier being transmitted.
Upon receiving a valid slave address and the R/W bit,
the slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX16H will select a read or write operation.
Operation
Control
Code
Block Select
R/W
Read
1010
Block Address
1
Write
1010
Block Address
0
FIGURE 5-1:
CONTROL BYTE
ALLOCATION
Read/Write Bit
Block
Select
Bits
Control Code
S
1
0
1
0
B2 B1 B0 R/W ACK
Slave Address
Acknowledge Bit
Start Bit
The next byte received defines the address of the first
data byte within the selected block (Figure 5-2). The
word address byte uses all eight bits.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
1
0
1
0
Control
Code
2008-2019 Microchip Technology Inc.
B2 B1 B0 R/W
Word Address Byte
A7
•
•
•
•
•
•
A0
Block
Select
Bits
DS20002118B-page 8
24AA16H/24LC16BH/24FC16H
6.0
WRITE OPERATION
6.1
Byte Write
6.2
Following the Start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic-low, are placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24XX16H.
After receiving another Acknowledge signal from the
24XX16H, the master device will transmit the data word
to be written into the addressed memory location. The
24XX16H acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle, and, during this time, the 24XX16H will not
generate Acknowledge signals (Figure 6-1).
Page Write
The write control byte, word address and first data byte
are transmitted to the 24XX16H in the same way as in
a byte write. However, instead of generating a Stop
condition, the master transmits up to 16 data bytes to
the 24XX16H, which are temporarily stored in the
on-chip page buffer and will be written into the memory
once the master has transmitted a Stop condition.
Upon receipt of each word, the four lower-order
Address Pointer bits, which form the byte counter, are
internally incremented by one. The higher-order
four bits of the word address and bits B2, B1 and B0
remain constant. If the master should transmit more
than 16 words prior to generating the Stop condition,
the Address Pointer will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2).
Note:
6.3
Page write operations are limited to writing bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of page size – 1. If a
page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Write Protection
The WP pin allows the user to write-protect half of the
array (400h-7FFh) when the pin is tied to VCC. If the pin
is tied to VSS, the write protection is disabled.
FIGURE 6-1:
BYTE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
1 0
Word
Address
S
T
O
P
Data
1 0 B2 B1 B0 0
Bus Activity
2008-2019 Microchip Technology Inc.
Block
Select
Bits
P
A
C
K
A
C
K
A
C
K
DS20002118B-page 9
24AA16H/24LC16BH/24FC16H
FIGURE 6-2:
PAGE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S 1 0 1 0 B2 B1B0 0
Bus Activity
Control
Byte
Block
Select
Bits
2008-2019 Microchip Technology Inc.
Word
Address (n)
Data (n + 1)
Data (n)
S
T
O
P
Data (n + 15)
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DS20002118B-page 10
24AA16H/24LC16BH/24FC16H
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally-timed write cycle. ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a write command (R/W = 0). If the device is still
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next read or write
operation. See Figure 7-1 for a flow diagram of this
operation.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
2008-2019 Microchip Technology Inc.
DS20002118B-page 11
24AA16H/24LC16BH/24FC16H
8.0
READ OPERATION
8.3
Sequential reads are initiated in the same way as a
random read or current read, except that once the
24XX16H transmits the first data byte, the master
issues an Acknowledge (as opposed to a Stop condition in a random read). This directs the 24XX16H to
transmit the next sequentially addressed 8-bit word
(Figure 8-3).
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
To provide sequential reads the 24XX16H contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
The 24XX16H contains an Address Pointer that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the previous access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 24XX16H
issues an Acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24XX16H
discontinues transmission (Figure 8-1).
8.2
Sequential Read
8.4
Noise Protection
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX16H as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the Acknowledge. This
terminates the write operation, but not before the internal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24XX16H will then issue an Acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition
and the 24XX16H discontinues transmission
(Figure 8-2).
FIGURE 8-1:
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
SDA Line
S 1 0 1 0 B2 B1 B0 1
Bus Activity
2008-2019 Microchip Technology Inc.
Control
Byte
Block
Select
Bits
S
T
O
P
Data (n)
P
A
C
K
N
o
A
C
K
DS20002118B-page 12
24AA16H/24LC16BH/24FC16H
FIGURE 8-2:
Bus Activity
Master
SDA Line
RANDOM READ
S
T
Control
A
Byte
R
T
S 1 0 1 0 B2 B1 B0 0
FIGURE 8-3:
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte
S
T
O
P
P
Data (n)
S 1 0 1 0 B2B1B0 1
A
Block C
Select K
Bits
Bus Activity
S
T
A
R
T
Word
Address (n)
A
C
K
Block
Select
Bits
A
C
K
N
o
A
C
K
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + x)
P
1
A
C
K
2008-2019 Microchip Technology Inc.
A
C
K
A
C
K
A
C
K
N
o
A
C
K
DS20002118B-page 13
24AA16H/24LC16BH/24FC16H
9.0
PACKAGING INFORMATION
9.1
Package Marking Information*
8-Lead MSOP
Example
XXXXXX
YWWNNN
4L16HI
91713F
8-Lead PDIP (300 mil)
Example
XXXXXXXX
XXXXXNNN
YYWW
24LC16BH
I/P e3 13F
1917
8-Lead SOIC (3.90 mm)
Example
XXXXXXXX
XXXXYYWW
24L16BHI
SN e3 1915
NNN
13F
8-Lead 2x3 TDFN
Example
XXX
YWW
NN
AG1
917
13
8-Lead TSSOP
Example
XXXX
4L6H
XYWW
I917
NNN
13F
2008-2019 Microchip Technology Inc.
DS20002118B-page 14
24AA16H/24LC16BH/24FC16H
5-Lead SOT-23 (1-Line Marking)
Example
XXNN
BWNN
5-Lead SOT-23 (2-Line Marking)
Example
Part Number
XXXXYY
WWNNN
AAFB19
1713F
1st Line Marking Codes
TDFN
MSOP
SOT-23
PDIP
SOIC
24AA16H
4A16HT(1)
24AA16H
24AA16HT(1)
AG1
—
24LC16BH
4L16HT(1)
24LC16BH
24L16BHT(1)
AG4
AG5
—
—
24FC16H
—
—
24FC16H
I-Temp.
E-Temp.
TSSOP
I-Temp.
E-Temp.
4A6H
BWNN(2,3)
—
4L6H
5QNN(2,3)
5RNN(2,3)
—
AAFAYY(4)
AAFAYY(4)
Note 1: T = Temperature grade (I, E)
2: NN = Alphanumeric traceability code
3: These parts use the 1-line SOT-23 marking format
4: These parts use the 2-line SOT-23 marking format
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
* Standard OTP marking consists of Microchip part number, year code, week code,
and traceability code.
Note:
For very small packages with no room for the JEDEC® designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2008-2019 Microchip Technology Inc.
DS20002118B-page 15
24AA16H/24LC16BH/24FC16H
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2019 Microchip Technology Inc.
DS20002118B-page 16
24AA16H/24LC16BH/24FC16H
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2019 Microchip Technology Inc.
DS20002118B-page 17
24AA16H/24LC16BH/24FC16H
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2019 Microchip Technology Inc.
DS20002118B-page 18
24AA16H/24LC16BH/24FC16H
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
C
A2
A
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
2008-2019 Microchip Technology Inc.
DS20002118B-page 19
24AA16H/24LC16BH/24FC16H
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
DATUM A
DATUM A
b
b
e
2
e
2
e
Units
Dimension Limits
Number of Pins
N
e
Pitch
Top to Seating Plane
A
Molded Package Thickness
A2
Base to Seating Plane
A1
Shoulder to Shoulder Width
E
Molded Package Width
E1
Overall Length
D
Tip to Seating Plane
L
c
Lead Thickness
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing
eB
§
e
MIN
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
INCHES
NOM
8
.100 BSC
.130
.310
.250
.365
.130
.010
.060
.018
-
MAX
.210
.195
.325
.280
.400
.150
.015
.070
.022
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
2008-2019 Microchip Technology Inc.
DS20002118B-page 20
24AA16H/24LC16BH/24FC16H
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2
2008-2019 Microchip Technology Inc.
DS20002118B-page 21
24AA16H/24LC16BH/24FC16H
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2
2008-2019 Microchip Technology Inc.
DS20002118B-page 22
24AA16H/24LC16BH/24FC16H
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev B
2008-2019 Microchip Technology Inc.
DS20002118B-page 23
24AA16H/24LC16BH/24FC16H
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.15 C
1
2
2X
0.15 C
TOP VIEW
0.10 C
C
(A3)
A
SEATING
PLANE
8X
0.08 C
A1
SIDE VIEW
0.10
C A B
D2
L
1
2
0.10
C A B
NOTE 1
E2
K
N
8X b
e
0.10
0.05
C A B
C
BOTTOM VIEW
Microchip Technology Drawing No. C04-129-MN Rev E Sheet 1 of 2
2008-2019 Microchip Technology Inc.
DS20002118B-page 24
24AA16H/24LC16BH/24FC16H
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Pins
e
Pitch
A
Overall Height
Standoff
A1
Contact Thickness
A3
D
Overall Length
Overall Width
E
Exposed Pad Length
D2
Exposed Pad Width
E2
b
Contact Width
Contact Length
L
Contact-to-Exposed Pad
K
MIN
0.70
0.00
1.35
1.25
0.20
0.25
0.20
MILLIMETERS
NOM
8
0.50 BSC
0.75
0.02
0.20 REF
2.00 BSC
3.00 BSC
1.40
1.30
0.25
0.30
-
MAX
0.80
0.05
1.45
1.35
0.30
0.45
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2
2008-2019 Microchip Technology Inc.
DS20002118B-page 25
24AA16H/24LC16BH/24FC16H
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
8
ØV
C
Y2
EV
Y1
1
2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
1.60
1.50
2.90
0.25
0.85
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing No. C04-129-MN Rev. B
2008-2019 Microchip Technology Inc.
DS20002118B-page 26
24AA16H/24LC16BH/24FC16H
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