24LC00/P

24AA00/24LC00/24C00 128-Bit I2C Bus Serial EEPROM Device Selection Table Package Types Device VCC Range Temp Range 24AA00 1.8-5.5 I NC 1 8 24LC00 2.5-5.5 I NC 2 7 NC 24C00 4.5-5.5 I,E NC 3 6 SCL Vss 4 5 SDA 8-PIN PDIP/SOIC Features • Single Supply with Operation down to 1.8V for 24AA00 Devices, 2.5V for 24LC00 Devices • Low-Power CMOS Technology: - Read current 500 A, typical - Standby current 100 nA, typical • 2-Wire Serial Interface, I2C Compatible • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kHz and 400 kHz Clock Compatibility • Page Write Time 3 ms, Typical • Self-Timed Erase/Write Cycle • ESD Protection >4000V • More than 1 Million Erase/Write Cycles • Data Retention >200 Years • Factory Programming Available • Packages include 8-lead PDIP, SOIC, TSSOP, DFN, TDFN and 5-lead SOT-23 • Pb-Free and RoHS Compliant • Temperature Ranges Available: - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C Description The Microchip Technology Inc. 24AA00/24LC00/ 24C00 (24XX00*) is a 128-bit Electrically Erasable PROM memory organized as 16 x 8 with a 2-wire serial interface. Low-voltage design permits operation down to 1.8 volts for the 24AA00 version, and every version maintains a maximum standby current of only 1 A and typical active current of only 500 A. This device was designed for where a small amount of EEPROM is needed for the storage of calibration values, ID numbers or manufacturing information, etc. The 24XX00 is available in 8-pin PDIP, 8-pin SOIC (3.90 mm), 8-pin TSSOP, 8-pin 2x3 DFN, TDFN and the 5-pin SOT-23 packages. VCC 8-PIN TSSOP NC NC NC VSS 1 2 3 4 8 7 6 5 5-PIN SOT-23 SCL 1 VSS 2 SDA 3 VCC NC SCL SDA DFN/TDFN 5 VCC NC 1 NC 2 4 NC NC 3 VSS 4 8 VCC 7 NC 6 SCL 5 SDA Block Diagram HV Generator I/O Control Logic SDA VCC VSS SCL Memory Control Logic XDEC EEPROM Array YDEC Sense AMP R/W Control *24XX00 is used in this document as a generic part number for the 24AA00/24LC00/24C00 devices.  1996-2018 Microchip Technology Inc. DS20001178J-page 1 24AA00/24LC00/24C00 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS All Parameters apply across the recommended operating ranges unless otherwise noted Parameter TA = -40°C to +85°C, TA = -40°C to +125°C, Industrial (I): Automotive (E) Symbol Min. Max. Units VCC = 1.8V to 5.5V VCC = 4.5V to 5.5V Conditions SCL and SDA pins: High-level input voltage VIH 0.7 VCC — V (Note) Low-level input voltage VIL — 0.3 VCC V (Note) Hysteresis of Schmitt Trigger inputs VHYS .05 VCC — V VCC  2.5V (Note) Low-level output voltage VOL — 0.4 V IOL = 3.0 mA, VCC = 4.5V IOL = 2.1 mA, VCC = 2.5V ILI — ±1 A VIN = VCC or VSS Output leakage current ILO — ±1 A VOUT = VCC or VSS Pin capacitance (all inputs/outputs) CIN, COUT — 10 pF VCC = 5.0V (Note) TA = 25°C, FCLK = 1 MHz Operating current ICC Write — 2 mA VCC = 5.5V, SCL = 400 kHz ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz ICCS — 1 A VCC = 5.5V, SDA = SCL = VCC Input leakage current Standby current Note: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING DATA THIGH TF SCL TSU:STA TLOW SDA IN TR TSP TSU:DAT THD:DAT TSU:STO THD:STA TAA TBUF SDA OUT DS20001178J-page 2  1996-2018 Microchip Technology Inc. 24AA00/24LC00/24C00 TABLE 1-2: AC CHARACTERISTICS All Parameters apply across all recommended operating ranges unless otherwise noted Parameter Industrial (I): Automotive (E): Symbol TA = -40°C to +85°C, VCC = 1.8V to 5.5V TA = -40°C to +125°C, VCC = 4.5V to 5.5V Min Max Units Conditions Clock frequency FCLK — — — 100 100 400 kHz 4.5V Vcc  5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc  5.5V Clock high time THIGH 4000 4000 600 — — — ns 4.5V Vcc  5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc  5.5V Clock low time TLOW 4700 4700 1300 — — — ns 4.5V Vcc  5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc  5.5V SDA and SCL rise time (Note 1) TR — — — 1000 1000 300 ns 4.5V Vcc  5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc  5.5V SDA and SCL fall time TF — 300 ns (Note 1) Start condition hold time THD:STA 4000 4000 600 — — — ns 4.5V Vcc  5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc  5.5V Start condition setup time TSU:STA 4700 4700 600 — — — ns 4.5V Vcc  5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc  5.5V Data input hold time THD:DAT 0 — ns (Note 2) Data input setup time TSU:DAT 250 250 100 — — — ns 4.5V Vcc  5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc  5.5V Stop condition setup time TSU:STO 4000 4000 600 — — — ns 4.5V Vcc  5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc  5.5V Output valid from clock (Note 2) TAA — — — 3500 3500 900 ns 4.5V Vcc  5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc  5.5V 4700 4700 1300 — — — ns 4.5V Vcc  5.5V (E Temp range) 1.8V Vcc 4.5V 4.5V Vcc  5.5V Bus free time: Time the bus must TBUF be free before a new transmission can start Output fall time from VIH minimum to VIL maximum TOF 20+0.1 CB 250 ns (Note 1), CB 100 pF Input filter spike suppression (SDA and SCL pins) TSP — 50 ns (Notes 1, 3) Write cycle time TWC Endurance Note 1: 2: 3: 4: — 4 ms 1M — cycles (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.  1996-2018 Microchip Technology Inc. DS20001178J-page 3 24AA00/24LC00/24C00 2.0 PIN DESCRIPTIONS Pin Function Table PDIP SOIC TSSOP DFN(1) TDFN(1) SOT-23 NC 1, 2, 3, 7 1, 2, 3, 7 1, 2, 3, 7 1, 2, 3, 7 1, 2, 3, 7 4 Not Connected VSS 4 4 4 4 4 2 Ground Name Description SDA 5 5 5 5 5 3 Serial Address/Data I/O SCL 6 6 6 6 6 1 Serial Clock VCC 8 8 8 8 8 5 +1.8V to 5.5V Power Supply Note 1: 2.1 The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating. SDA Serial Data This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 2.2 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. 2.3 Noise Protection The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. DS20001178J-page 4  1996-2018 Microchip Technology Inc. 24AA00/24LC00/24C00 3.0 FUNCTIONAL DESCRIPTION The 24XX00 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the Start and Stop conditions, while the 24XX00 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus Not Busy (A) Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited.  1996-2018 Microchip Technology Inc. DS20001178J-page 5 24AA00/24LC00/24C00 4.5 Acknowledge The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition (Figure 4-2). Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24XX00 does not generate any Acknowledge bits if an internal programming cycle is in progress. FIGURE 4-1: SCL (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (C) (D) Start Condition Address or Acknowledge Valid (C) (A) SDA FIGURE 4-2: Stop Condition Data Allowed to Change ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 SDA 2 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. DS20001178J-page 6 8 9 1 2 3 Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.  1996-2018 Microchip Technology Inc. 24AA00/24LC00/24C00 5.0 DEVICE ADDRESSING After generating a Start condition, the bus master transmits a control byte consisting of a slave address and a Read/Write bit that indicates what type of operation is to be performed. The slave address for the 24XX00 consists of a 4-bit device code ‘1010’ followed by three “don’t care” bits. The last bit of the control byte determines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected (Figure 5-1). The 24XX00 monitors the bus for its corresponding slave address all the time. It generates an Acknowledge bit if the slave address was true and it is not in a programming mode. FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit Device Select Bits S 1 0 1 Don’t Care Bits 0 x x x R/W ACK Slave Address Start Bit Acknowledge Bit  1996-2018 Microchip Technology Inc. DS20001178J-page 7 24AA00/24LC00/24C00 6.0 WRITE OPERATIONS 6.1 Byte Write condition. This initiates the internal write cycle, and during this time the 24XX00 will not generate Acknowledge signals (Figure 6-1). After a byte Write command, the internal address counter will not be incremented and will point to the same address location that was just written. If a Stop bit is transmitted to the device at any point in the Write command sequence before the entire sequence is complete, then the command will abort and no data will be written. If more than 8 data bits are transmitted before the Stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. If more than one data byte is transmitted to the device and a Stop bit is sent before a full eight data bits have been transmitted, then the Write command will abort and no data will be written. The 24XX00 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5V (24AA00 and 24LC00) or 3.8V (24C00) at nominal conditions. Following the Start signal from the master, the device code (4 bits), the “don’t care” bits (3 bits), and the R/W bit (which is a logic low) are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the Address Pointer of the 24XX00. Only the lower four address bits are used by the device, and the upper four bits are “don’t cares.” The 24XX00 will acknowledge the address byte and the master device will then transmit the data word to be written into the addressed memory location. The 24XX00 acknowledges again and the master generates a Stop FIGURE 6-1: BUS ACTIVITY MASTER SDA LINE BYTE WRITE S T A R T S 1 BUS ACTIVITY Control Byte 0 1 0 x x Word Address x x 0 A C K x x S T O P Data P x A C K A C K x = “don’t care” bit DS20001178J-page 8  1996-2018 Microchip Technology Inc. 24AA00/24LC00/24C00 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for flow diagram. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation  1996-2018 Microchip Technology Inc. DS20001178J-page 9 24AA00/24LC00/24C00 8.0 READ OPERATIONS Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX00 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the device issues an acknowledge and transmits the eight-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the device discontinues transmission (Figure 8-1). 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the device as part of a write operation. FIGURE 8-1: 8.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the device transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the device to transmit the next sequentially addressed 8-bit word (Figure 8-3). To provide sequential reads the 24XX00 contains an internal Address Pointer which is incremented by one at the completion of each read operation. This Address Pointer allows the entire memory contents to be serially read during one operation. CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S 10 10 xxx 1 BUS ACTIVITY x = “don’t care” bit DS20001178J-page 10 After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then the master issues the control byte again, but with the R/W bit set to a one. The 24XX00 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the device discontinues transmission (Figure 8-2). After this command, the internal address counter will point to the address location following the one that was just read. Control Byte S T O P Data P A C K N O A C K  1996-2018 Microchip Technology Inc. 24AA00/24LC00/24C00 FIGURE 8-2: RANDOM READ S T BUS ACTIVITY A MASTER R Control Byte Word Address(n) T S 10 10xxx 0 SDA LINE x xxx Control Byte P A C K x = “don’t care” bit FIGURE 8-3: BUS ACTIVITY MASTER S T O P Data (n) S 10 10xxx 1 A C K A C K BUS ACTIVITY S T A R T N O A C K SEQUENTIAL READ Control Byte Data n Data n + 1 Data n + 2 S T O P Data n + x P SDA LINE BUS ACTIVITY A C K  1996-2018 Microchip Technology Inc. A C K A C K A C K N O A C K DS20001178J-page 11 24AA00/24LC00/24C00 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC (3.90 mm) XXXXXXXT XXXXYYWW NNN Example: 24LC00 I/P e3 13F 0527 Example: 24LC00I SN e3 0527 13F 8-Lead TSSOP Example: XXXX 4L00 TYWW I527 NNN 13F 8-Lead 2x3 DFN XXX YWW NN 8-Lead 2x3 TDFN XXX YWW NN Example: 204 527 13 Example: A04 527 13 5-Lead SOT-23 Example: XXNN M03F DS20001178J-page 12  1996-2018 Microchip Technology Inc. 24AA00/24LC00/24C00 1st Line Marking Codes Part Number TSSOP SOT-23 DFN TDFN I Temp. E Temp. I Temp. E Temp. I Temp. E Temp. 4A00 B0NN — 201 — A01 — 24LC00 4L00 M0NN — 204 — A04 — 24C00 4C00 D0NN E0NN 207 — A07 A08 24AA00 Note: NN = Alphanumeric traceability code Legend: XX...X T Y YY WW NNN e3 Note: Note: Note: Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.  1996-2018 Microchip Technology Inc. DS20001178J-page 13 24AA00/24LC00/24C00 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2 DS20001178J-page 14  1996-2018 Microchip Technology Inc. 24AA00/24LC00/24C00 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e 2 e 2 e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness Upper Lead Width b1 b Lower Lead Width Overall Row Spacing eB § e MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2  1996-2018 Microchip Technology Inc. DS20001178J-page 15 24AA00/24LC00/24C00 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001178J-page 16  1996-2018 Microchip Technology Inc. 24AA00/24LC00/24C00      !"#$% &  ! "# $% &"'"" ($)  % *++&&&!  !+$  1996-2018 Microchip Technology Inc. DS20001178J-page 17 24AA00/24LC00/24C00   '( ( )  '** !"' % &  ! "# $% &"'"" ($)  % *++&&&!  !+$ D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 @" !" A!" E#!7  )(" AA8 8 E E EG H  (  G3 K  L J;>? L  %%($ $""   1 1; % )) 1 ; L 1; 1 G3 N% 8  %%($N% 81 ?   %%($A