24AA024/24LC024/24AA025/24LC025
2K I2C™ Serial EEPROM
Device Selection Table
Description
Part
Number
VCC
Range
Max.
Clock
24AA024
1.7V-5.5V
400 kHz(1)
24AA025
1.7V-5.5V
(1)
I
No
24LC024
2.5V-5.5V
400 kHz
I, E
Yes
2.5V-5.5V
400 kHz
I, E
No
24LC025
Note 1:
400 kHz
Temp. Write
Range Protect
I
Yes
100 kHz for VCC < 2.5V
Features
• Single Supply with Operation from 1.7V to 5.5V for
24AA024/24AA025 Devices and 2.5V to 5.5V for
24LC024/24LC025 Devices
• Low-Power CMOS Technology:
- Read current: 1 mA, typical
- Standby current: 1 µA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time: 5 ms Maximum
• Self-timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect on 24XX024 Devices
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN and MSOP
• 6-Lead SOT-23 Package, 24XX025 only
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
The
Microchip
Technology
Inc.
24AA024/24LC024/24AA025/24LC025 is a 2 Kbit
Serial Electrically Erasable PROM with a voltage range
of 1.7V to 5.5V. The device is organized as a single
block of 256 x 8-bit memory with a 2-wire serial
interface. Low current design permits operation with
typical standby and active currents of only 1 µA and
1 mA, respectively. The device has a page write
capability for up to 16 bytes of data. Functional address
lines allow the connection of up to eight
24AA024/24LC024/24AA025/24LC025 devices on the
same bus for up to 16K bits of contiguous EEPROM
memory. The device is available in the standard 8-pin
PDIP, 8-pin SOIC (3.90 mm), TSSOP, 2x3 DFN and
TDFN and MSOP packages. The 24AA025/24LC025 is
also available in the 6-lead SOT-23 package.
Package Types
PDIP/SOIC/TSSOP/MSOP
A0
1
8
DFN/TDFN
A0 1
VCC
A1
2
7
WP(1)
A2
3
6
SCL
VSS
4
5
SDA
8 VCC
7 WP(1)
A1 2
6 SCL
A2 3
VSS 4
5 SDA
SOT-23
Note 1:
SCL
1
6
VCC
VSS
2
5
A0
SDA
3
4
A1
WP pin is not internally connected on the
24XX025.
Block Diagram
A0 A1 A2
WP(1)
I/O
Control
Logic
Memory
Control
Logic
HV Generator
XDEC
EEPROM
Array
SDA SCL
VCC
VSS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
2007-2015 Microchip Technology Inc.
DS20001210P-page 1
24AA024/24LC024/24AA025/24LC025
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
Symbol
No.
D1
Industrial (I):
TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Characteristic
Min.
Typ.
Max.
Units
VIH
High-level Input Voltage
0.7VCC
—
—
V
Low-level Input Voltage
Conditions
—
—
0.3VCC
V
0.2VCC for VCC < 2.5V
0.05VCC
—
—
V
(Note)
Low-level Output Voltage
—
—
0.40
V
IOL = 3.0 mA, VCC = 2.5V
ILI
Input Leakage Current
—
—
±1
µA
VIN = VSS or VCC
D6
ILO
Output Leakage Current
—
—
±1
µA
VOUT = VSS or VCC
D7
CIN,
COUT
Pin Capacitance
(all inputs/outputs)
—
—
10
pF
VCC = 5.5V (Note)
TA = 25°C, FCLK = 1 MHz
D8
ICCWRITE Operating Current
—
0.1
3
mA
VCC = 5.5V, SCL = 400 kHz
D9
ICCREAD
D10
ICCS
D2
VIL
D3
VHYS
D4
VOL
D5
Note:
Hysteresis of Schmitt
Trigger Inputs
Standby Current
—
0.05
1
mA
—
0.01
1
µA
SDA = SCL = VCC
A0, A1, A2, WP = VSS, I-Temp
—
—
5
µA
SDA = SCL = VCC
A0, A1, A2, WP = VSS,
E-Temp
This parameter is periodically sampled and not 100% tested.
DS20001210P-page 2
2007-2015 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
Conditions
1
FCLK
Clock Frequency
—
100
kHz
1.7V ≤ VCC < 1.8V
—
400
kHz
1.8V ≤ VCC ≤ 5.5V
2
THIGH
Clock High Time
4000
—
ns
1.7V ≤ VCC < 1.8V
600
—
ns
1.8V ≤ VCC ≤ 5.5V
3
TLOW
Clock Low Time
4700
—
ns
1.7V ≤ VCC < 1.8V
1300
—
ns
1.8V ≤ VCC ≤ 5.5V
4
TR
SDA and SCL Rise Time
(Note 1)
—
1000
ns
1.7V ≤ VCC < 1.8V
—
300
ns
1.8V ≤ VCC ≤ 5.5V
5
TF
SDA and SCL Fall Time
(Note 1)
—
1000
ns
1.7V ≤ VCC < 1.8V
—
300
ns
1.8V ≤ VCC ≤ 5.5V
6
THD:STA Start Condition Hold Time
4000
—
ns
1.7V ≤ VCC < 1.8V
600
—
ns
1.8V ≤ VCC ≤ 5.5V
7
TSU:STA
4700
—
ns
1.7V ≤ VCC < 1.8V
600
—
ns
1.8V ≤ VCC ≤ 5.5V
8
THD:DAT Data Input Hold Time
0
—
ns
(Note 2)
9
TSU:DAT Data Input Setup Time
250
—
ns
1.7V ≤ VCC < 1.8V
100
—
ns
1.8V ≤ VCC ≤ 5.5V
10
11
12
13
14
Start Condition Setup Time
TSU:STO Stop Condition Setup Time
TSU:WP
THD:WP
TAA
TBUF
WP Setup Time
WP Hold Time
Output Valid from Clock
(Note 2)
Bus Free Time: Bus time must
be free before a new
transmission can start
4000
—
ns
1.7V ≤ VCC < 1.8V
600
—
ns
1.8V ≤ VCC ≤ 5.5V
4000
—
ns
1.7V ≤ VCC < 1.8V
600
—
ns
1.8V ≤ VCC ≤ 5.5V
4700
—
ns
1.7V ≤ VCC < 1.8V
600
—
ns
1.8V ≤ VCC ≤ 5.5V
—
3500
ns
1.7V ≤ VCC < 1.8V
—
900
ns
1.8V ≤ VCC ≤ 5.5V
4700
—
ns
1.7V ≤ VCC < 1.8V
1300
—
ns
1.8V ≤ VCC ≤ 5.5V
(Note 1 and Note 3)
15
TSP
Input Filter Spike Suppression
(SDA and SCL pins)
—
50
ns
16
TWC
Write Cycle Time (byte or
page)
—
5
ms
17
—
Endurance
1M
—
cycles 25°C, VCC = 5.5V (Note 4)
Note 1: Not 100% tested.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
2007-2015 Microchip Technology Inc.
DS20001210P-page 3
24AA024/24LC024/24AA025/24LC025
FIGURE 1-1:
BUS TIMING DATA
5
SCL
7
SDA
In
3
4
D3
2
8
10
9
6
15
14
13
SDA
Out
WP
DS20001210P-page 4
(protected)
(unprotected)
11
12
2007-2015 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name
PDIP
SOIC
TSSOP
DFN/TDFN
MSOP
SOT-23
Description
A0
1
1
1
1
1
5
Address Pin AO
A1
2
2
2
2
2
4
Address Pin A1
A2
3
3
3
3
3
—
Address Pin A2
VSS
4
4
4
4
4
2
Ground
SDA
5
5
5
5
5
3
Serial Address/Data I/O
SCL
6
6
6
6
6
1
Serial Clock
WP
7
7
7
7
7
—
Write-Protect Input
VCC
8
8
8
8
8
6
+1.7 to 5.5V Power Supply
2.1
A0, A1, A2
2.5
Noise Protection
The levels on the A0, A1 and A2 inputs are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true. For the SOT-23
package only, pin A2 is not connected.
The 24AA024/24LC024/24AA025/24LC025 employs a
VCC threshold detector circuit which disables the
internal erase/write logic if the VCC is below 1.5V at
nominal conditions.
Up to eight 24AA024/24LC024/24AA025/24LC025
devices (four for the SOT-23 package) may be
connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either VCC or VSS.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
2.2
The 24AA024/24LC024/24AA025/24LC025 supports
a bidirectional, 2-wire bus and data transmission
protocol. A device that sends data onto the bus is
defined as transmitter, while a device receiving data
is defined as receiver. The bus has to be controlled
by a master device that generates the Serial Clock
(SCL), controls the bus access and generates the
Start
and
Stop
conditions,
while
the
24AA024/24LC024/24AA025/24LC025 works as
slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
SDA Serial Data
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal; therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz and 2 k for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3
SCL Serial Clock
3.0
FUNCTIONAL DESCRIPTION
The SCL input is used to synchronize the data transfer
from and to the device.
2.4
WP (24XX024 Only)
WP is the hardware write-protect pin. It must be tied to
VCC or VSS. If tied to Vcc, hardware write protection is
enabled. If WP is tied to Vss, the hardware write
protection is disabled. Note that the WP pin is available
only on the 24XX024. This pin is not internally
connected on the 24LC025.
2007-2015 Microchip Technology Inc.
DS20001210P-page 5
24AA024/24LC024/24AA025/24LC025
4.0
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (though only the last sixteen will
be stored when performing a write operation). When an
overwrite does occur, it will replace data in a first-in
first-out fashion.
4.1
4.5
Bus Not Busy (A)
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. A master
must signal an end of data to the slave by not generating
an Acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must
leave the data line high to enable the master to generate
the Stop condition (Figure 4-2).
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
FIGURE 4-1:
SCL
(A)
The 24AA024/24LC024/24AA025/24LC025
does not generate any Acknowledge bits if
an internal programming cycle is in
progress.
Note:
Stop Data Transfer (C)
4.4
Acknowledge
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(B)
(C)
(D)
(C)
(A)
SDA
Start
Condition
FIGURE 4-2:
Address or
Acknowledge
Valid
Stop
Condition
Data
Allowed
to Change
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
SDA
2
3
4
5
6
7
Data from transmitter
Transmitter must release the SDA line at this point allowing
the Receiver to pull the SDA line low to acknowledge the
previous eight bits of data.
DS20001210P-page 6
8
9
1
2
3
Data from transmitter
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
2007-2015 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code. For the
24AA024/24LC024/24AA025/24LC025, this is set as
‘1010’ binary for read and write operations. The next
three bits of the control byte are the Chip Select bits
(A2, A1, A0). The Chip Select bits allow the use of up
to
eight
24AA024/24LC024/24AA025/24LC025
devices on the same bus and are used to select which
device is accessed. The Chip Select bits in the control
byte must correspond to the logic levels on the
corresponding A2, A1 and A0 pins for the device to
respond. These bits are, in effect, the three Most
Significant bits of the word address.
For the SOT-23 package, the A2 address pin is not
available. During device addressing, the A2 Chip
Select bit should be set to ‘0’.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. Following the Start condition, the
24AA024/24LC024/24AA025/24LC025 monitors the
SDA bus checking the control byte being transmitted.
Upon receiving a ‘1010’ code and appropriate Chip
Select bits, the slave device outputs an Acknowledge
signal on the SDA line. Depending on the state of the
R/W bit, the 24AA024/24LC024/24AA025/24LC025
will select a read or write operation.
2007-2015 Microchip Technology Inc.
FIGURE 5-1:
CONTROL BYTE FORMAT
Read/Write Bit
Chip Select
Bits
Control Code
S
1
0
1
0
A2
A1
A0 R/W ACK
Slave Address
Start Bit
5.1
Acknowledge Bit
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 16K bits
by
adding
up
to
eight
24AA024/24LC024/24AA025/24LC025 devices on the
same bus. In this case, software can use A0 of the
control byte as address bit A8; A1 as address bit A9;
and A2 as address bit A10. It is not possible to
sequentially read across device boundaries.
For the SOT-23 package, up to four 24AA025/24LC025
devices can be added for up to 8K bits of address
space. In this case, software can use A0 of the control
byte as address bit A8, and A1 as address bit A9. It is
not possible to sequentially read across device
boundaries.
DS20001210P-page 7
24AA024/24LC024/24AA025/24LC025
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the Start signal from the master, the device
code(four bits), the Chip Select bits (three bits) and
the R/W bit (which is a logic low) are placed onto the
bus by the master transmitter. The device will
acknowledge this control byte during the ninth clock
pulse. The next byte transmitted by the master is the
word address and will be written into the Address
Pointer of the 24AA024/24LC024/24AA025/24LC025.
After receiving another Acknowledge signal from the
24AA024/24LC024/24AA025/24LC025, the master
device will transmit the data word to be written into the
addressed
memory
location.
The
24AA024/24LC024/24AA025/24LC025 acknowledges
again and the master generates a Stop condition. This
initiates the internal write cycle and, during this time,
the 24AA024/24LC024/24AA025/24LC025 will not
generate Acknowledge signals (Figure 6-1). If an
attempt is made to write to the protected portion of the
array when the hardware write protection (24XX024
only) has been enabled, the device will acknowledge
the command, but no data will be written. The write
cycle time must be observed even if write protection is
enabled.
6.2
The higher-order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte-write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the protected portion of the array
when the hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written. The write cycle time must be observed
even if write protection is enabled.
Note:
Page Write
The write control byte, word address and the first data
byte
are
transmitted
to
the
24AA024/24LC024/24AA025/24LC025 in the same
way as in a byte write. However, instead of generating
a Stop condition, the master transmits up to 15
additional
data
bytes
to
the
24AA024/24LC024/24AA025/24LC025, which are
temporarily stored in the on-chip page buffer and will be
written into the memory once the master has
transmitted a Stop condition. Upon receipt of each
word, the four lower-order Address Pointer bits are
internally incremented by one.
FIGURE 6-1:
6.3
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Write Protection
The WP pin (available on 24XX024 only) must be tied
to VCC or VSS. If tied to VCC, the entire array will be
write-protected. If the WP pin is tied to VSS, write
operations to all address locations are allowed.
The WP pin is not available on the SOT-23 package.
BYTE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Bus Activity
DS20001210P-page 8
Control
Byte
Word
Address
S
T
O
P
Data
P
A
C
K
A
C
K
A
C
K
2007-2015 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
FIGURE 6-2:
PAGE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
Bus Activity
2007-2015 Microchip Technology Inc.
Word
Address (n)
Data (n)
Data (n + 15)
Data (n +1)
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DS20001210P-page 9
24AA024/24LC024/24AA025/24LC025
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle, with ACK
polling being initiated immediately. This involves the
master sending a Start condition, followed by the
control byte for a Write command (R/W = 0). If the
device is still busy with the write cycle, no ACK will be
returned. If no ACK is returned, the Start bit and control
byte must be resent. If the cycle is complete, the device
will return the ACK and the master can then proceed
with the next Read or Write command. See Figure 7-1
for a flow diagram of this operation.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
DS20001210P-page 10
2007-2015 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
8.0
READ OPERATIONS
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24AA024/24LC024/24AA025/24LC025 contains
an address counter that maintains the address of the
last word accessed, internally incremented by one.
Therefore, if the previous read access was to address
‘n’, the next current address read operation would
access data from address n + 1. Upon receipt of the
slave address with the R/W bit set to ‘1’, the
24AA024/24LC024/24AA025/24LC025 issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but generate
a
Stop
condition,
which
causes
the
24AA024/24LC024/24AA025/24LC025 to discontinue
transmission (Figure 8-1).
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24AA024/24LC024/24AA025/24LC025
as part of a write operation. Once the word address is
sent, the master generates a Start condition following
the acknowledge. This terminates the write operation,
but not before the internal Address Pointer is set. The
master then issues the control byte again, but with the
R/W bit set to a ‘1’.
The 24AA024/24LC024/24AA025/24LC025 will then
issue an acknowledge and transmit the 8-bit data word.
The master will not acknowledge the transfer, though it
does generate a Stop condition, which causes the
24AA024/24LC024/24AA025/24LC025 to discontinue
transmission (Figure 8-2). After this command, the
internal address counter will point to the address
location following the one that was just read.
2007-2015 Microchip Technology Inc.
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random
read
except
that
after
the
24AA024/24LC024/24AA025/24LC025 transmits the
first data byte, the master issues an acknowledge (as
opposed to a Stop condition in a random read). This
directs the 24AA024/24LC024/24AA025/24LC025 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3).
To
provide
sequential
reads,
the
24AA024/24LC024/24AA025/24LC025 contains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation. The internal Address
Pointer will automatically roll over from address 0FFh
to address 000h.
FIGURE 8-1:
Bus Activity
Master
SDA Line
Bus Activity
CURRENT ADDRESS
READ
S
T
A
R
T
Control
Byte
S
T
O
P
Data
P
S
A
C
K
N
O
A
C
K
DS20001210P-page 11
24AA024/24LC024/24AA025/24LC025
FIGURE 8-2:
RANDOM READ
Bus Activity
Master
S
T
A
R
T
Control
Byte
S
SDA Line
Bus Activity
Master
Control
Byte
S
T
O
P
Data (n)
P
S
A
C
K
A
C
K
Bus Activity
FIGURE 8-3:
S
T
A
R
T
Word
Address (n)
N
O
A
C
K
A
C
K
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + x)
P
SDA Line
Bus Activity
DS20001210P-page 12
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
2007-2015 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
9.0
PACKAGING INFORMATION
9.1
Package Marking Information*
8-Lead PDIP (300 mil)
XXXXXXXX
T/XXXNNN
YYWW
8-Lead SOIC (3.90 mm)
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP
Example:
24LC024
I/P e3 13F
1512
Example:
24LC024I
SN e3 1512
13F
Example:
XXXX
4L24
TYWW
I512
NNN
13F
8-Lead MSOP
XXXXT
YWWNNN
8-Lead 2x3 DFN
XXX
YWW
NN
8-Lead 2x3 TDFN
XXX
YWW
NN
2007-2015 Microchip Technology Inc.
Example:
4L24I
51213F
Example:
2P4
512
13
Example:
AP4
512
13
DS20001210P-page 13
24AA024/24LC024/24AA025/24LC025
6-Lead SOT-23
Example:
XXNN
HQEC
1st Line Marking Codes
Part Number
DFN
TSSOP
24AA024
4A24
TDFN
SOT-23
MSOP
4A24T
I-TEMP
E-TEMP
I-TEMP
E-TEMP
I-TEMP
E-TEMP
2P1
—
AP1
—
—
—
24LC024
4L24
4L24T
2P4
AP5
AP4
2P5
—
—
24AA025
4A25
4A25T
2R1
—
AR1
—
HQNN
HRNN
4L25
4L25T
2R4
AR5
AR4
2R5
HMNN
HPNN
24LC025
Note:
T = Temperature grade (I, E)
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
* Standard OTP marking consists of Microchip part number, year code, week code,
and traceability code.
Note:
Note:
DS20001210P-page 14
For very small packages with no room for the JEDEC® designator
e3 , the marking will only appear on the outer carton or reel label.
In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2007-2015 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
C
A2
A
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
2007-2015 Microchip Technology Inc.
DS20001210P-page 15
24AA024/24LC024/24AA025/24LC025
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
DATUM A
DATUM A
b
b
e
2
e
2
e
Units
Dimension Limits
Number of Pins
N
e
Pitch
Top to Seating Plane
A
Molded Package Thickness
A2
Base to Seating Plane
A1
Shoulder to Shoulder Width
E
Molded Package Width
E1
Overall Length
D
Tip to Seating Plane
L
c
Lead Thickness
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing
eB
§
e
MIN
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
INCHES
NOM
8
.100 BSC
.130
.310
.250
.365
.130
.010
.060
.018
-
MAX
.210
.195
.325
.280
.400
.150
.015
.070
.022
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
DS20001210P-page 16
2007-2015 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2007-2015 Microchip Technology Inc.
DS20001210P-page 17
24AA024/24LC024/24AA025/24LC025
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001210P-page 18
2007-2015 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
!"#$%
&
!
"# $% &"'""
($)
%
*++&&&!
!+$
2007-2015 Microchip Technology Inc.
DS20001210P-page 19
24AA024/24LC024/24AA025/24LC025
'(
(
)
'** !"' %
&
!
"# $% &"'""
($)
%
*++&&&!
!+$
D
N
E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
@"
!"
A!"
E#!7
)("
AA8
8
E
E
EG
H
(
G3 K
L
J;>?
L
%%($
$""
1
1;
%
))
1
;
L
1;
1
G3 N%
8
%%($N%
81
?
%%($A