24LC1025T-I/SM

24AA1025/24LC1025/24FC1025 1024K I2C™ Serial EEPROM Device Selection Table: Part Number VCC Range Max. Clock Frequency 24AA1025 1.7-5.5V 400 kHz† I 24LC1025 2.5-5.5V 400 kHz* I, E 24FC1025 1.8-5.5V 1 MHz‡ I Temp. Ranges † 100 kHz for VCC < 2.5V *100 kHz for VCC < 4.5V, E-temp ‡400 kHz for VCC < 2.5V This device is capable of both random and sequential reads. Reads may be sequential within address boundaries 0000h to FFFFh and 10000h to 1FFFFh. Functional address lines allow up to four devices on the same data bus. This allows for up to 4 Mbits total system EEPROM memory. This device is available in the standard 8-pin PDIP, SOIC and SOIJ packages. Package Type PDIP A0 1 8 VCC A1 2 7 WP A2* 3 6 SCL VSS 4 5 SDA Features: • Low-Power CMOS Technology: - Read current 450 A, maximum - Standby current 5 A, maximum • 2-Wire Serial Interface, I2C™ Compatible • Cascadable up to Four Devices • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kHz and 400 kHz Clock Compatibility • 1 MHz Clock for FC Versions • Page Write Time 3 ms, typical • Self-Timed Erase/Write Cycle • 128-Byte Page Write Buffer • Hardware Write-Protect • ESD Protection >4000V • More than 1 Million Erase/Write Cycles • Data Retention >200 Years • Factory Programming Available • Packages include 8-lead PDIP, SOIJ and SOIC • Pb-Free and RoHS Compliant • Temperature Ranges: - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C Description: The Microchip Technology Inc. 24AA1025/24LC1025/ 24FC1025 (24XX1025*) is a 128K x 8 (1024K bit) Serial Electrically Erasable PROM, capable of operation across a broad voltage range (1.7V to 5.5V). It has been developed for advanced, low-power applications such as personal communications or data acquisition. This device has both byte write and page write capability of up to 128 bytes of data.  2005-2013 Microchip Technology Inc. SOIJ/SOIC A0 1 8 VCC A1 2 7 WP A2* 3 6 SCL VSS 4 5 SDA *A2 must be tied to VCC. Block Diagram A0 A1 I/O Control Logic WP Memory Control Logic HV Generator XDEC EEPROM Array Page Latches I/O SCL YDEC SDA VCC VSS Sense AMP R/W Control *24XX1025 is used in this document as a generic part number for the 24AA1025/24LC1025/24FC1025 devices. DS20001941L-page 1 24AA1025/24LC1025/24FC1025 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS .......................................................................................................... -0.6V to VCC+1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins  4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. Sym. Characteristic Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C Min. Max. Units Conditions — A1, A2, SCL, SDA and WP pins: — — — D1 VIH High-level input voltage 0.7 VCC — V D2 VIL Low-level input voltage — 0.3 VCC 0.2 VCC V V VCC 2.5V VCC < 2.5V D3 VHYS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) 0.05 VCC — V VCC  2.5V (Note) D4 VOL Low-level output voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V IOL = 2.1 mA @ VCC = 2.5V D5 ILI Input leakage current — ±1 A VIN = VSS or VCC VIN = VSS or VCC D6 ILO Output leakage current — ±1 A VOUT = VSS or VCC D7 CIN, COUT Pin capacitance (all inputs/outputs) — 10 pF VCC = 5.0V (Note) TA = 25°C, FCLK = 1 MHz D8 ICC Read Operating current — 450 A VCC = 5.5V, SCL = 400 kHz — 5 mA VCC = 5.5V D9 ICCS — 5 A SCL, SDA, VCC = 5.5V A1, A2, WP = VSS ICC Write Note: Standby current This parameter is periodically sampled and not 100% tested. DS20001941L-page 2  2005-2013 Microchip Technology Inc. 24AA1025/24LC1025/24FC1025 TABLE 1-2: AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): Vcc = +2.5V to 5.5V TA = -40°C to +125°C AC CHARACTERISTICS Param. No. Sym. Characteristic Min. Max. Units Conditions 1 FCLK Clock frequency — — — — — 100 100 400 400 1000 kHz 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 2 THIGH Clock high time 4000 4000 600 600 500 — — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 3 TLOW Clock low time 4700 4700 1300 1300 500 — — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 4 TR SDA and SCL rise time (Note 1) — — — — — 1000 1000 300 300 300 ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 5 TF SDA and SCL fall time (Note 1) — — 300 100 ns All except 24FC1025 1.8V  VCC  5.5V (24FC1025 only) 6 THD:STA Start condition hold time 4000 4000 600 600 250 — — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 7 TSU:STA 4700 4700 600 600 250 — — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 8 THD:DAT Data input hold time 0 — ns (Note 2) 9 TSU:DAT 250 250 100 100 100 — — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 10 TSU:STO Stop condition setup time 4000 4000 600 600 250 — — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) Note 1: Start condition setup time Data input setup time Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.  2005-2013 Microchip Technology Inc. DS20001941L-page 3 24AA1025/24LC1025/24FC1025 AC CHARACTERISTICS (Continued) Param. No. Sym. Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): Vcc = +2.5V to 5.5V TA = -40°C to +125°C Characteristic Min. Max. Units Conditions 11 TSU:WP WP setup time 4000 4000 600 600 600 — — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 12 THD:WP WP hold time 4700 4700 1300 1300 1300 — — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 13 TAA Output valid from clock (Note 2) — — — — — 3500 3500 900 900 400 ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 4700 4700 1300 1300 500 — — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  4.5V, E-temp 2.5V  VCC  5.5V 1.8V  VCC  2.5V (24FC1025 only) 2.5V  VCC  5.5V (24FC1025 only) 15 TSP Input filter spike suppression (SDA and SCL pins) — 50 ns All except 24FC1025 (Note 1 and Note 3) 16 TWC ms — 17 Write cycle time (byte or page) Endurance Note 1: — 5 1,000,000 — cycles Page mode, 25°C, VCC = 5.5V (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA IN 3 4 D3 2 8 10 9 6 15 14 13 SDA OUT WP DS20001941L-page 4 (protected) (unprotected) 11 12  2005-2013 Microchip Technology Inc. 24AA1025/24LC1025/24FC1025 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: 2.1 PIN FUNCTION TABLE Name PDIP SOIJ SOIC Function A0 1 1 1 User Configurable Chip Select A1 2 2 2 User Configurable Chip Select A2 3 3 3 Non-Configurable Chip Select. This pin must be hard-wired to logical 1 state (VCC). Operation will be undefined with this pin left floating or held to logical 0 (VSS). VSS 4 4 4 Ground SDA 5 5 5 Serial Data SCL 6 6 6 Serial Clock WP 7 7 7 Write-Protect Input VCC 8 8 8 +1.7 to 5.5V (24AA1025) +2.5 to 5.5V (24LC1025) +1.8 to 5.5V (24FC1025) A0, A1 Chip Address Inputs The A0 and A1 inputs are used by the 24XX1025 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the comparison is true. Up to four devices may be connected to the same bus by using different Chip Select bit combinations. In most applications, the chip address inputs A0 and A1 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. 2.2 A2 Chip Address Input The A2 input is non-configurable Chip Select. This pin must be tied to VCC in order for this device to operate. If left floating or tied to VSS, device operation will be undefined.  2005-2013 Microchip Technology Inc. 2.3 Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an opendrain terminal, therefore, the SDA bus requires a pullup resistor to VCC (typical 10 k for 100 kHz, 2 kfor 400 kHz and 1 MHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 2.4 Serial Clock (SCL) This input is used to synchronize the data transfer from and to the device. 2.5 Write-Protect (WP) This pin must be connected to either VSS or VCC. If tied to VSS, write operations are enabled. If tied to VCC, write operations are inhibited, but read operations are not affected. DS20001941L-page 5 24AA1025/24LC1025/24FC1025 3.0 FUNCTIONAL DESCRIPTION The 24XX1025 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the Start and Stop conditions while the 24XX1025 works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. DS20001941L-page 6  2005-2013 Microchip Technology Inc. 24AA1025/24LC1025/24FC1025 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device. 4.5 Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Bus Not Busy (A) Both data and clock lines remain high. Note: 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 A device that acknowledges must pull-down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX1025) will leave the data line high to enable the master to generate the Stop condition. Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition. 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. FIGURE 4-1: (A) The 24XX1025 does not generate any Acknowledge bits if an internal programming cycle is in progress, however, the control byte that is being polled must match the control byte used to initiate the write cycle. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) (D) Start Condition Address or Acknowledge Valid (C) (A) SCL SDA FIGURE 4-2: Data Allowed To Change Stop Condition ACKNOWLEDGE TIMING Acknowledge Bit SCL SDA 1 2 3 4 5 6 7 Data from transmitter The transmitter must release the SDA line at this point allowing the receiver to pull the SDA line low to acknowledge the previous eight bits of data.  2005-2013 Microchip Technology Inc. 8 9 1 2 3 Data from transmitter The receiver must release the SDA line at this point so the transmitter can continue sending data. DS20001941L-page 7 24AA1025/24LC1025/24FC1025 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code; for the 24XX1025, this is set as ‘1010’ binary for read and write operations. The next bit of the control byte is the block select bit (B0). This bit acts as the A16 address bit for accessing the entire array. The next two bits of the control byte are the Chip Select bits (A1, A0). The Chip Select bits allow the use of up to four 24XX1025 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A1 and A0 pins for the device to respond. These bits are in effect the two Most Significant bits (MSb) of the word address. The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is selected, and when set to a zero, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). The upper address bits are transferred first, followed by the Least Significant bits (LSb). Following the Start condition, the 24XX1025 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a ‘1010’ code and appropriate device select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX1025 will select a read or write operation. This device has an internal addressing boundary limitation that is divided into two segments of 512K bits. Block select bit ‘B0’ to control access to each segment. FIGURE 5-2: 0 1 Control Code Read/Write Bit Block Select Bits Control Code S 1 0 1 0 B0 Chip Select Bits A1 A0 R/W ACK Slave Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The Chip Select bits A1 and A0 can be used to expand the contiguous address space for up to 4 Mbit by adding up to four 24XX1025’s on the same bus. In this case, software can use A0 of the control byte as address bit A17 and A1 as address bit A18. It is not possible to sequentially read across device boundaries. Each device has internal addressing boundary limitations. This divides each part into two segments of 512K bits. The block select bit ‘B0’ controls access to each “half”. Sequential read operations are limited to 512K blocks. To read through four devices on the same bus, eight random Read commands must be given. ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte 1 CONTROL BYTE FORMAT B 0 0 A 1 Address High Byte A 0 R/W Block Chip Select Select Bits Bit DS20001941L-page 8 A A A A A A 15 14 13 12 11 10 Address Low Byte A 9 A 8 A 7 • • • • • • A 0 X = “don’t care” bit  2005-2013 Microchip Technology Inc. 24AA1025/24LC1025/24FC1025 6.0 WRITE OPERATIONS 6.1 Byte Write Following the Start condition from the master, the control code (four bits), the block select (one bit), the Chip Select (two bits), and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the Address Pointer of the 24XX1025. The next byte is the Least Significant Address Byte. After receiving another Acknowledge signal from the 24XX1025, the master device will transmit the data word to be written into the addressed memory location. The 24XX1025 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and during this time, the 24XX1025 will not generate Acknowledge signals as long as the control byte being polled matches the control byte that was used to initiate the write (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. After a byte Write command, the internal address counter will point to the address location following the one that was just written. Note: When doing a write of less than 128 bytes the data in the rest of the page is refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page.  2005-2013 Microchip Technology Inc. 6.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24XX1025 in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 127 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a Stop condition. After receipt of each word, the seven lower Address Pointer bits are internally incremented by one. If the master should transmit more than 128 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. 6.3 Write Protection The WP pin allows the user to write-protect the entire array (00000-1FFFF) when the pin is tied to VCC. If tied to VSS the write protection is disabled. The WP pin is sampled at the Stop bit for every Write command (Figure 1-1). Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. DS20001941L-page 9 24AA1025/24LC1025/24FC1025 FIGURE 6-1: BYTE WRITE S T A R T BUS ACTIVITY MASTER Control Byte Address High Byte Address Low Byte S T O P Data AA S1 01 0B 010 0 SDA LINE X = “don’t care” bit A C K A C K A C K A C K BUS ACTIVITY FIGURE 6-2: P PAGE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE BAA S101 00100 BUS ACTIVITY X = “don’t care” bit DS20001941L-page 10 Control Byte Address High Byte Address Low Byte Data Byte 0 S T O P Data Byte 127 P A C K A C K A C K A C K A C K  2005-2013 Microchip Technology Inc. 24AA1025/24LC1025/24FC1025 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete. (This feature can be used to maximize bus throughput.) Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for flow diagram. Note: Care must be taken when polling the 24XX1025. The control byte that was used to initiate the write needs to match the control byte used for polling. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation  2005-2013 Microchip Technology Inc. DS20001941L-page 11 24AA1025/24LC1025/24FC1025 8.0 READ OPERATION 8.2 Read operations are initiated in the same way as write operations with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX1025 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to one, the 24XX1025 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24XX1025 discontinues transmission (Figure 8-1). FIGURE 8-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S 1 0 1 0 B AA 1 0 1 0 BUS ACTIVITY DS20001941L-page 12 Control Byte S T O P Data Byte P A C K N O A C K Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24XX1025 as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then, the master issues the control byte again, but with the R/W bit set to a one. The 24XX1025 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition which causes the 24XX1025 to discontinue transmission (Figure 8-2). After a random Read command, the internal address counter will point to the address location following the one that was just read. 8.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24XX1025 transmits the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random read. This acknowledge directs the 24XX1025 to transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge, but will generate a Stop condition. To provide sequential reads, the 24XX1025 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows half the memory contents to be serially read during one operation. Sequential read address boundaries are 00000h to 0FFFFh and 10000h to 1FFFFh. The internal Address Pointer will automatically roll over from address 0FFFFh to address 00000h if the master acknowledges the byte received from the array address, 0FFFFh. The internal address counter will automatically roll over from address 1FFFFh to address 10000h if the master acknowledges the byte received from the array address, 1FFFFh.  2005-2013 Microchip Technology Inc. 24AA1025/24LC1025/24FC1025 FIGURE 8-2: BUS ACTIVITY MASTER SDA LINE RANDOM READ S T A R T Control Byte S 1 0 1 0 BUS ACTIVITY MASTER S T A R T Address Low Byte B A A 0 0 1 0 Control Byte S T O P Data Byte S 1 0 1 0 B A A1 0 1 0 A C K A C K BUS ACTIVITY FIGURE 8-3: Address High Byte A C K P N O A C K A C K SEQUENTIAL READ Control Byte Data n Data n + 1 S T O P Data n + X Data n + 2 P SDA LINE BUS ACTIVITY A C K  2005-2013 Microchip Technology Inc. A C K A C K A C K N O A C K DS20001941L-page 13 24AA1025/24LC1025/24FC1025 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX TXXXXNNN YYWW 24LC1025 I/P e3 13F 0928 8-Lead SOIC (3.90 mm) 8-Lead SOIJ (5.28 mm) Legend: XX...X T Y YY WW NNN e3 Note: Note: * Example: 24L1025I SN e3 0928 13F XXXXXXXT XXXXYYWW NNN XXXXXXXX TXXXXXXX YYWWNNN Example: Example: 24LC1025 I/SM e3 0928 13F Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS20001941L-page 14  2005-2013 Microchip Technology Inc. 24AA1025/24LC1025/24FC1025           3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6&! '! 9'&! 7"')  %! 7,8. 7 7 7: ; < &  & &  = =   ##4 4!!   -  1!& &   = =  "# &  "# >#& .  - -  ##4>#& .   #& 9 * 9#>#& :   *+ 1, -    !"#$%&" '  ()"&'"!&) &#*&&&#   +%&, & !& - '! !#.#  &"#' #%!  & "! ! #%!  & "! !! &$#/ !#  '! #&   .0 1,21!'!   &$& "! **& "&&  !       * ,