24LC128-I/MS

24AA128/24LC128/24FC128 128K I2C™ CMOS Serial EEPROM Device Selection Table Part Number VCC Range Max. Clock Frequency Temp. Ranges 24AA128 1.7-5.5V 400 kHz(1) I 24LC128 2.5-5.5V 400 kHz I, E 24FC128 1.7-5.5V 1 MHz(2) I Note 1: 2: • Temperature Ranges: - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C Description: The Microchip Technology Inc. 24AA128/24LC128/ 24FC128 (24XX128*) is a 16K x 8 (128 Kbit) Serial Electrically Erasable PROM (EEPROM), capable of operation across a broad voltage range (1.7V to 5.5V). It has been developed for advanced, low-power applications such as personal communications or data acquisition. This device also has a page write capability of up to 64 bytes of data. This device is capable of both random and sequential reads up to the 128K boundary. Functional address lines allow up to eight devices on the same bus, for up to 1 Mbit address space. This device is available in the standard 8-pin plastic DIP, SOIC (3.90 mm and 5.28 mm), TSSOP, MSOP, DFN, TDFN and Chip Scale packages. 100 kHz for VCC < 2.5V. 400 kHz for VCC < 2.5V. Features: • Single Supply with Operation down to 1.7V for 24AA128/24FC128 devices, 2.5V for 24LC128 Devices • Low-Power CMOS Technology: - Write current 3 mA, typical - Standby current 100 nA, typical • 2-Wire Serial Interface, I2C™ Compatible • Cascadable up to Eight Devices • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kHz and 400 kHz Clock Compatibility • 1 MHz Clock for FC Versions • Page Write Time 5 ms, typical • Self-Timed Erase/Write Cycle • 64-Byte Page Write Buffer • Hardware Write-Protect • ESD Protection >4000V • More than 1 Million Erase/Write Cycles • Data Retention > 200 years • Factory Programming Available • Packages include 8-lead PDIP, SOIC, TSSOP, DFN, TDFN, MSOP, and Chip Scale Packages • Pb-Free and RoHS Compliant Block Diagram A0 A1 A2 WP Memory Control Logic I/O Control Logic HV Generator EEPROM Array XDEC Page Latches I/O SCL YDEC SDA VCC Sense Amp. R/W Control VSS *24XX128 is used in this document as a generic part number for the 24AA128/24LC128/24FC128 devices. Package Types A1 2 A2 3 VSS 4 8 VCC A0 1 7 WP A1 2 6 SCL A2 3 5 SDA VSS 4 CS (Chip Scale)2 DFN/TDFN 8 VCC A0 1 7 WP A1 2 6 SCL A2 3 5 SDA VSS 4 VCC A1 A0 8 VCC 24XX128 1 24XX128 A0 24XX128 TSSOP/MSOP1 PDIP/SOIC 7 WP 6 SCL 5 SDA 1 2 4 WP 6 3 5 7 A2 8 SDA SCL VSS (TOP DOWN VIEW, BALLS NOT VISIBLE) Note 1: Pins A0 and A1 are no-connects for the MSOP package only. 2: Available in I-temp, “AA” only.  2010 Microchip Technology Inc. DS21191S-page 1 24AA128/24LC128/24FC128 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins  4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C DC CHARACTERISTICS Param. No. Sym. Characteristic — A0, A1, A2, SCL, SDA and WP pins: Min. Max. Units Conditions — — — — D1 VIH High-level input voltage 0.7 VCC — V — D2 VIL Low-level input voltage — 0.3 VCC 0.2 VCC V V VCC 2.5V VCC < 2.5V D3 VHYS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) 0.05 VCC — V VCC  2.5V (Note 1) D4 VOL Low-level output voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V IOL = 2.1 mA @ VCC = 2.5V D5 ILI Input leakage current — ±1 A VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC D6 ILO Output leakage current — ±1 A VOUT = VSS or VCC D7 CIN, COUT Pin capacitance (all inputs/outputs) — 10 pF VCC = 5.0V (Note 1) TA = 25°C, FCLK = 1 MHz D8 ICC Read Operating current — 400 A VCC = 5.5V, SCL = 400 kHz — 3 mA VCC = 5.5V — 1 A TA = -40°C to +85°C SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS — 5 A TA = -40°C to 125°C SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS ICC D9 Write ICCS Standby current Note 1: This parameter is periodically sampled and not 100% tested. DS21191S-page 2  2010 Microchip Technology Inc. 24AA128/24LC128/24FC128 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C AC CHARACTERISTICS Param. No. Sym. Characteristic Min. Max. Units Conditions 1 FCLK Clock frequency — — — — 100 400 400 1000 kHz 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC128 2.5V  VCC  5.5V 24FC128 2 THIGH Clock high time 4000 600 600 500 — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC128 2.5V  VCC  5.5V 24FC128 3 TLOW Clock low time 4700 1300 1300 500 — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC128 2.5V  VCC  5.5V 24FC128 4 TR SDA and SCL rise time (Note 1) — — — 1000 300 300 ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  5.5V 24FC128 5 TF SDA and SCL fall time (Note 1) — — 300 100 ns All except, 24FC128 1.7V  VCC  5.5V 24FC128 6 THD:STA Start condition hold time 4000 600 600 250 — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC128 2.5V  VCC  5.5V 24FC128 7 TSU:STA 4700 600 600 250 — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC128 2.5V  VCC  5.5V 24FC128 8 THD:DAT Data input hold time 0 — ns (Note 2) 9 TSU:DAT Data input setup time 250 100 100 — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  5.5V 24FC128 10 TSU:STO Stop condition setup time 4000 600 600 250 — — — — ns 1.7 V  VCC  2.5V 2.5 V  VCC  5.5V 1.7V  VCC  2.5V 24FC128 2.5 V  VCC  5.5V 24FC128 11 TSU:WP WP setup time 4000 600 600 — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  5.5V 24FC128 12 THD:WP WP hold time 4700 1300 1300 — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  5.5V 24FC128 Start condition setup time Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com.  2010 Microchip Technology Inc. DS21191S-page 3 24AA128/24LC128/24FC128 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C AC CHARACTERISTICS Param. No. Sym. Characteristic Min. Max. Units Conditions — — — — 3500 900 900 400 ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC128 2.5V  VCC  5.5V 24FC128 4700 1300 1300 500 — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC128 2.5V  VCC  5.5V 24FC128 10 + 0.1CB 250 250 ns All except, 24FC128 (Note 1) 24FC128 (Note 1) 13 TAA Output valid from clock (Note 2) 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 15 TOF Output fall time from VIH minimum to VIL maximum CB  100 pF 16 TSP Input filter spike suppression (SDA and SCL pins) — 50 ns All except, 24FC128 (Notes 1 and 3) 17 TWC Write cycle time (byte or page) — 5 ms — 18 — Endurance 1,000,000 — cycles Page Mode, 25°C, 5.5V (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com. FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA IN 3 4 D3 2 8 10 9 6 16 14 13 SDA OUT WP DS21191S-page 4 (protected) (unprotected) 11 12  2010 Microchip Technology Inc. 24AA128/24LC128/24FC128 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Name A0 PIN FUNCTION TABLE PDIP SOIC TSSOP MSOP DFN(1) TDFN(1) CS Function 1 1 1 — 1 1 3 User Configurable Chip Select A1 2 2 2 — 2 2 2 User Configurable Chip Select (NC) — — — 1, 2 — — — Not Connected A2 3 3 3 3 3 3 5 User Configurable Chip Select VSS 4 4 4 4 4 4 8 Ground SDA 5 5 5 5 5 5 6 Serial Data SCL 6 6 6 6 6 6 7 Serial Clock WP 7 7 7 7 7 7 4 Write-Protect Input VCC 8 8 8 8 8 8 1 +1.7V to 5.5V (24AA128) +2.5V to 5.5V (24LC128) +1.7V to 5.5V (24FC128) Note 1: 2.1 The exposed pad on the DFN/TDFN package can be connected to VSS or left floating. A0, A1, A2 Chip Address Inputs 2.3 Serial Clock (SCL) The A0, A1 and A2 inputs are used by the 24XX128 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. This input is used to synchronize the data transfer to and from the device. For the MSOP package only, pins A0 and A1 are not connected. This pin must be connected to either VSS or VCC. If tied to VSS, write operations are enabled. If tied to VCC, write operations are inhibited but read operations are not affected. Up to eight devices (two for the MSOP package) may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. 2.2 Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz and 1 MHz). 2.4 3.0 Write-Protect (WP) FUNCTIONAL DESCRIPTION The 24XX128 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions while the 24XX128 works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.  2010 Microchip Technology Inc. DS21191S-page 5 24AA128/24LC128/24FC128 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device. 4.5 Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this Acknowledge bit. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus Not Busy (A) Both data and clock lines remain high. 4.2 Note: Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 A low-to-high transition of the SDA line, while the clock (SCL) is high, determines a Stop condition. All operations must end with a Stop condition. Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. FIGURE 4-1: (A) The 24XX128 does not generate any Acknowledge bits if an internal programming cycle is in progress. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX128) will leave the data line high to enable the master to generate the Stop condition. Stop Data Transfer (C) 4.4 Acknowledge DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA FIGURE 4-2: Data Allowed to Change Stop Condition ACKNOWLEDGE TIMING Acknowledge Bit 1 SCL SDA 2 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point, allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. DS21191S-page 6 8 9 1 2 3 Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.  2010 Microchip Technology Inc. 24AA128/24LC128/24FC128 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code. For the 24XX128, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX128 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are, in effect, the three Most Significant bits of the word address. For the MSOP package, the A0 and A1 pins are not connected. During device addressing, the A0 and A1 Chip Select bits (Figures 5-1 and 5-2) should be set to ‘0’. Only two 24XX128 MSOP packages can be connected to the same bus. The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is selected. When set to a zero, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because only A13…A0 are used, the upper two address bits are “don’t care” bits. The upper address bits are transferred first, followed by the Less Significant bits. Following the Start condition, the 24XX128 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a ‘1010’ code and appropriate device select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX128 will select a read or write operation. FIGURE 5-2: 0 1 Control Code Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Slave Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 1 Mbit by adding up to eight 24XX128 devices on the same bus. In this case, software can use A0 of the control byte as address bit A14; A1 as address bit A15; and A2 as address bit A16. It is not possible to sequentially read across device boundaries. For the MSOP package, up to two 24XX128 devices can be added for up to 256 Kbit of address space. In this case, software can use A2 of the control byte as address bit A16. Bits A0 (A14) and A1 (A15) of the control byte must always be set to logic ‘0’ for the MSOP. ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte 1 CONTROL BYTE FORMAT 0 A 2 A 1 Address High Byte A 0 R/W Chip Select Bits  2010 Microchip Technology Inc. x x A A A A 13 12 11 10 Address Low Byte A 9 A 8 A 7 • • • • • • A 0 x = “don’t care” bit DS21191S-page 7 24AA128/24LC128/24FC128 6.0 WRITE OPERATIONS 6.3 6.1 Byte Write The WP pin allows the user to write-protect the entire array (0000-3FFF) when the pin is tied to VCC. If tied to VSS the write protection is disabled. The WP pin is sampled at the Stop bit for every Write command (Figure 1-1). Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle. Following the Start condition from the master, the control code (four bits), the Chip Select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the Address Pointer of the 24XX128. The next byte is the Least Significant Address Byte. After receiving another Acknowledge signal from the 24XX128, the master device will transmit the data word to be written into the addressed memory location. The 24XX128 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and during this time, the 24XX128 will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written, and the device will immediately accept a new command. After a byte Write command, the internal address counter will point to the address location following the one that was just written. Note: 6.2 Note: Write Protection Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is, therefore, necessary for the application software to prevent page write operations that would attempt to cross a page boundary. When doing a write of less than 64 bytes the data in the rest of the page is refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page. Page Write The write control byte, word address, and the first data byte are transmitted to the 24XX128 in much the same way as in a byte write. The exception is that instead of generating a Stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer, and will be written into memory once the master has transmitted a Stop condition. Upon receipt of each word, the six lower Address Pointer bits are internally incremented by ‘1’. If the master should transmit more than 64 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. DS21191S-page 8  2010 Microchip Technology Inc. 24AA128/24LC128/24FC128 FIGURE 6-1: Bus Activity Master SDA Line BYTE WRITE S T A R T Control Byte AA S1010A 210 0 Address Low Byte S T O P Data xx A C K Bus Activity FIGURE 6-2: Address High Byte P A C K A C K A C K x = “don’t care” bit PAGE WRITE Bus Activity Master S T A R T SDA Line AAA S10102 100 Control Byte Bus Activity Address High Byte Address Low Byte S T O P Data Byte 63 Data Byte 0 P xx A C K A C K A C K A C K A C K x = “don’t care” bit 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (This feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for flow diagram. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation  2010 Microchip Technology Inc. DS21191S-page 9 24AA128/24LC128/24FC128 8.0 READ OPERATION 8.2 Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is done by sending the word address to the 24XX128 as part of a write operation (R/W bit set to ‘0’). Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a ‘1’. The 24XX128 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition, which causes the 24XX128 to discontinue transmission (Figure 8-2). After a random Read command, the internal address counter will point to the address location following the one that was just read. Read operations are initiated in much the same way as write operations with the exception that the R/W bit of the control byte is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX128 contains an address counter that maintains the address of the last word accessed, internally incremented by ‘1’. Therefore, if the previous read access was to address ‘n’ (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to ‘1’, the 24XX128 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24XX128 discontinues transmission (Figure 8-1). FIGURE 8-1: 8.3 S T A R T SDA Line S 1 0 1 0 A AA 1 2 1 0 FIGURE 8-2: N O A C K RANDOM READ S T A R T Bus Activity Master SDA Line P A C K Bus Activity S T O P Data Byte Control Byte Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24XX128 transmits the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random read. This acknowledge directs the 24XX128 to transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a Stop condition. To provide sequential reads, the 24XX128 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address 3FFF to address 0000 if the master acknowledges the byte received from the array address 3FFF. CURRENT ADDRESS READ Bus Activity Master Random Read Control Byte Address High Byte S1 01 0 AAA0 2 1 0 xx A C K A C K Bus Activity S T A R T Address Low Byte A C K Control Byte S 1 0 1 0 A A A1 2 1 0 S T O P Data Byte P N O A C K A C K x = “don’t care” bit FIGURE 8-3: Bus Activity Master SEQUENTIAL READ Control Byte Data (n) Data (n + 1) S T O P Data (n + x) Data (n + 2) P SDA Line Bus Activity DS21191S-page 10 A C K A C K A C K A C K N O A C K  2010 Microchip Technology Inc. 24AA128/24LC128/24FC128 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC (3.90 mm) XXXXXXXT XXXXYYWW NNN 8-Lead SOIC (5.28 mm) XXXXXXXX T/XXXXXX YYWWNNN 8-Lead TSSOP Example: 24AA128 I/P e3 017 0510 Example: 24LC128I SN e3 0510 017 Example: 24LC128 I/SM e3 0510017 Example: XXXX TYWW NNN 8-Lead Chip Scale XXXXXXX YYWWNNN  2010 Microchip Technology Inc. 4LC I510 017 Example: 24AA128 0810017 DS21191S-page 11 24AA128/24LC128/24FC128 Package Marking Information (Continued) 8-Lead MSOP Example: XXXXXT 4L128I YWWNNN 051017 Example: 8-Lead DFN-S 24LC128 I/MF 0510 017 XXXXXXX T/XXXXX YYWW NNN 8-Lead 2x3 TDFN Example: XXX YWW NN A84 510 I7 First Line Marking Codes Part Number TSSOP MSOP TDFN I-Temp E-Temp 24AA128 4AC 4A128T A81 — 24LC128 4LC 4L128T A84 A85 24FC128 4FC 4F128T A8A — Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. *Standard device marking consists of Microchip part number, year code, week code, and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 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