24AA16/24LC16B/24FC16
16K I2C Serial EEPROM
Device Selection Table
Part Number
VCC Range
Max. Clock Frequency
400 kHz
Temp. Ranges
(1)
Available Packages
I, E
MC, MS, P, SN, MNY, ST, OT, CSP
24AA16
1.7V-5.5V
24LC16B
2.5V-5.5V
400 kHz
I, E
MC, MS, P, SN, MNY, ST, OT
24FC16
1.7V-5.5V
1 MHz
I, E
MS, P, SN, ST, MUY, OT
Note 1: 100 kHz for VCC < 2.5V.
Features
Packages
• Single Supply with Operation down to 1.7V for
24AA16 and 24FC16 Devices, 2.5V for 24LC16B
Devices
• Low-Power CMOS Technology:
- Read current 1 mA, maximum
- Standby current 1 μA, maximum (I-temp.)
• Two-Wire Serial Interface, I2C Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz, 400 kHz and 1 MHz Compatibility
• Page Write Time: 5 ms, Maximum
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
• Automotive AEC-Q100 Qualified
• 8-Lead DFN, 8-Lead MSOP, 8-Lead PDIP, 8-Lead
SOIC, 8-Lead TDFN, 8-Lead TSSOP, 8-Lead
UDFN, 5-Lead SOT-23 and 5-Ball CSP
Description
The Microchip Technology Inc. 24XX16(1) is a 16-Kbit
Electrically Erasable PROM. The device is organized
as eight blocks of 256 x 8-bit memory with a two-wire
serial interface. Its low-voltage design permits
operation down to 1.7V with standby and active
currents of only 1 μA and 1 mA, respectively. The
24XX16 also has a page write capability for up to
16 bytes of data.
Note 1: 24XX16 is used in this document as a
generic
part
number
for
the
24AA16/24LC16B/24FC16 devices.
Package Types
8-Lead PDIP/MSOP
(Top View)
8-Lead DFN/TDFN/UDFN
(Top View)
A0(1) 1
8
VCC
A1(1)
2
7
WP
A2(1) 3
VSS 4
6
5
SCL
SDA
Note 1:
A0(1)
11
88
VCC
A1(1)
22
77
A2
33
66
WP
SCL
VSS
44
55
SDA
(1)
8-Lead SOIC/TSSOP
(Top View)
A0(1)
A1(1)
1
8
VCC
2
7
WP
A2(1)
3
6
SCL
VSS
4
5
SDA
5-Ball CSP
(Top View)
5-Lead SOT-23
(Top View)
SCL
1
VSS
2
SDA
3
5
WP
VCC
1
WP
4
VCC
SCL
2
VSS
5
SDA
3
4
Pins A0, A1 and A2 are not used by the 24XX16 (no internal connections).
2002-2019 Microchip Technology Inc.
DS20001703M-page 1
24AA16/24LC16B/24FC16
Block Diagram
WP
I/O
Control
Logic
Memory
Control
Logic
HV Generator
XDEC
EEPROM
Array
Page Latches
I/O
SCL
YDEC
SDA
VCC
VSS
2002-2019 Microchip Technology Inc.
Sense Amp.
R/W Control
DS20001703M-page 2
24AA16/24LC16B/24FC16
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
Symbol
No.
Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC16B)
Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC16)
Characteristic
Min.
Typical
Max.
Units
Conditions
D1
VIH
High-Level Input Voltage
0.7 VCC
—
—
V
D2
VIL
Low-Level Input Voltage
—
—
0.3 VCC
V
D3
VHYS
0.05 VCC
—
—
V
Note
D4
VOL
Low-Level Output
Voltage
—
—
0.40
V
IOL = 3.0 mA, VCC = 2.5V
D5
ILI
Input Leakage Current
—
—
±1
μA
VIN = VSS or VCC
D6
ILO
Output Leakage Current
—
—
±1
μA
VOUT = VSS or VCC
D7
CIN,
COUT
Pin Capacitance
(all inputs/outputs)
—
—
10
pF
VCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
D8
ICCWRITE Operating Current
—
—
3
mA
VCC = 5.5V, SCL = 400 kHz
D9
ICCREAD
—
—
1
mA
VCC = 5.5V, SCL = 400 kHz
D10
ICCS
—
—
1
μA
SDA = SCL = VCC
WP = VSS, I-Temp.
—
—
3
μA
SDA = SCL = VCC
WP = VSS, E-Temp. (24FC16)
—
—
5
μA
SDA = SCL = VCC
WP = VSS, E-Temp. (24LC16B)
Note:
Hysteresis of Schmitt
Trigger Inputs
Standby Current
This parameter is periodically sampled and not 100% tested.
2002-2019 Microchip Technology Inc.
DS20001703M-page 3
24AA16/24LC16B/24FC16
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
Symbol
No.
1
FCLK
2
THIGH
3
TLOW
4
TR
5
TF
6
Characteristic
Clock Frequency
Clock High Time
Clock Low Time
SDA and SCL Rise Time
SDA and SCL Fall Time
THD:STA Start Condition Hold Time
TSU:STA Start Condition Setup
Time
7
8
THD:DAT Data Input Hold Time
9
TSU:DAT Data Input Setup Time
Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC16B)
Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC16)
Min.
Max.
Units
—
400
kHz
Conditions
2.5V ≤ VCC ≤ 5.5V
—
100
kHz
1.7V ≤ VCC < 2.5V (24AA16)
—
1000
kHz
1.7V ≤ VCC ≤ 5.5V (24FC16)
600
—
ns
2.5V ≤ VCC ≤ 5.5V
4000
—
ns
1.7V ≤ VCC < 2.5V (24AA16)
260
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16)
1300
—
ns
2.5V ≤ VCC ≤ 5.5V
4700
—
ns
1.7V ≤ VCC < 2.5V (24AA16)
500
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16)
—
300
ns
2.5V ≤ VCC ≤ 5.5V (Note 1)
—
1000
ns
1.7V ≤ VCC < 2.5V (24AA16) (Note 1)
—
1000
ns
1.7V ≤ VCC ≤ 5.5V (24FC16) (Note 1)
—
300
ns
Note 1
600
—
ns
2.5V ≤ VCC ≤ 5.5V
4000
—
ns
1.7V ≤ VCC < 2.5V (24AA16)
250
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16)
600
—
ns
2.5V ≤ VCC ≤ 5.5V
4700
—
ns
1.7V ≤ VCC < 2.5V (24AA16)
250
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16)
0
—
ns
Note 2
100
—
ns
2.5V ≤ VCC ≤ 5.5V
250
—
ns
1.7V ≤ VCC < 2.5V (24AA16)
50
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16)
TSU:STO Stop Condition Setup
Time
600
—
ns
2.5V ≤ VCC ≤ 5.5V
4000
—
ns
1.7V ≤ VCC < 2.5V (24AA16)
250
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16)
11
TSU:WP
600
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16)
12
THD:WP WP Hold Time
10
13
TAA
14
TBUF
Note 1:
2:
3:
4:
WP Setup Time
Output Valid from Clock
Bus Free Time: The time
the bus must be free
before a new transmission can start
600
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16)
—
900
ns
2.5V ≤ VCC ≤ 5.5V (Note 2)
—
3500
ns
1.7V ≤ VCC < 2.5V (24AA16) (Note 2)
—
450
ns
1.7V ≤ VCC ≤ 5.5V (24FC16) (Note 2)
1300
—
ns
2.5V ≤ VCC ≤ 5.5V
4700
—
ns
1.7V ≤ VCC < 2.5V (24AA16)
500
—
ns
1.7V ≤ VCC ≤ 5.5V (24FC16)
Characterized but not 100% tested.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
CB = total capacitance of one bus line in pF.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
2002-2019 Microchip Technology Inc.
DS20001703M-page 4
24AA16/24LC16B/24FC16
AC CHARACTERISTICS (Continued)
Param.
Symbol
No.
15
Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC16B)
Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC16)
Characteristic
TOF
Min.
Output Fall Time from VIH 20+0.1CB
Minimum to VIL Maximum
—
16
TSP
17
TWC
18
3:
4:
Conditions
250
ns
2.5V ≤ VCC ≤ 5.5V
(Notes 1, 3 and 4)
250
ns
1.7V ≤ VCC < 2.5V (24AA16)
(Notes 1, 3 and 4)
—
50
ns
Note 1
—
100
ns
1.7V ≤ VCC ≤ 5.5V (24FC16) (Note 1)
Write Cycle Time
(byte or page)
—
5
ms
1,000,000
—
cycles 25°C, 5.5V, Page Mode (Note 4)
Characterized but not 100% tested.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
CB = total capacitance of one bus line in pF.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
FIGURE 1-1:
BUS TIMING DATA
5
SCL
Units
Input Filter Spike
Suppression
(SDA and SCL pins)
Endurance
Note 1:
2:
Max.
7
SDA
IN
3
4
D3
2
8
10
9
6
16
14
13
SDA
OUT
WP
2002-2019 Microchip Technology Inc.
(protected)
(unprotected)
11
12
DS20001703M-page 5
24AA16/24LC16B/24FC16
FIGURE 1-2:
BUS TIMING START/STOP
D3
SCL
6
7
10
SDA
Start
2002-2019 Microchip Technology Inc.
Stop
DS20001703M-page 6
24AA16/24LC16B/24FC16
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name
DFN(1)
MSOP
PDIP
SOIC
TDFN(1) TSSOP UDFN(1)
A0
1
1
1
1
1
1
A1
2
2
2
2
2
A2
3
3
3
3
3
SOT-23
CSP
Description
1
—
—
Not Connected
2
2
—
—
Not Connected
3
3
—
—
Not Connected
VSS
4
4
4
4
4
4
4
2
2
Ground
SDA
5
5
5
5
5
5
5
3
5
Serial Address/Data I/O
SCL
6
6
6
6
6
6
6
1
4
Serial Clock
WP
7
7
7
7
7
7
7
5
3
Write-Protect Input
8
8
8
8
8
8
8
4
1
Power Supply
VCC
Note 1:
2.1
The exposed pad on the DFN/TDFN/UDFN package can be connected to VSS or left floating.
A0, A1, A2
2.3
Serial Clock (SCL)
The A0, A1 and A2 pins are not used by the 24XX16.
They may be left floating or tied to either VSS or VCC.
The SCL input is used to synchronize the data transfer
to and from the device.
2.2
2.4
Serial Address/Data Input/Output
(SDA)
The SDA input is a bidirectional pin used to transfer
addresses and data into and out of the device. Since
it is an open-drain terminal, the SDA bus requires a
pull-up resistor to VCC (typical 10 kΩ for 100 kHz,
2 kΩ for 400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2002-2019 Microchip Technology Inc.
Write-Protect (WP)
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to VCC, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
DS20001703M-page 7
24AA16/24LC16B/24FC16
3.0
FUNCTIONAL DESCRIPTION
The 24XX16 supports a bidirectional, two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX16 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
4.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (although only the last sixteen
will be stored when doing a write operation). When an
overwrite does occur, it will replace data based on the
first-in first-out (FIFO) principle.
4.5
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 4-1:
(A)
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
Bus Not Busy (A)
Data Valid (D)
The 24XX16 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the Acknowledge-related clock pulse.
Moreover, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX16) will leave the data line
high to enable the master to generate the Stop
condition.
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SCL
SDA
2002-2019 Microchip Technology Inc.
Data
Allowed
to Change
Stop
Condition
DS20001703M-page 8
24AA16/24LC16B/24FC16
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists of a 4-bit control code. For the 24XX16, this is
set as ‘1010’ binary for read and write operations. The
next three bits of the control byte are the block-select
bits (B2, B1, B0). They are used by the master device
to select which of the eight 256-word blocks of memory
are to be accessed. These bits, in effect, are the three
Most Significant bits of the word address. It should be
noted that the protocol limits the size of the memory to
eight blocks of 256 words, therefore, the protocol can
support only one 24XX16. per system. The
combination of the 4-bit control code and the next three
bits are called the slave address.
The last bit of the control byte is the Read/Write (R/W)
bit and it defines the operation to be performed. When
set to ‘1’, a read operation is selected. When set to ‘0’,
a write operation is selected. Following the Start
condition, the 24XX16 monitors the SDA bus, checking
the device type identifier being transmitted. Upon
receiving a valid slave address and the R/W bit, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX16 will select a read or write operation.
Operation
Control
Code
Block Select
R/W
Read
1010
Block Address
1
Write
1010
Block Address
0
FIGURE 5-1:
CONTROL BYTE
ALLOCATION
Read/Write Bit
Block
Select
Bits
Control Code
S
1
0
1
0
B2 B1 B0 R/W ACK
Slave Address
Acknowledge Bit
Start Bit
The next byte received defines the address of the first
data byte within the selected block (Figure 5-2). The
word address byte uses all eight bits.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
1
0
1
0
Control
Code
2002-2019 Microchip Technology Inc.
B2 B1 B0 R/W
Word Address Byte
A7
•
•
•
•
•
•
A0
Block
Select
Bits
DS20001703M-page 9
24AA16/24LC16B/24FC16
6.0
WRITE OPERATION
6.1
Byte Write
6.2
Following the Start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic-low, are placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24XX16. After
receiving another Acknowledge signal from the
24XX16, the master device will transmit the data word
to be written into the addressed memory location. The
24XX16 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and, during this time, the 24XX16 will not
generate Acknowledge signals (Figure 6-1).
Page Write
The write control byte, word address and first data byte
are transmitted to the 24XX16 in the same way as in a
byte write. However, instead of generating a Stop
condition, the master transmits up to 16 data bytes to
the 24XX16, which are temporarily stored in the
on-chip page buffer and will be written into the memory
once the master has transmitted a Stop condition.
Upon receipt of each word, the four lower-order
Address Pointer bits, which form the byte counter, are
internally incremented by one. The higher-order
four bits of the word address and bits B2, B1 and B0
remain constant. If the master should transmit more
than 16 words prior to generating the Stop condition,
the Address Pointer will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2).
Note:
6.3
Page write operations are limited to writing bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of page size – 1. If a
page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Write Protection
The WP pin allows the user to write-protect the entire
array (000-7FF) when the pin is tied to VCC. If tied to
VSS, the write protection is disabled.
FIGURE 6-1:
BYTE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
1 0
Word
Address
S
T
O
P
Data
1 0 B2 B1 B0 0
Bus Activity
2002-2019 Microchip Technology Inc.
Block
Select
Bits
P
A
C
K
A
C
K
A
C
K
DS20001703M-page 10
24AA16/24LC16B/24FC16
FIGURE 6-2:
PAGE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S 1 0 1 0 B2 B1 B0 0
Bus Activity
Control
Byte
Block
Select
Bits
2002-2019 Microchip Technology Inc.
Word
Address (n)
Data (n + 1)
Data (n)
S
T
O
P
Data (n + 15)
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DS20001703M-page 11
24AA16/24LC16B/24FC16
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally-timed write cycle. ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a write command (R/W = 0). If the device is still
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next read or write
operation. See Figure 7-1 for a flow diagram of this
operation.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
2002-2019 Microchip Technology Inc.
DS20001703M-page 12
24AA16/24LC16B/24FC16
8.0
READ OPERATION
8.3
Sequential Read
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
Sequential reads are initiated in the same way as a
random read or current read, except that once the
24XX16 transmits the first data byte, the master issues
an Acknowledge (as opposed to a Stop condition in a
random read). This directs the 24XX16 to transmit the
next sequentially addressed 8-bit word (Figure 8-3).
8.1
To provide sequential reads the 24XX16 contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
Current Address Read
The 24XX16 contains an Address Pointer that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the previous access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 24XX16
issues an Acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24XX16
discontinues transmission (Figure 8-1).
8.2
8.4
Noise Protection
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX16 as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the Acknowledge. This
terminates the write operation, but not before the internal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24XX16 will then issue an Acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX16 discontinues transmission (Figure 8-2).
FIGURE 8-1:
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
SDA Line
S 1 0 1 0 B2 B1 B0 1
Bus Activity
2002-2019 Microchip Technology Inc.
Control
Byte
Block
Select
Bits
S
T
O
P
Data (n)
P
A
C
K
N
o
A
C
K
DS20001703M-page 13
24AA16/24LC16B/24FC16
FIGURE 8-2:
RANDOM READ
S
T
Control
A
Byte
R
T
S 1 0 1 0 B2 B1 B0 0
Bus Activity
Master
SDA Line
FIGURE 8-3:
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte
S
T
O
P
P
Data (n)
S 1 0 1 0 B2B1B0 1
A
Block C
Select K
Bits
Bus Activity
S
T
A
R
T
Word
Address (n)
A
C
K
A
C
K
Block
Select
Bits
N
o
A
C
K
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + x)
P
1
A
C
K
2002-2019 Microchip Technology Inc.
A
C
K
A
C
K
A
C
K
N
o
A
C
K
DS20001703M-page 14
24AA16/24LC16B/24FC16
9.0
PACKAGING INFORMATION
9.1
Package Marking Information*
8-Lead 2x3 DFN
Example
XXX
YWW
NN
254
915
13
8-Lead MSOP
Example
XXXXXX
YWWNNN
4L16I
91513F
8-Lead PDIP (300 mil)
Example
XXXXXXXX
XXXXXNNN
YYWW
24LC16B
I/P e3 13F
1915
8-Lead SOIC (3.90 mm)
Example
XXXXXXXX
XXXXYYWW
24LC16BI
SN e3 1915
NNN
13F
8-Lead 2x3 TDFN
XXX
YWW
NN
2002-2019 Microchip Technology Inc.
Example
A51
915
13
DS20001703M-page 15
24AA16/24LC16B/24FC16
8-Lead TSSOP
Example
XXXX
4L16
XYWW
I915
NNN
13F
8-Lead 2x3 UDFN
XXX
YWW
NN
5-Lead SOT-23 (1-Line Marking)
XXNN
5-Lead SOT-23 (2-Line Marking)
XXXXYY
WWNNN
5-Ball CSP
XN
2002-2019 Microchip Technology Inc.
Example
ADR
915
13
Example
B513
Example
AAEZ19
1513F
Example
51
DS20001703M-page 16
24AA16/24LC16B/24FC16
Part Number
1st Line Marking Codes
DFN
I-Temp. E-Temp.
24AA16
251
24LC16B
24FC16
TDFN
254
—
—
255
—
MSOP
SOIC
4A16T(1)
24AA16T(1)
4L16T
(1)
24LC16BT
24FC16
24FC16
SOT-23
I-Temp. E-Temp.
(1)
A51
A54
—
EE9
A55
—
TSSOP UDFN
4A16
4L16
AADW
CSP
I-Temp.
E-Temp.
—
B5NN(2,3)
7VNN(2,3)
5N
—
(2,3)
N5NN(2,3)
—
(4)
(4)
—
ADR
M5NN
AAEZYY
AAEZYY
Note 1: T = Temperature grade (I, E)
2: NN = Alphanumeric traceability code
3: These parts use the 1-line SOT-23 marking format
4: These parts use the 2-line SOT-23 marking format
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
* Standard OTP marking consists of Microchip part number, year code, week code,
and traceability code.
Note:
For very small packages with no room for the JEDEC® designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2002-2019 Microchip Technology Inc.
DS20001703M-page 17
24AA16/24LC16B/24FC16
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