24LC16B
16K I2C Serial EEPROM
Extended (-55°C to +125°C) Operating Temperatures
Device Selection Table
Description
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
24LC16B
2.5V-5.5V
400 kHz
M
Features
• Single Supply with Operation down to 2.5V
• Low-Power CMOS Technology:
- Active current 1 mA, typical
- Standby current, 1 µA, typical
• 2-Wire Serial Interface, I2C Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms Maximum
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges:
- Extended (M): -55°C to +125°C
The Microchip Technology Inc. 24LC16B is a 16 Kbit
Electrically Erasable PROM. The device is organized
as eight blocks of 256 x 8-bit memory with a 2-wire
serial interface. Low-voltage design permits operation
down to 2.5V with standby and active currents of only
1 µA and 1 mA, respectively. The 24LC16B also has a
page write capability for up to 16 bytes of data. The
24LC16B is available in the standard 8-pin SOIC and
5-lead SOT-23 packages.
Package Types
SOT-23
SOIC
A0
1
8
VCC
SCL 1
5 WP
A1
2
7
WP
A2
3
6
SCL
VSS 2
SDA 3
4 VCC
VSS
4
5
SDA
Note:
Pins A0, A1 and A2 are not used by the
24LC16B (no internal connections).
Block Diagram
HV
Generator
WP
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
I/O
SCL
YDEC
SDA
VCC
VSS
2009-2016 Microchip Technology Inc.
Sense Amp.
R/W Control
DS20002213B-page 1
24LC16B
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-55°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Extended (M):
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
TA = -55°C to +125°C, VCC = +2.5V to +5.5V
Typ.(2)
Max.
Units
Conditions
D1
VIH
High-Level Input Voltage
0.7 VCC
—
—
V
D2
VIL
Low-Level Input Voltage
—
—
0.3 VCC
V
D3
VHYS
0.05 VCC
—
—
V
D4
VOL
Low-Level Output Voltage
—
—
0.40
V
IOL = 3.0 mA, VCC = 2.5V
D5
ILI
Input Leakage Current
—
—
±1
µA
VIN = VSS or VCC
D6
ILO
Output Leakage Current
—
—
±1
µA
VOUT = VSS or VCC
D7
CIN
Pin Capacitance
(all inputs/outputs)
—
—
10
pF
VCC = 5.0V (Note 1)
TA = 25°C, FCLK = 1 MHz
—
—
3
mA
VCC = 5.5V, SCL = 400 kHz
COUT
Hysteresis of Schmitt
Trigger Inputs
D8
ICCWRITE Operating current
D9
ICCREAD
D10
ICCS
Note 1:
2:
Standby Current
Note 1
—
0.01
1
mA
—
—
1
µA
+85°C, SDA = SCL = VCC
WP = VSS
—
—
5
µA
+125°C, SDA = SCL = VCC
WP = VSS
This parameter is periodically sampled and not 100% tested.
Typical measurements taken at room temperature.
DS20002213B-page 2
2009-2016 Microchip Technology Inc.
24LC16B
TABLE 1-2:
AC CHARACTERISTICS
Extended (M): TA = -55°C to +125°C, VCC = +2.5V to +5.5V
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
—
400
kHz
Conditions
1
FCLK
Clock Frequency
2
THIGH
Clock High Time
600
—
ns
3
TLOW
Clock Low Time
1300
—
ns
4
TR
SDA and SCL Rise Time
(Note 1)
—
300
ns
Note 1
TF
SDA and SCL Fall Time
—
300
ns
Note 1
600
—
ns
5
6
THD:STA Start Condition Hold Time
7
TSU:STA
Start Condition Setup Time
4000
—
ns
600
—
ns
8
THD:DAT Data Input Hold Time
0
—
ns
9
TSU:DAT Data Input Setup Time
100
—
ns
10
TSU:STO Stop Condition Setup Time
600
—
ns
—
900
ns
1300
—
ns
20+0.1CB
250
ns
Output Valid from Clock
(Note 2)
11
TAA
12
TBUF
13
TOF
Output Fall Time from VIH
Minimum to VIL Maximum
14
TSP
Input Filter Spike Suppression
(SDA and SCL pins)
—
50
ns
15
TWC
Write Cycle Time
(byte or page)
—
5
ms
Endurance
1M
—
16
Note 1:
2:
3:
4:
Bus Free Time: Bus time must
be free before a new
transmission can start
Note 2
Notes 1 and 3
cycles Page mode, +25°C, 5.5V
(Note 4)
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
2009-2016 Microchip Technology Inc.
DS20002213B-page 3
24LC16B
FIGURE 1-1:
BUS TIMING DATA
5
4
2
3
SCL
7
SDA
IN
8
10
9
6
14
12
11
SDA
OUT
FIGURE 1-2:
BUS TIMING START/STOP
D3
SCL
6
7
10
SDA
Start
DS20002213B-page 4
Stop
2009-2016 Microchip Technology Inc.
24LC16B
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
PIN FUNCTION TABLE
Name
8-pin SOIC
5-pin SOT-23
A0
1
—
Not Connected
A1
2
—
Not Connected
A2
3
—
Not Connected
VSS
4
2
Ground
SDA
5
3
Serial Address/Data I/O
SCL
6
1
Serial Clock
WP
7
5
Write-Protect Input
VCC
8
4
+2.5V to +5.5V Power Supply
Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an
open-drain terminal, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.2
Serial Clock (SCL)
Description
2.3
Write-Protect (WP)
The WP pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to VCC, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
2.4
A0, A1, A2
The A0, A1 and A2 pins are not used by the 24LC16B.
They may be left floating or tied to either VSS or VCC.
The SCL input is used to synchronize the data transfer
to and from the device.
2009-2016 Microchip Technology Inc.
DS20002213B-page 5
24LC16B
3.0
FUNCTIONAL DESCRIPTION
The 24LC16B supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24LC16B works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur it will replace data in a first-in first-out (FIFO)
fashion.
4.5
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
FIGURE 4-1:
(A)
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
Note:
4.1
Data Valid (D)
The 24LC16B does not generate any
Acknowledge bits
if an internal
programming cycle is in progress.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by not generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24LC16B) will leave the data line high to enable
the master to generate the Stop condition.
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SCL
SDA
DS20002213B-page 6
Data
Allowed
to Change
Stop
Condition
2009-2016 Microchip Technology Inc.
24LC16B
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code.
For the 24LC16B, this is set as ‘1010’ binary for read
and write operations. The next three bits of the control
byte are the Block Select bits (B2, B1, B0). They are
used by the master device to select which of the eight
256 word-blocks of memory are to be accessed.
These bits are, in effect, the three Most Significant bits
(MSb) of the word address. It should be noted that the
protocol limits the size of the memory to eight blocks
of 256 words, therefore, the protocol can support only
one 24LC16B per system.
The last bit of the Control byte defines the operation to
be performed. When set to ‘1’, a read operation is
selected. When set to ‘0’, a write operation is selected.
Following the Start condition, the 24LC16B monitors
the SDA bus, checking the device type identifier being
transmitted and, upon receiving a ‘1010’ code, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24LC16B will select a read or write operation.
FIGURE 5-2:
Control
Code
Block Select
R/W
Read
1010
Block Address
1
Write
1010
Block Address
0
Operation
FIGURE 5-1:
CONTROL BYTE
ALLOCATION
Read/Write Bit
Block
Select
Bits
Control Code
S
1
0
1
0
B2 B1 B0 R/W ACK
Slave Address
Acknowledge Bit
Start Bit
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
1
0
1
0
B
2
Control
Code
2009-2016 Microchip Technology Inc.
B
1
Address Low Byte
B
0 R/W
A
7
•
•
•
•
•
•
A
0
Block
Select
Bits
DS20002213B-page 7
24LC16B
6.0
WRITE OPERATION
6.1
Byte Write
Following the Start condition from the master, the
device code (four bits), the block address (three bits)
and the R/W bit, which is a logic low, are placed onto
the bus by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow once it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the word address and will be written into the Address
Pointer of the 24LC16B. After receiving another
Acknowledge signal from the 24LC16B, the master
device will transmit the data word to be written into the
addressed
memory
location.
The
24LC16B
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and,
during this time, the 24LC16B will not generate
Acknowledge signals (Figure 6-1).
Note:
6.2
When doing a write of less than 16 bytes,
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle; for this reason,
endurance is specified per page.
Note:
6.3
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page-size’) and end at addresses that
are integer multiples of [page size – 1]. If
a Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Write Protection
The WP pin allows the user to write-protect the entire
array (000-7FF) when the pin is tied to VCC. If tied to
VSS, the write protection is disabled.
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC16B in the same way
as in a byte write. However, instead of generating a
Stop condition, the master transmits up to 16 data bytes
to the 24LC16B, which are temporarily stored in the
on-chip page buffer and will be written into memory
once the master has transmitted a Stop condition.
Upon receipt of each word, the four lower-order
Address Pointer bits are internally incremented by one.
The higher-order 7 bits of the word address remain
constant. If the master should transmit more than
16 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 6-2).
DS20002213B-page 8
2009-2016 Microchip Technology Inc.
24LC16B
FIGURE 6-1:
BYTE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
1
1
P
A
C
K
A
C
K
A
C
K
PAGE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S 1 0 1 0 B2 B1B0 0
Bus Activity
S
T
O
P
Data
0 B2 B1 B0 0
Block
Select
Bits
Bus Activity
FIGURE 6-2:
0
Word
Address
Word
Address (n)
Control
Byte
Block
Select
Bits
2009-2016 Microchip Technology Inc.
Data (n + 1)
Data (n)
S
T
O
P
Data (n + 15)
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DS20002213B-page 9
24LC16B
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally-timed write cycle and ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W = 0). If the device is still
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next Read or
Write command. See Figure 7-1 for a flow diagram of
this operation.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
DS20002213B-page 10
2009-2016 Microchip Technology Inc.
24LC16B
8.0
READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
8.4
Noise Protection
The 24LC16B employs a VCC threshold detector circuit
which disables the internal erase/write logic if the Vcc
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
Current Address Read
The 24LC16B contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address ‘n’, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 24LC16B
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24LC16B
discontinues transmission (Figure 8-1).
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24LC16B as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the internal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24LC16B will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24LC16B will discontinue transmission (Figure 8-2).
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read, except that once the 24LC16B transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24LC16B to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24LC16B contains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
2009-2016 Microchip Technology Inc.
DS20002213B-page 11
24LC16B
FIGURE 8-1:
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
1 0
1
Bus Activity
FIGURE 8-2:
Bus Activity
Master
0 B2 B1 B0 1
A
C
K
RANDOM READ
S
T
A
R
T
Control
Byte
Block
Select
Bits
Bus Activity
SDA Line
Bus Activity
N
o
A
C
K
S
T
A
R
T
Word
Address (n)
S 1 0 1 0 B2B1B0 0
Bus Activity
Master
P
Block
Select
Bits
SDA Line
FIGURE 8-3:
S
T
O
P
Data (n)
Control
Byte
S
T
O
P
Data (n)
P
S 1 0 1 0 B2 B1B0 1
A
C
K
A
C
K
Block
Select
Bits
A
C
K
N
o
A
C
K
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + x)
P
1
A
C
K
A
C
K
A
C
K
A
C
K
N
o
A
C
K
DS20002213B-page 12
2009-2016 Microchip Technology Inc.
24LC16B
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead SOIC (3.90 mm)
Example:
XXXXXXXT
XXXXYYWW
NNN
24LC16BM
SN e3 1606
13F
5-Lead SOT-23
Example:
AADN6
061L7
1st Line Marking Codes
Part Number
24LC16B
Legend: XX...X
T
Y
YY
WW
NNN
e3
SOIC
SOT-23
24LC16BT
AADNY
Part number or part number code
Temperature (M)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
Note:
For very small packages with no room for the JEDEC® designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
2009-2016 Microchip Technology Inc.
DS20002213B-page 13
24LC16B
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002213B-page 14
2009-2016 Microchip Technology Inc.
24LC16B
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2016 Microchip Technology Inc.
DS20002213B-page 15
24LC16B
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DS20002213B-page 16
2009-2016 Microchip Technology Inc.
24LC16B
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