24LC21A/SN

24LC21A 1K 2.5V Dual Mode I2C™ Serial EEPROM PDIP NC 1 8 Vcc NC 2 7 VCLK NC 3 6 SCL VSS 4 5 SDA NC 1 8 Vcc NC 2 7 VCLK NC 3 6 SCL Vss 4 5 SDA 24LC21A • Single Supply with Operation Down to 2.5V • Completely Implements DDC1™/DDC2™ Interface for Monitor Identification, Including Recovery to DDC1 • Pin and Function Compatible with 24LC21 • Low-Power CMOS Technology - 1 mA typical active current - 10 μA standby current typical at 5.5V • 2-Wire Serial Interface Bus, I2C™ Compatible • 100 kHz (2.5V) and 400 kHz (5V) Compatibility • Self-Timed Write Cycle (including auto-erase) • Page Write Buffer for up to Eight Bytes • 1,000,000 Erase/Write Cycles Ensured • Data Retention > 200 years • ESD Protection > 4000V • 8-pin PDIP and SOIC Package • Available for Extended Temperature Ranges - Industrial (I): -40°C to +85°C • Pb-Free and RoHS Compliant Package Types SOIC 24LC21A Features: Block Diagram Description: HV Generator The Microchip Technology Inc. 24LC21A is a 128 x 8-bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: Transmit-Only mode and Bidirectional mode. Upon power-up, the device will be in the Transmit-Only mode, sending a serial bit stream of the memory array from 00h to 7Fh, clocked by the VCLK pin. A valid high-to-low transition on the SCL pin will cause the device to enter the transition mode, and look for a valid control byte on the I2C bus. If it detects a valid control byte from the master, it will switch into Bidirectional mode, with byte selectable read/write capability of the memory array using SCL. If no control byte is received, the device will revert to the Transmit-Only mode after it receives 128 consecutive VCLK pulses while the SCL pin is idle. The 24LC21A is available in a standard 8-pin PDIP and SOIC package in industrial temperature range. DDC is a trademark of the Video Electronics Standards Association. I2C is a trademark of Philips Corporation. © 2008 Microchip Technology Inc. I/O Control Logic Memory Control Logic EEPROM Array XDEC Page Latches SDA SCL YDEC VCLK Sense AMP R/W Control VCC VSS Pin Function Table Name Function VSS SDA SCL VCLK VCC NC Ground Serial Address/Data I/O Serial Clock (Bidirectional mode) Serial Clock (Transmit-Only mode) +2.5V to 5.5V Power Supply No Connection DS21160G-page 1 24LC21A 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS .........................................................................................................................................-0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Parameter VCC = +2.5V to 5.5V Industrial (I): TA =-40°C to +85°C Symbol Min. Max. Units Conditions SCL and SDA pins: High-level input voltage Low-level input voltage VIH VIL 0.7 VCC — — 0.3 VCC V V Input levels on VCLK pin: High-level input voltage Low-level input voltage VIH VIL 2.0 — — 0.2 VCC V V VCC ≥ 2.7V (Note) VCC < 2.7V (Note) Hysteresis of Schmitt Trigger inputs VHYS .05 VCC — V (Note) Low-level output voltage VOL1 — 0.4 V IOL = 3 mA, VCC = 2.5V (Note) Low-level output voltage VOL2 — 0.6 V IOL = 6 mA, VCC = 2.5V Input leakage current ILI — ±1 μA VIN = 0.1V to VCC Output leakage current ILO — ±1 μA VOUT = 0.1V to VCC Pin capacitance (all inputs/outputs) CIN, COUT — 10 pF VCC = 5.0V (Note) TA = 25°C, FCLK = 1 MHz Operating current ICC Write ICC Read — — 3 1 mA mA VCC = 5.5V VCC = 5.5V, SCL = 400 kHz Standby current ICCS — — 30 100 μA μA VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC VCLK = VSS Note: This parameter is periodically sampled and not 100% tested. DS21160G-page 2 © 2008 Microchip Technology Inc. 24LC21A TABLE 1-2: AC CHARACTERISTICS Parameter Symbol Vcc = 2.5-5.5V Standard Mode Vcc = 4.5 - 5.5V Fast Mode Min. Max. Min. Max. Units Remarks Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition hold time FCLK THIGH TLOW TR TF THD:STA — 4000 4700 — — 4000 100 — — 1000 300 — — 600 1300 — — 600 400 — — 300 300 — kHz ns ns ns ns ns Start condition setup time TSU:STA 4700 — 600 — ns Data input hold time Data input setup time Stop condition setup time Output valid from clock Bus free time THD:DAT TSU:DAT TSU:STO TAA TBUF 0 250 4000 — 4700 — — — 3500 — 0 100 600 — 1300 — — — 900 — ns ns ns ns ns — 250 250 ns — 50 20 + 0.1 CB — (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB ≤ 100 pF 50 ns (Note 3) — 10 — 10 ms Byte or Page mode — 4000 4700 0 4000 — 0 2000 — — — — 1000 — — 600 1300 0 600 — 0 1000 — — — — 500 — ns ns ns ns ns ns ns — 100 — 100 ns 1M — 1M — cycles TOF Output fall time from VIH minimum to VIL maximum Input filter spike suppres- TSP sion (SDA and SCL pins) Write cycle time TWR Transmit-Only Mode Parameters Output valid from VCLK TVAA VCLK high time TVHIGH VCLK low time TVLOW VCLK setup time TVHST VCLK hold time TSPVL Mode transition time TVHZ Transmit-only power-up TVPU time Input filter spike suppres- TSPV sion (VCLK pin) Endurance — Note 1: 2: 3: 4: (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated Start condition (Note 2) 25°C, Vcc = 5.0V, Block mode (Note 4) Not 100% tested. CB = Total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide noise and spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. © 2008 Microchip Technology Inc. DS21160G-page 3 24LC21A 2.0 FUNCTIONAL DESCRIPTION it be initialized prior to valid data being sent in the Transmit-Only mode (Section 2.2 “Initialization Procedure”). In this mode, data is transmitted on the SDA pin in 8-bit bytes, with each byte followed by a ninth, null bit (Figure 2-1). The clock source for the TransmitOnly mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted Most Significant bit first. Each byte within the memory array will be output in sequence. After address 7Fh in the memory array is transmitted, the internal Address Pointers will wrap around to the first memory location (00h) and continue. The Bidirectional mode Clock (SCL) pin must be held high for the device to remain in the Transmit-Only mode. The 24LC21A is designed to comply to the DDC Standard proposed by VESA (Figure 3-3) with the exception that it is not Access.bus capable. It operates in two modes, the Transmit-Only mode and the Bidirectional mode. There is a separate 2-wire protocol to support each mode, each having a separate clock input but sharing a common data line (SDA). The device enters the Transmit-Only mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high-to-low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the Bidirectional mode and look for its control byte to be sent by the master. If it detects its control byte, it will stay in the Bidirectional mode. Otherwise, it will revert to the Transmit-Only mode after it sees 128 VCLK pulses. 2.1 2.2 After VCC has stabilized, the device will be in the Transmit-Only mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal sychronization. During this period, the SDA pin will be in a high-impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the Most Significant bit in address 00h. (Figure 2-2). Transmit-Only Mode The device will power-up in the Transmit-Only mode at address 00h. This mode supports a unidirectional 2-wire protocol for continuous transmission of the contents of the memory array. This device requires that FIGURE 2-1: Initialization Procedure TRANSMIT-ONLY MODE SCL Tvaa Tvaa SDA Null Bit Bit 1 (LSB) Bit 1 (MSB) Bit 7 VCLK Tvhigh Tvlow FIGURE 2-2: DEVICE INITIALIZATION Vcc SCL SDA Tvaa High-Impedance for 9 Clock Cycles Tvaa Bit 8 Bit 7 Tvpu VCLK DS21160G-page 4 1 2 8 9 10 11 © 2008 Microchip Technology Inc. 24LC21A 3.0 BIDIRECTIONAL MODE Once the device has switched into the Bidirectional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire Bidirectional data transmission protocol (I2C™). In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. The bus must be controlled by a master device that generates the Bidirectional mode clock (SCL), controls access to the bus and generates the Start and Stop conditions, while the 24LC21A acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. In the Bidirectional mode, the 24LC21A only responds to commands for device ‘1010 000X’. Before the 24LC21A can be switched into the Bidirectional mode (Figure 3-1), it must enter the Transition mode, which is done by applying a valid high-to-low transition on the Bidirectional mode clock (SCL). As soon it enters the Transition mode, it looks for a control byte ‘1010 000X’ on the I2C™ bus, and starts to count pulses on VCLK. Any high-to-low transition on the SCL line will reset the count. If it sees a pulse count of 128 on VCLK while the SCL line is idle, it will revert back to the Transmit-Only mode, and transmit its contents starting with the Most Significant bit in address 00h. However, if it detects the control byte on the I2C™ bus, (Figure 3-2) it will switch to the in the Bidirectional mode. Once the device has made the transition to the Bidirectional mode, the only way to switch the device back to the Transmit-Only mode is to remove power from the device. The mode transition process is shown in detail in Figure 3-3. FIGURE 3-1: MODE MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE Transmit-Only Recovery to Transmit-Only mode Bidirectional TVHZ SCL (MSB of data in 00h) Bit 8 SDA VCLK count = VCLK FIGURE 3-2: 1 2 3 4 127 128 SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE Transition mode with possibility to return to Transmit-Only mode Transmit-Only MODE Bidirectional permanently SCL SDA VCLK count = VCLK 1 2 n S 1 0 0 1 0 0 0 0 0 ACK n < 128 © 2008 Microchip Technology Inc. DS21160G-page 5 24LC21A DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA® FIGURE 3-3: The 24LC21A was designed to comply to the portion of flowchart inside dash box Display Power-on or DDC Circuit Powered from +5 volts Communication is idle Is Vsync present? No Yes High-to-Low transition on SCL? Send EDID continuously using Vsync as clock No Yes High-to-Low transition on SCL? No Yes Stop sending EDID. Switch to DDC2™ mode. Display has optional transition state ? DDC2 communication idle. Display waiting for address byte. No DDC2B address received? Yes Set Vsync counter = 0 or start timer Yes Receive DDC2B command No Reset counter or timer Respond to DDC2B command Change on SCL, SDA or VCLK lines? No Yes No Is display Access.busTM capable? High-Low transition on SCL ? Yes Yes Reset Vsync counter = 0 Valid DDC2 address received? No Valid Access.bus address? No Yes Yes No No VCLK cycle? See Access.bus specification to determine correct procedure. Yes Increment VCLK counter (if appropriate) No Counter=128 or timer expired? Yes Switch back to DDC1™ mode. Note 1: The base flowchart is copyright © 1993, 1994, 1995 Video Electronic Standard Association (VESA) from VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA. 2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology Inc. 3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A. DS21160G-page 6 © 2008 Microchip Technology Inc. 24LC21A 3.1 Bidirectional Mode Bus Characteristics The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. When an overwrite does occur it will replace data in a first-in firstout (FIFO) fashion. Note: Accordingly, the following bus conditions have been defined (Figure 3-4). 3.1.1 BUS NOT BUSY (A) 3.1.5 Both data and clock lines remain high. 3.1.2 START DATA TRANSFER (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 3.1.3 3.1.4 DATA VALID (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. FIGURE 3-4: (A) ACKNOWLEDGE Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: STOP DATA TRANSFER (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. Once switched into Bidirectional mode, the 24LC21A will remain in that mode until power is removed. Removing power is the only way to reset the 24LC21A into the Transmit-Only mode. The 24LC21A does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA © 2008 Microchip Technology Inc. Data Allowed to Change Stop Condition DS21160G-page 7 24LC21A FIGURE 3-5: BUS TIMING START/STOP SCL VHYS THD:STA TSU:STO TSU:STA SDA Start FIGURE 3-6: Stop BUS TIMING DATA TF TR THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT THD:STA SDA IN TSU:STO TSP TBUF TAA TAA SDA OUT 3.1.6 FIGURE 3-7: SLAVE ADDRESS After generating a Start condition, the bus master transmits the slave address consisting of a 7-bit device code (1010000) for the 24LC21A. Start Read/Write The eighth bit of slave address determines whether the master device wants to read or write to the 24LC21A (Figure 3-7). The 24LC21A monitors the bus for its corresponding slave address continuously. It generates an Acknowledge bit if the slave address was true and it is not in a programming mode. Operation Slave Address R/W Read Write 1010000 1010000 1 0 DS21160G-page 8 CONTROL BYTE ALLOCATION R/W Slave Address 1 0 1 0 0 0 A 0 © 2008 Microchip Technology Inc. 24LC21A 4.0 WRITE OPERATION 4.1 Byte Write Following the start signal from the master, the slave address (four bits), three zero bits (000) and the R/W bit which is a logic low are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the Address Pointer of the 24LC21A. After receiving another acknowledge signal from the 24LC21A the master device will transmit the data word to be written into the addressed memory location. The 24LC21A acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24LC21A will not generate acknowledge signals (Figure 4-1). It is required that VCLK be held at a logic high level during command and data transfer in order to program the device. This applies to both byte write and page write operation. Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high-to-low during the self-timed program operation will not halt programming of the device. © 2008 Microchip Technology Inc. 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24LC21A in the same way as in a byte write. But instead of generating a Stop condition the master transmits up to eight data bytes to the 24LC21A which are temporarily stored in the onchip page buffer and will be written into the memory after the master has transmitted a Stop condition. After the receipt of each word, the three lower order Address Pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 4-3). It is required that VCLK be held at a logic high level during command and data transfer in order to program the device. This applies to both byte write and page write operation. Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high-to-low during the self-timed program operation will not halt programming of the device. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. DS21160G-page 9 24LC21A FIGURE 4-1: BYTE WRITE S T A R T Bus Activity Master SDA Line Word Address Control Byte S T O P Data S P A C K Bus Activity A C K A C K VCLK FIGURE 4-2: VCLK WRITE ENABLE TIMING SCL THD:STA SDA IN THD:STO VCLK TVHST FIGURE 4-3: PAGE WRITE Bus Activity Master S T A R T SDA Line S Bus Activity TSPVL Word Address Control Byte Data (n) S T O P Data n + 7 Data n + 1 P A C K A C K A C K A C K A C K VCLK DS21160G-page 10 © 2008 Microchip Technology Inc. 24LC21A 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 5-1 for the flow diagram. FIGURE 5-1: 6.0 WRITE PROTECTION When using the 24LC21A in the Bidirectional mode, the VCLK pin can be used as a write-protect control pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array. Connecting the VCLK pin to VSS would allow the 24LC21A to operate as a serial ROM, although this configuration would prevent using the device in the Transmit-Only mode. ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation © 2008 Microchip Technology Inc. DS21160G-page 11 24LC21A 7.0 READ OPERATION 7.3 Sequential Read Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read and sequential read. Sequential reads are initiated in the same way as a random read except that after the 24LC21A transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24LC21A to transmit the next sequentially addressed 8-bit word (Figure 7-3). 7.1 To provide sequential reads the 24LC21A contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. Current Address Read The 24LC21A contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LC21A issues an acknowledge and transmits the eight-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24LC21A discontinues transmission (Figure 7-1). FIGURE 7-1: Bus Activity Master SDA Line CURRENT ADDRESS READ S T A R T Control Byte 7.2 Noise Protection The 24LC21A employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SDA, SCL and VCLK inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. S T O P Data n S10100001 Bus Activity 7.4 P A C K N O A C K Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC21A as part of a write operation. After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LC21A will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24LC21A discontinues transmission (Figure 7-2). DS21160G-page 12 © 2008 Microchip Technology Inc. 24LC21A FIGURE 7-2: RANDOM READ S T A R T Bus Activity Master Control Byte S T A R T Word Address S 1 0 1 0 0 0 0 0 SDA Line FIGURE 7-3: S T O P Data n S 1 0 1 0 0 0 0 1 A C K BUS Activity Control Byte A C K P A C K N O A C K SEQUENTIAL READ Bus Activity Master Data n Control Byte Data n+2 Data n+1 S T O P Data n+X P SDA Line Bus Activity A C K © 2008 Microchip Technology Inc. A C K A C K A C K N O A C K DS21160G-page 13 24LC21A 8.0 PIN DESCRIPTIONS 8.1 SDA This pin is used to transfer addresses and data into and out of the device, when the device is in the Bidirectional mode. In the Transmit-Only mode, which only allows data to be read from the device, data is also transferred on the SDA pin. This pin is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 KΩ for 100 kHz, 2 KΩ for 400 kHz). For normal data transfer in the Bidirectional mode, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 8.2 SCL This pin is the clock input for the Bidirectional mode, and is used to synchronize data transfer to and from the device. It is also used as the signaling input to switch the device from the Transmit-Only mode to the Bidirectional mode. It must remain high for the chip to continue operation in the Transmit-Only mode. 8.3 VCLK This pin is the clock input for the Transmit-Only mode (DDC1). In the Transmit-Only mode, each bit is clocked out on the rising edge of this signal. In the Bidirectional mode, a high logic level is required on this pin to enable write capability. DS21160G-page 14 © 2008 Microchip Technology Inc. 24LC21A 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (3.90 mm) XXXXXXXX XXXXYYWW NNN Legend: XX...X T Y YY WW NNN e3 * Example: 24LC21A I/PNNN 0145 Example: 24LC21A I/SN0145 NNN Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). © 2008 Microchip Technology Inc. DS21160G-page 15 24LC21A           3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6&! '! 9'&! 7"')  %! 7,8. 7 7 7: ; < &  & &  = =   ##4 4!!   -  1!& &   = =  "# &  "# >#& .  - -  ##4>#& .   #& 9 * 9#>#& :   *+ 1, -    !"#$%&" '  ()"&'"!&) &#*&&&#   +%&, & !& - '! !#.#  &"#' #%!  & "! ! #%!  & "! !! &$#/ !#  '! #&   .0 1,21!'!   &$& "! **& "&&  !       * ,